#ifndef __SN8P2988__H
#define __SN8P2988__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	VREG2 = 0x85;
sbit	FDUMMY5 = 0x85:7;
sbit	FDUMMY4 = 0x85:6;
sbit	FDUMMY3 = 0x85:5;
sbit	FDUMMY2 = 0x85:4;
sbit	FDUMMY1 = 0x85:3;
sbit	FDUMMY0 = 0x85:2;
sbit	FACMSEL = 0x85:1;
sbit	FACMEN = 0x85:0;
sfr	PFLAG = 0x86;
sbit	FC = 0x86:2;
sbit	FDC = 0x86:1;
sbit	FZ = 0x86:0;
sfr	RBANK = 0x87;
sbit	FRBNKS3 = 0x87:3;
sbit	FRBNKS2 = 0x87:2;
sbit	FRBNKS1 = 0x87:1;
sbit	FRBNKS0 = 0x87:0;
sfr	WR0 = 0x88;
sfr	WR1 = 0x89;
sfr	WR2 = 0x8a;
sfr	URTX1 = 0x8b;
sbit	FUTX1EN = 0x8b:7;
sbit	FUTX1PEN = 0x8b:6;
sbit	FUTX1PS = 0x8b:5;
sbit	FUTX1BRK = 0x8b:4;
sbit	FURX1BZ = 0x8b:3;
sbit	FUTX1BZ = 0x8b:2;
sfr	URRX1 = 0x8c;
sbit	FURX1EN = 0x8c:7;
sbit	FURX1PEN = 0x8c:6;
sbit	FURX1PS = 0x8c:5;
sbit	FURX1PC = 0x8c:4;
sbit	FUFMER1 = 0x8c:3;
sbit	FURS12 = 0x8c:2;
sbit	FURS11 = 0x8c:1;
sbit	FURS10 = 0x8c:0;
sfr	URCR1 = 0x8d;
sfr	UTX1D = 0x8e;
sfr	URX1D = 0x8f;
sfr	VREG = 0x90;
sbit	FBGREN = 0x90:7;
sbit	FBGCHP = 0x90:6;
sbit	FAVEN = 0x90:5;
sbit	FAVESEL = 0x90:4;
sbit	FAVDDREN = 0x90:2;
sbit	FAVDDRSEL1 = 0x90:1;
sbit	FAVDDRSEL0 = 0x90:0;
sfr	CHS = 0x91;
sbit	FMUXP3 = 0x91:7;
sbit	FMUXP2 = 0x91:6;
sbit	FMUXP1 = 0x91:5;
sbit	FMUXP0 = 0x91:4;
sbit	FMUXN3 = 0x91:3;
sbit	FMUXN2 = 0x91:2;
sbit	FMUXN1 = 0x91:1;
sbit	FMUXN0 = 0x91:0;
sfr	AMPM = 0x92;
sbit	FAMPCKS2 = 0x92:7;
sbit	FAMPCKS1 = 0x92:6;
sbit	FAMPCKS0 = 0x92:5;
sbit	FPCHPEN = 0x92:4;
sbit	FGS2 = 0x92:3;
sbit	FGS1 = 0x92:2;
sbit	FGS0 = 0x92:1;
sbit	FAMPEN = 0x92:0;
sfr	ADCM1 = 0x93;
sbit	FRVS3 = 0x93:7;
sbit	FRVS2 = 0x93:6;
sbit	FRVS1 = 0x93:5;
sbit	FRVS0 = 0x93:4;
sbit	FACHPEN = 0x93:3;
sbit	FGX = 0x93:2;
sbit	FADGN = 0x93:1;
sbit	FADC1EN = 0x93:0;
sfr	ADCM2 = 0x94;
sbit	FADCKS = 0x94:7;
sbit	FOSR2 = 0x94:6;
sbit	FOSR1 = 0x94:5;
sbit	FOSR0 = 0x94:4;
sbit	FGR = 0x94:3;
sbit	FOFSEL1 = 0x94:2;
sbit	FOFSEL0 = 0x94:1;
sbit	FDRDY = 0x94:0;
sfr	LBTM = 0x95;
sbit	FLBTSEL3 = 0x95:5;
sbit	FLBTSEL2 = 0x95:4;
sbit	FLBTSEL1 = 0x95:3;
sbit	FLBTSEL0 = 0x95:2;
sbit	FLBTO = 0x95:1;
sbit	FLBTEN = 0x95:0;
sfr	ADCDH = 0x96;
sfr	ADCDM = 0x97;
sfr	ADCDL = 0x98;
sfr	TC0CH = 0x99;
sfr	TC0RH = 0x9a;
sfr	TC0DL = 0x9b;
sfr	TC0DH = 0x9c;
sfr	TC1CH = 0x9d;
sfr	TC1RH = 0x9e;
sfr	TC1DL = 0x9f;
sfr	ROMADRH = 0xa0;
sbit	FROMADR15 = 0xa0:7;
sbit	FROMADR13 = 0xa0:5;
sbit	FROMADR12 = 0xa0:4;
sbit	FROMADR11 = 0xa0:3;
sbit	FROMADR10 = 0xa0:2;
sbit	FROMADR9 = 0xa0:1;
sbit	FROMADR8 = 0xa0:0;
sfr	ROMADRL = 0xa1;
sbit	FROMADR7 = 0xa1:7;
sbit	FROMADR6 = 0xa1:6;
sbit	FROMADR5 = 0xa1:5;
sbit	FROMADR4 = 0xa1:4;
sbit	FROMADR3 = 0xa1:3;
sbit	FROMADR2 = 0xa1:2;
sbit	FROMADR1 = 0xa1:1;
sbit	FROMADR0 = 0xa1:0;
sfr	ROMDAH = 0xa2;
sbit	FROMDA15 = 0xa2:7;
sbit	FROMDA14 = 0xa2:6;
sbit	FROMDA13 = 0xa2:5;
sbit	FROMDA12 = 0xa2:4;
sbit	FROMDA11 = 0xa2:3;
sbit	FROMDA10 = 0xa2:2;
sbit	FROMDA9 = 0xa2:1;
sbit	FROMDA8 = 0xa2:0;
sfr	ROMDAL = 0xa3;
sbit	FROMDA7 = 0xa3:7;
sbit	FROMDA6 = 0xa3:6;
sbit	FROMDA5 = 0xa3:5;
sbit	FROMDA4 = 0xa3:4;
sbit	FROMDA3 = 0xa3:3;
sbit	FROMDA2 = 0xa3:2;
sbit	FROMDA1 = 0xa3:1;
sbit	FROMDA0 = 0xa3:0;
sfr	DA1M = 0xa4;
sbit	FDA1EN = 0xa4:7;
sbit	FDA1REF1 = 0xa4:5;
sbit	FDA1REF0 = 0xa4:4;
sbit	FDA1B11 = 0xa4:3;
sbit	FDA1B10 = 0xa4:2;
sbit	FDA1B9 = 0xa4:1;
sbit	FDA1B8 = 0xa4:0;
sfr	DA1BL = 0xa5;
sbit	FDA1B7 = 0xa5:7;
sbit	FDA1B6 = 0xa5:6;
sbit	FDA1B5 = 0xa5:5;
sbit	FDA1B4 = 0xa5:4;
sbit	FDA1B3 = 0xa5:3;
sbit	FDA1B2 = 0xa5:2;
sbit	FDA1B1 = 0xa5:1;
sbit	FDA1B0 = 0xa5:0;
sfr	MSPSTAT = 0xa6;
sbit	FCKE = 0xa6:6;
sbit	FD_A = 0xa6:5;
sbit	FP = 0xa6:4;
sbit	FS = 0xa6:3;
sbit	FRED_WRT = 0xa6:2;
sbit	FBF = 0xa6:0;
sfr	MSPM1 = 0xa7;
sbit	FWCOL = 0xa7:7;
sbit	FMSPOV = 0xa7:6;
sbit	FMSPENB = 0xa7:5;
sbit	FCKP = 0xa7:4;
sbit	FSLRXCKP = 0xa7:3;
sbit	FMSPWK = 0xa7:2;
sbit	FMSPC = 0xa7:0;
sfr	MSPM2 = 0xa8;
sbit	FGCEN = 0xa8:7;
sbit	FACKSTAT = 0xa8:6;
sbit	FACKDT = 0xa8:5;
sbit	FACKEN = 0xa8:4;
sbit	FRCEN = 0xa8:3;
sbit	FPEN = 0xa8:2;
sbit	FRSEN = 0xa8:1;
sbit	FSEN = 0xa8:0;
sfr	MSPBUF = 0xa9;
sfr	MSPADR = 0xaa;
sfr	TC1DH = 0xab;
sfr	TC2CH = 0xac;
sfr	TC2RH = 0xad;
sfr	TC2DL0 = 0xae;
sfr	TC2DH0 = 0xaf;
sfr	LCDM1 = 0xb0;
sbit	FDUTY1 = 0xb0:7;
sbit	FDUTY0 = 0xb0:6;
sbit	FLCDMOD1 = 0xb0:5;
sbit	FLCDMOD0 = 0xb0:4;
sbit	FLCDEN = 0xb0:3;
sbit	FLCDBIAS = 0xb0:2;
sbit	FLCDRATE = 0xb0:1;
sbit	FLCDCLK = 0xb0:0;
sfr	LCDM2 = 0xb1;
sbit	FVAR1 = 0xb1:7;
sbit	FVAR0 = 0xb1:6;
sbit	FDISQ = 0xb1:5;
sbit	FLCDBNK = 0xb1:4;
sbit	FVPPINTL = 0xb1:3;
sbit	FVCP2 = 0xb1:2;
sbit	FVCP1 = 0xb1:1;
sbit	FVCP0 = 0xb1:0;
sfr	P2SEG = 0xb2;
sfr	P3SEG = 0xb3;
sfr	BZRM = 0xb4;
sbit	FBZREN = 0xb4:2;
sbit	FBZRCKS1 = 0xb4:1;
sbit	FBZRCKS0 = 0xb4:0;
sfr	P1SEG = 0xb5;
sfr	P4SEG = 0xb6;
sfr	P5SEG = 0xb7;
sfr	OPM1 = 0xb8;
sbit	FSW3 = 0xb8:7;
sbit	FSW2 = 0xb8:6;
sbit	FSW1 = 0xb8:5;
sbit	FSW0 = 0xb8:4;
sbit	FOPA2CHP = 0xb8:3;
sbit	FOPA2EN = 0xb8:2;
sbit	FOPA1CHP = 0xb8:1;
sbit	FOPA1EN = 0xb8:0;
sfr	OPM2 = 0xb9;
sbit	FSW11 = 0xb9:7;
sbit	FSW10 = 0xb9:6;
sbit	FSW9 = 0xb9:5;
sbit	FSW8 = 0xb9:4;
sbit	FSW7 = 0xb9:3;
sbit	FSW6 = 0xb9:2;
sbit	FSW5 = 0xb9:1;
sbit	FSW4 = 0xb9:0;
sfr	ADM = 0xba;
sbit	FADC2EN = 0xba:7;
sbit	FADS = 0xba:6;
sbit	FEOC = 0xba:5;
sbit	FCHS3 = 0xba:3;
sbit	FCHS2 = 0xba:2;
sbit	FCHS1 = 0xba:1;
sbit	FCHS0 = 0xba:0;
sfr	ADB = 0xbb;
sbit	FADB11 = 0xbb:7;
sbit	FADB10 = 0xbb:6;
sbit	FADB9 = 0xbb:5;
sbit	FADB8 = 0xbb:4;
sbit	FADB7 = 0xbb:3;
sbit	FADB6 = 0xbb:2;
sbit	FADB5 = 0xbb:1;
sbit	FADB4 = 0xbb:0;
sfr	ADR = 0xbc;
sbit	FLVBAT = 0xbc:7;
sbit	FGCHS = 0xbc:6;
sbit	FADCKS1 = 0xbc:5;
sbit	FADCKS0 = 0xbc:4;
sbit	FADB3 = 0xbc:3;
sbit	FADB2 = 0xbc:2;
sbit	FADB1 = 0xbc:1;
sbit	FADB0 = 0xbc:0;
sfr	LCDM3 = 0xbd;
sbit	FBGM = 0xbd:1;
sbit	FLCDMODE = 0xbd:0;
sfr	ADT = 0xbe;
sbit	FAD2VREF = 0xbe:5;
sbit	FADT4 = 0xbe:4;
sbit	FADT3 = 0xbe:3;
sbit	FADT2 = 0xbe:2;
sbit	FADT1 = 0xbe:1;
sbit	FADT0 = 0xbe:0;
sfr	PEDGE = 0xbf;
sbit	FP01G1 = 0xbf:6;
sbit	FP01G0 = 0xbf:5;
sbit	FP00G1 = 0xbf:4;
sbit	FP00G0 = 0xbf:3;
sfr	P0M = 0xc0;
sbit	FP07M = 0xc0:7;
sbit	FP06M = 0xc0:6;
sbit	FP05M = 0xc0:5;
sbit	FP04M = 0xc0:4;
sbit	FP03M = 0xc0:3;
sbit	FP02M = 0xc0:2;
sbit	FP01M = 0xc0:1;
sbit	FP00M = 0xc0:0;
sfr	P1M = 0xc1;
sbit	FP17M = 0xc1:7;
sbit	FP16M = 0xc1:6;
sbit	FP15M = 0xc1:5;
sbit	FP14M = 0xc1:4;
sbit	FP13M = 0xc1:3;
sbit	FP12M = 0xc1:2;
sbit	FP11M = 0xc1:1;
sbit	FP10M = 0xc1:0;
sfr	P2M = 0xc2;
sbit	FP27M = 0xc2:7;
sbit	FP26M = 0xc2:6;
sbit	FP25M = 0xc2:5;
sbit	FP24M = 0xc2:4;
sbit	FP23M = 0xc2:3;
sbit	FP22M = 0xc2:2;
sbit	FP21M = 0xc2:1;
sbit	FP20M = 0xc2:0;
sfr	P3M = 0xc3;
sbit	FP37M = 0xc3:7;
sbit	FP36M = 0xc3:6;
sbit	FP35M = 0xc3:5;
sbit	FP34M = 0xc3:4;
sbit	FP33M = 0xc3:3;
sbit	FP32M = 0xc3:2;
sbit	FP31M = 0xc3:1;
sbit	FP30M = 0xc3:0;
sfr	P4M = 0xc4;
sbit	FP47M = 0xc4:7;
sbit	FP46M = 0xc4:6;
sbit	FP45M = 0xc4:5;
sbit	FP44M = 0xc4:4;
sbit	FP43M = 0xc4:3;
sbit	FP42M = 0xc4:2;
sbit	FP41M = 0xc4:1;
sbit	FP40M = 0xc4:0;
sfr	P5M = 0xc5;
sbit	FP57M = 0xc5:7;
sbit	FP56M = 0xc5:6;
sbit	FP55M = 0xc5:5;
sbit	FP54M = 0xc5:4;
sbit	FP53M = 0xc5:3;
sbit	FP52M = 0xc5:2;
sbit	FP51M = 0xc5:1;
sbit	FP50M = 0xc5:0;
sfr	INTRQ1 = 0xc6;
sbit	FMSPIRQ = 0xc6:4;
sbit	FTC2IRQ = 0xc6:3;
sbit	FTC1IRQ = 0xc6:2;
sbit	FTC0IRQ = 0xc6:1;
sbit	FT0IRQ = 0xc6:0;
sfr	INTEN1 = 0xc7;
sbit	FMSPIEN = 0xc7:4;
sbit	FTC2IEN = 0xc7:3;
sbit	FTC1IEN = 0xc7:2;
sbit	FTC0IEN = 0xc7:1;
sbit	FT0IEN = 0xc7:0;
sfr	INTRQ0 = 0xc8;
sbit	FADC2IRQ = 0xc8:7;
sbit	FADC1IRQ = 0xc8:6;
sbit	FURX1IRQ = 0xc8:5;
sbit	FUTX1IRQ = 0xc8:4;
sbit	FURX0IRQ = 0xc8:3;
sbit	FUTX0IRQ = 0xc8:2;
sbit	FP01IRQ = 0xc8:1;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN0 = 0xc9;
sbit	FADC2IEN = 0xc9:7;
sbit	FADC1IEN = 0xc9:6;
sbit	FURX1IEN = 0xc9:5;
sbit	FUTX1IEN = 0xc9:4;
sbit	FURX0IEN = 0xc9:3;
sbit	FUTX0IEN = 0xc9:2;
sbit	FP01IEN = 0xc9:1;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	FRQH = 0xcb;
sbit	FCKEN = 0xcb:7;
sbit	FFRQ9 = 0xcb:1;
sbit	FFRQ8 = 0xcb:0;
sfr	WDTR = 0xcc;
sfr	FRQL = 0xcd;
sbit	FFRQ7 = 0xcd:7;
sbit	FFRQ6 = 0xcd:6;
sbit	FFRQ5 = 0xcd:5;
sbit	FFRQ4 = 0xcd:4;
sbit	FFRQ3 = 0xcd:3;
sbit	FFRQ2 = 0xcd:2;
sbit	FFRQ1 = 0xcd:1;
sbit	FFRQ0 = 0xcd:0;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sbit	FPC13 = 0xcf:5;
sbit	FPC12 = 0xcf:4;
sbit	FPC11 = 0xcf:3;
sbit	FPC10 = 0xcf:2;
sbit	FPC9 = 0xcf:1;
sbit	FPC8 = 0xcf:0;
sfr	P0 = 0xd0;
sbit	FP07 = 0xd0:7;
sbit	FP06 = 0xd0:6;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP17 = 0xd1:7;
sbit	FP16 = 0xd1:6;
sbit	FP15 = 0xd1:5;
sbit	FP14 = 0xd1:4;
sbit	FP13 = 0xd1:3;
sbit	FP12 = 0xd1:2;
sbit	FP11 = 0xd1:1;
sbit	FP10 = 0xd1:0;
sfr	P2 = 0xd2;
sbit	FP27 = 0xd2:7;
sbit	FP26 = 0xd2:6;
sbit	FP25 = 0xd2:5;
sbit	FP24 = 0xd2:4;
sbit	FP23 = 0xd2:3;
sbit	FP22 = 0xd2:2;
sbit	FP21 = 0xd2:1;
sbit	FP20 = 0xd2:0;
sfr	P3 = 0xd3;
sbit	FP37 = 0xd3:7;
sbit	FP36 = 0xd3:6;
sbit	FP35 = 0xd3:5;
sbit	FP34 = 0xd3:4;
sbit	FP33 = 0xd3:3;
sbit	FP32 = 0xd3:2;
sbit	FP31 = 0xd3:1;
sbit	FP30 = 0xd3:0;
sfr	P4 = 0xd4;
sbit	FP47 = 0xd4:7;
sbit	FP46 = 0xd4:6;
sbit	FP45 = 0xd4:5;
sbit	FP44 = 0xd4:4;
sbit	FP43 = 0xd4:3;
sbit	FP42 = 0xd4:2;
sbit	FP41 = 0xd4:1;
sbit	FP40 = 0xd4:0;
sfr	P5 = 0xd5;
sbit	FP57 = 0xd5:7;
sbit	FP56 = 0xd5:6;
sbit	FP55 = 0xd5:5;
sbit	FP54 = 0xd5:4;
sbit	FP53 = 0xd5:3;
sbit	FP52 = 0xd5:2;
sbit	FP51 = 0xd5:1;
sbit	FP50 = 0xd5:0;
sfr	P4UR = 0xd6;
sbit	FP47R = 0xd6:7;
sbit	FP46R = 0xd6:6;
sbit	FP45R = 0xd6:5;
sbit	FP44R = 0xd6:4;
sbit	FP43R = 0xd6:3;
sbit	FP42R = 0xd6:2;
sbit	FP41R = 0xd6:1;
sbit	FP40R = 0xd6:0;
sfr	P5UR = 0xd7;
sbit	FP57R = 0xd7:7;
sbit	FP56R = 0xd7:6;
sbit	FP55R = 0xd7:5;
sbit	FP54R = 0xd7:4;
sbit	FP53R = 0xd7:3;
sbit	FP52R = 0xd7:2;
sbit	FP51R = 0xd7:1;
sbit	FP50R = 0xd7:0;
sfr	T0M = 0xd8;
sbit	FT0EN = 0xd8:7;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE0 = 0xd8:4;
sbit	FTC0GN = 0xd8:1;
sbit	FT0TB = 0xd8:0;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FTC0ENB = 0xda:7;
sbit	FTC0RATE2 = 0xda:6;
sbit	FTC0RATE1 = 0xda:5;
sbit	FTC0RATE0 = 0xda:4;
sbit	FTC0CKS1 = 0xda:3;
sbit	FTC0CKS0 = 0xda:2;
sbit	FPWM0OUT = 0xda:1;
sfr	TC0CL = 0xdb;
sfr	TC0RL = 0xdc;
sfr	P2UR = 0xdd;
sbit	FP27R = 0xdd:7;
sbit	FP26R = 0xdd:6;
sbit	FP25R = 0xdd:5;
sbit	FP24R = 0xdd:4;
sbit	FP23R = 0xdd:3;
sbit	FP22R = 0xdd:2;
sbit	FP21R = 0xdd:1;
sbit	FP20R = 0xdd:0;
sfr	P3UR = 0xde;
sbit	FP37R = 0xde:7;
sbit	FP36R = 0xde:6;
sbit	FP35R = 0xde:5;
sbit	FP34R = 0xde:4;
sbit	FP33R = 0xde:3;
sbit	FP32R = 0xde:2;
sbit	FP31R = 0xde:1;
sbit	FP30R = 0xde:0;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sbit	FP07R = 0xe0:7;
sbit	FP06R = 0xe0:6;
sbit	FP05R = 0xe0:5;
sbit	FP04R = 0xe0:4;
sbit	FP03R = 0xe0:3;
sbit	FP02R = 0xe0:2;
sbit	FP01R = 0xe0:1;
sbit	FP00R = 0xe0:0;
sfr	P1UR = 0xe1;
sbit	FP17R = 0xe1:7;
sbit	FP16R = 0xe1:6;
sbit	FP15R = 0xe1:5;
sbit	FP14R = 0xe1:4;
sbit	FP13R = 0xe1:3;
sbit	FP12R = 0xe1:2;
sbit	FP11R = 0xe1:1;
sbit	FP10R = 0xe1:0;
sfr	URTX0 = 0xe2;
sbit	FUTX0EN = 0xe2:7;
sbit	FUTX0PEN = 0xe2:6;
sbit	FUTX0PS = 0xe2:5;
sbit	FUTX0BRK = 0xe2:4;
sbit	FURX0BZ = 0xe2:3;
sbit	FUTX0BZ = 0xe2:2;
sfr	URRX0 = 0xe3;
sbit	FURX0EN = 0xe3:7;
sbit	FURX0PEN = 0xe3:6;
sbit	FURX0PS = 0xe3:5;
sbit	FURX0PC = 0xe3:4;
sbit	FUFMER0 = 0xe3:3;
sbit	FURS02 = 0xe3:2;
sbit	FURS01 = 0xe3:1;
sbit	FURS00 = 0xe3:0;
sfr	URCR0 = 0xe4;
sfr	UTX0D = 0xe5;
sfr	URX0D = 0xe6;
sfr	_YZ = 0xe7;
sfr	_HL = 0xe8;
sfr	TC1M = 0xe9;
sbit	FTC1ENB = 0xe9:7;
sbit	FTC1RATE2 = 0xe9:6;
sbit	FTC1RATE1 = 0xe9:5;
sbit	FTC1RATE0 = 0xe9:4;
sbit	FTC1CKS1 = 0xe9:3;
sbit	FTC1CKS0 = 0xe9:2;
sbit	FPWM1OUT = 0xe9:1;
sfr	TC1CL = 0xea;
sfr	TC1RL = 0xeb;
sfr	TC2M = 0xec;
sbit	FTC2ENB = 0xec:7;
sbit	FTC2RATE2 = 0xec:6;
sbit	FTC2RATE1 = 0xec:5;
sbit	FTC2RATE0 = 0xec:4;
sbit	FTC2CKS1 = 0xec:3;
sbit	FTC2CKS0 = 0xec:2;
sbit	FTC2MOD1 = 0xec:1;
sbit	FTC2MOD0 = 0xec:0;
sfr	TC2CL = 0xed;
sfr	TC2RL = 0xee;
sfr	PWMCTL = 0xef;
sbit	FPWM9OUT = 0xef:7;
sbit	FPWM8OUT = 0xef:6;
sbit	FPWM7OUT = 0xef:5;
sbit	FPWM6OUT = 0xef:4;
sbit	FPWM5OUT = 0xef:3;
sbit	FPWM4OUT = 0xef:2;
sbit	FPWM3OUT = 0xef:1;
sbit	FPWM2OUT = 0xef:0;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;

sfr	TC2DL1 = 0xe00;
sbit	FTC2DL17 = 0xe00:7;
sbit	FTC2DL16 = 0xe00:6;
sbit	FTC2DL15 = 0xe00:5;
sbit	FTC2DL14 = 0xe00:4;
sbit	FTC2DL13 = 0xe00:3;
sbit	FTC2DL12 = 0xe00:2;
sbit	FTC2DL11 = 0xe00:1;
sbit	FTC2DL10 = 0xe00:0;


sfr	TC2DH1 = 0xe01;
sbit	FTC2DH17 = 0xe01:7;
sbit	FTC2DH16 = 0xe01:6;
sbit	FTC2DH15 = 0xe01:5;
sbit	FTC2DH14 = 0xe01:4;
sbit	FTC2DH13 = 0xe01:3;
sbit	FTC2DH12 = 0xe01:2;
sbit	FTC2DH11 = 0xe01:1;
sbit	FTC2DH10 = 0xe01:0;


sfr	TC2DL2 = 0xe02;
sbit	FTC2DL27 = 0xe02:7;
sbit	FTC2DL26 = 0xe02:6;
sbit	FTC2DL25 = 0xe02:5;
sbit	FTC2DL24 = 0xe02:4;
sbit	FTC2DL23 = 0xe02:3;
sbit	FTC2DL22 = 0xe02:2;
sbit	FTC2DL21 = 0xe02:1;
sbit	FTC2DL20 = 0xe02:0;


sfr	TC2DH2 = 0xe03;
sbit	FTC2DH27 = 0xe03:7;
sbit	FTC2DH26 = 0xe03:6;
sbit	FTC2DH25 = 0xe03:5;
sbit	FTC2DH24 = 0xe03:4;
sbit	FTC2DH23 = 0xe03:3;
sbit	FTC2DH22 = 0xe03:2;
sbit	FTC2DH21 = 0xe03:1;
sbit	FTC2DH20 = 0xe03:0;


sfr	TC2DL3 = 0xe04;
sbit	FTC2DL37 = 0xe04:7;
sbit	FTC2DL36 = 0xe04:6;
sbit	FTC2DL35 = 0xe04:5;
sbit	FTC2DL34 = 0xe04:4;
sbit	FTC2DL33 = 0xe04:3;
sbit	FTC2DL32 = 0xe04:2;
sbit	FTC2DL31 = 0xe04:1;
sbit	FTC2DL30 = 0xe04:0;


sfr	TC2DH3 = 0xe05;
sbit	FTC2DH37 = 0xe05:7;
sbit	FTC2DH36 = 0xe05:6;
sbit	FTC2DH35 = 0xe05:5;
sbit	FTC2DH34 = 0xe05:4;
sbit	FTC2DH33 = 0xe05:3;
sbit	FTC2DH32 = 0xe05:2;
sbit	FTC2DH31 = 0xe05:1;
sbit	FTC2DH30 = 0xe05:0;


sfr	TC2DL4 = 0xe06;
sbit	FTC2DL47 = 0xe06:7;
sbit	FTC2DL46 = 0xe06:6;
sbit	FTC2DL45 = 0xe06:5;
sbit	FTC2DL44 = 0xe06:4;
sbit	FTC2DL43 = 0xe06:3;
sbit	FTC2DL42 = 0xe06:2;
sbit	FTC2DL41 = 0xe06:1;
sbit	FTC2DL40 = 0xe06:0;


sfr	TC2DH4 = 0xe07;
sbit	FTC2DH47 = 0xe07:7;
sbit	FTC2DH46 = 0xe07:6;
sbit	FTC2DH45 = 0xe07:5;
sbit	FTC2DH44 = 0xe07:4;
sbit	FTC2DH43 = 0xe07:3;
sbit	FTC2DH42 = 0xe07:2;
sbit	FTC2DH41 = 0xe07:1;
sbit	FTC2DH40 = 0xe07:0;


sfr	TC2DL5 = 0xe08;
sbit	FTC2DL57 = 0xe08:7;
sbit	FTC2DL56 = 0xe08:6;
sbit	FTC2DL55 = 0xe08:5;
sbit	FTC2DL54 = 0xe08:4;
sbit	FTC2DL53 = 0xe08:3;
sbit	FTC2DL52 = 0xe08:2;
sbit	FTC2DL51 = 0xe08:1;
sbit	FTC2DL50 = 0xe08:0;


sfr	TC2DH5 = 0xe09;
sbit	FTC2DH57 = 0xe09:7;
sbit	FTC2DH56 = 0xe09:6;
sbit	FTC2DH55 = 0xe09:5;
sbit	FTC2DH54 = 0xe09:4;
sbit	FTC2DH53 = 0xe09:3;
sbit	FTC2DH52 = 0xe09:2;
sbit	FTC2DH51 = 0xe09:1;
sbit	FTC2DH50 = 0xe09:0;


sfr	TC2DL6 = 0xe0a;
sbit	FTC2DL67 = 0xe0a:7;
sbit	FTC2DL66 = 0xe0a:6;
sbit	FTC2DL65 = 0xe0a:5;
sbit	FTC2DL64 = 0xe0a:4;
sbit	FTC2DL63 = 0xe0a:3;
sbit	FTC2DL62 = 0xe0a:2;
sbit	FTC2DL61 = 0xe0a:1;
sbit	FTC2DL60 = 0xe0a:0;


sfr	TC2DH6 = 0xe0b;
sbit	FTC2DH67 = 0xe0b:7;
sbit	FTC2DH66 = 0xe0b:6;
sbit	FTC2DH65 = 0xe0b:5;
sbit	FTC2DH64 = 0xe0b:4;
sbit	FTC2DH63 = 0xe0b:3;
sbit	FTC2DH62 = 0xe0b:2;
sbit	FTC2DH61 = 0xe0b:1;
sbit	FTC2DH60 = 0xe0b:0;


sfr	TC2DL7 = 0xe0c;
sbit	FTC2DL77 = 0xe0c:7;
sbit	FTC2DL76 = 0xe0c:6;
sbit	FTC2DL75 = 0xe0c:5;
sbit	FTC2DL74 = 0xe0c:4;
sbit	FTC2DL73 = 0xe0c:3;
sbit	FTC2DL72 = 0xe0c:2;
sbit	FTC2DL71 = 0xe0c:1;
sbit	FTC2DL70 = 0xe0c:0;


sfr	TC2DH7 = 0xe0d;
sbit	FTC2DH77 = 0xe0d:7;
sbit	FTC2DH76 = 0xe0d:6;
sbit	FTC2DH75 = 0xe0d:5;
sbit	FTC2DH74 = 0xe0d:4;
sbit	FTC2DH73 = 0xe0d:3;
sbit	FTC2DH72 = 0xe0d:2;
sbit	FTC2DH71 = 0xe0d:1;
sbit	FTC2DH70 = 0xe0d:0;


sfr	DA2M = 0xe0e;
sbit	FDA2EN	 = 0xe0e:7;
sbit	FDA2REF1 = 0xe0e:5;
sbit	FDA2REF0 = 0xe0e:4;
sbit	FDA2B11	 = 0xe0e:3;
sbit	FDA2B10	 = 0xe0e:2;
sbit	FDA2B9	 = 0xe0e:1;
sbit	FDA2B8	 = 0xe0e:0;
	

sfr	DA2BL = 0xe0f;
sbit	FDA2B7 = 0xe0f:7;
sbit	FDA2B6 = 0xe0f:6;
sbit	FDA2B5 = 0xe0f:5;
sbit	FDA2B4 = 0xe0f:4;
sbit	FDA2B3 = 0xe0f:3;
sbit	FDA2B2 = 0xe0f:2;
sbit	FDA2B1 = 0xe0f:1;
sbit	FDA2B0 = 0xe0f:0;


sfr	OPM3 = 0xe10;
sbit	FOPCKS1 = 0xe10:1;
sbit	FOPCKS0 = 0xe10:0;
		
		
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SLowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#define ROMWRTVPP __asm{RomwrtVpp}
#define TEMP_CALIBRATION(arg0,arg1,arg2,arg3) __asm{Temp_calibration arg0,arg1,arg2,arg3}
#endif
