#ifndef __SZK671__H
#define __SZK671__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FLVD36 = 0x86:5;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sfr	TC0M = 0x88;
sbit	FTC0ENB = 0x88:7;
sbit	FTC0RATE2 = 0x88:6;
sbit	FTC0RATE1 = 0x88:5;
sbit	FTC0RATE0 = 0x88:4;
sbit	FALOAD0 = 0x88:2;
sfr	TC0C = 0x89;
sfr	TC0R = 0x8a;
sfr	CFS = 0x8e;
sbit	FIHRCOEN = 0x8e:7;
sfr	UDA = 0x90;
sbit	FUDE = 0x90:7;
sbit	FUDA6 = 0x90:6;
sbit	FUDA5 = 0x90:5;
sbit	FUDA4 = 0x90:4;
sbit	FUDA3 = 0x90:3;
sbit	FUDA2 = 0x90:2;
sbit	FUDA1 = 0x90:1;
sbit	FUDA0 = 0x90:0;
sfr	USTATUS = 0x91;
sbit	FBUS_RST = 0x91:4;
sbit	FSUSPEND = 0x91:3;
sbit	FEP0SETUP = 0x91:2;
sbit	FEP0IN = 0x91:1;
sbit	FEP0OUT = 0x91:0;
sfr	EP0OUT_CNT = 0x92;
sbit	FUEP0OC4 = 0x92:4;
sbit	FUEP0OC3 = 0x92:3;
sbit	FUEP0OC2 = 0x92:2;
sbit	FUEP0OC1 = 0x92:1;
sbit	FUEP0OC0 = 0x92:0;
sfr	USB_INT_EN = 0x93;
sbit	FREG_EN = 0x93:7;
sbit	FDP_PU_EN = 0x93:6;
sbit	FEP2_NAK_EN = 0x93:3;
sbit	FEP1_NAK_EN = 0x93:2;
sbit	FUE2D = 0x93:1;
sbit	FUE1D = 0x93:0;
sfr	EP_ACK = 0x94;
sbit	FEP2_NAK = 0x94:3;
sbit	FEP1_NAK = 0x94:2;
sbit	FEP2_ACK = 0x94:1;
sbit	FEP1_ACK = 0x94:0;
sfr	UE0R = 0x96;
sbit	FUE0E = 0x96:7;
sbit	FUE0M1 = 0x96:6;
sbit	FUE0M0 = 0x96:5;
sbit	FUE0C3 = 0x96:3;
sbit	FUE0C2 = 0x96:2;
sbit	FUE0C1 = 0x96:1;
sbit	FUE0C0 = 0x96:0;
sfr	UE1R = 0x97;
sbit	FUE1E = 0x97:7;
sbit	FUE1M1 = 0x97:6;
sbit	FUE1M0 = 0x97:5;
sbit	FUE1C3 = 0x97:3;
sbit	FUE1C2 = 0x97:2;
sbit	FUE1C1 = 0x97:1;
sbit	FUE1C0 = 0x97:0;
sfr	UE2R = 0x98;
sbit	FUE2E = 0x98:7;
sbit	FUE2M1 = 0x98:6;
sbit	FUE2M0 = 0x98:5;
sbit	FUE2C3 = 0x98:3;
sbit	FUE2C2 = 0x98:2;
sbit	FUE2C1 = 0x98:1;
sbit	FUE2C0 = 0x98:0;
sfr	UPID = 0xab;
sbit	FEP0OUT_EN = 0xab:7;
sbit	FUBDE = 0xab:2;
sbit	FDDP = 0xab:1;
sbit	FDDN = 0xab:0;
sfr	UTOGGLE = 0xac;
sbit	FEP2_DATA01 = 0xac:1;
sbit	FEP1_DATA01 = 0xac:0;
sfr	UNDT_EN = 0xad;
sfr	UNDT = 0xae;
sbit	FNDT = 0xae:0;
sfr	EP0_STALL = 0xb0;
sbit	FEP0_OUT_STALL = 0xb0:1;
sbit	FEP0_IN_STALL = 0xb0:0;
sfr	P0M = 0xb8;
sbit	FP07M = 0xb8:7;
sbit	FP06M = 0xb8:6;
sbit	FP05M = 0xb8:5;
sbit	FP04M = 0xb8:4;
sbit	FP03M = 0xb8:3;
sbit	FP02M = 0xb8:2;
sbit	FP01M = 0xb8:1;
sbit	FP00M = 0xb8:0;
sfr	PEDGE = 0xbf;
sbit	FP00G1 = 0xbf:1;
sbit	FP00G0 = 0xbf:0;
sfr	P1M = 0xc1;
sbit	FP17M = 0xc1:7;
sbit	FP16M = 0xc1:6;
sbit	FP15M = 0xc1:5;
sbit	FP14M = 0xc1:4;
sbit	FP13M = 0xc1:3;
sbit	FP12M = 0xc1:2;
sbit	FP11M = 0xc1:1;
sbit	FP10M = 0xc1:0;
sfr	P2M = 0xc2;
sbit	FP27M = 0xc2:7;
sbit	FP26M = 0xc2:6;
sbit	FP25M = 0xc2:5;
sbit	FP24M = 0xc2:4;
sbit	FP23M = 0xc2:3;
sbit	FP22M = 0xc2:2;
sbit	FP21M = 0xc2:1;
sbit	FP20M = 0xc2:0;
sfr	P3M = 0xc3;
sbit	FP36M = 0xc3:6;
sbit	FP35M = 0xc3:5;
sbit	FP34M = 0xc3:4;
sbit	FP33M = 0xc3:3;
sbit	FP32M = 0xc3:2;
sbit	FP31M = 0xc3:1;
sbit	FP30M = 0xc3:0;
sfr	P5M = 0xc5;
sbit	FP55M = 0xc5:5;
sbit	FP54M = 0xc5:4;
sbit	FP53M = 0xc5:3;
sbit	FP52M = 0xc5:2;
sbit	FP51M = 0xc5:1;
sbit	FP50M = 0xc5:0;
sfr	INTRQ = 0xc8;
sbit	FNDTIRQ = 0xc8:7;
sbit	FUSBIRQ = 0xc8:6;
sbit	FTC0IRQ = 0xc8:5;
sbit	FWAKEIRQ = 0xc8:2;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN = 0xc9;
sbit	FNDTIEN = 0xc9:7;
sbit	FUSBIEN = 0xc9:6;
sbit	FTC0IEN = 0xc9:5;
sbit	FWAKEIEN = 0xc9:2;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP07 = 0xd0:7;
sbit	FP06 = 0xd0:6;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP17 = 0xd1:7;
sbit	FP16 = 0xd1:6;
sbit	FP15 = 0xd1:5;
sbit	FP14 = 0xd1:4;
sbit	FP13 = 0xd1:3;
sbit	FP12 = 0xd1:2;
sbit	FP11 = 0xd1:1;
sbit	FP10 = 0xd1:0;
sfr	P2 = 0xd2;
sbit	FP27 = 0xd2:7;
sbit	FP26 = 0xd2:6;
sbit	FP25 = 0xd2:5;
sbit	FP24 = 0xd2:4;
sbit	FP23 = 0xd2:3;
sbit	FP22 = 0xd2:2;
sbit	FP21 = 0xd2:1;
sbit	FP20 = 0xd2:0;
sfr	P3 = 0xd3;
sbit	FP37 = 0xd3:7;
sbit	FP36 = 0xd3:6;
sbit	FP35 = 0xd3:5;
sbit	FP34 = 0xd3:4;
sbit	FP33 = 0xd3:3;
sbit	FP32 = 0xd3:2;
sbit	FP31 = 0xd3:1;
sbit	FP30 = 0xd3:0;
sfr	P5 = 0xd5;
sbit	FP55 = 0xd5:5;
sbit	FP54 = 0xd5:4;
sbit	FP53 = 0xd5:3;
sbit	FP52 = 0xd5:2;
sbit	FP51 = 0xd5:1;
sbit	FP50 = 0xd5:0;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sfr	P1UR = 0xe1;
sfr	P2UR = 0xe2;
sfr	P3UR = 0xe3;
sfr	P5UR = 0xe5;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	NDT_HW = 0xe8;
sbit	EFT_FLAG = 0xe8:0;
sbit	NDT_ENB = 0xe8:1;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#endif
