<?xml version="1.0" encoding="UTF-8"?>
<chip>
	<configure-file-ver>1.0</configure-file-ver>
	<chip-name>HS16F2612</chip-name>
	<chip-classes>Flash</chip-classes>
	<chip-id>CC</chip-id>
	<chip-id-debug>fc36</chip-id-debug>
	<chip-ver>0</chip-ver>
	<ccs-file-ver>4</ccs-file-ver>
	<ram-start-addr>0</ram-start-addr>
	<ram-size>256</ram-size>
	<otp-body-size>2048</otp-body-size>
	<user-rom-size>2040</user-rom-size>
	<reset-addr>0</reset-addr>
	<stack-level>8</stack-level>
	<config-word-count>5</config-word-count>
	<max-breakpoint>4</max-breakpoint>
	<asm-inc>$(DevEnvDir)\asm_inc\$(ChipName).inc</asm-inc>
	<clang-inc>$(DevEnvDir)\include\$(ChipName).h</clang-inc>		
	<description></description>
	<rams>
		<ram start-addr="0" length="512">
			<ram-segment start-addr="00" size="32" write-addr="00" read-addr="00" value-addr="00" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="20" size="80" write-addr="20" read-addr="20" value-addr="20" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="70" size="16" write-addr="70" read-addr="70" value-addr="70" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="80" size="32" write-addr="100" read-addr="100" value-addr="80" visiable="false" bank="1"></ram-segment>
			<ram-segment start-addr="a0" size="80" write-addr="120" read-addr="120" value-addr="a0" visiable="true" bank="1"></ram-segment>	
			<ram-segment start-addr="f0" size="16" write-addr="170" read-addr="170" value-addr="f0" visiable="true" bank="1"></ram-segment>	
			<ram-segment start-addr="100" size="32" write-addr="200" read-addr="200" value-addr="100" visiable="false" bank="2"></ram-segment>	
			<ram-segment start-addr="170" size="16" write-addr="270" read-addr="270" value-addr="170" visiable="true" bank="2"></ram-segment>		
			<ram-segment start-addr="180" size="32" write-addr="300" read-addr="300" value-addr="180" visiable="false" bank="3"></ram-segment>			
			<ram-segment start-addr="1f0" size="16" write-addr="370" read-addr="370" value-addr="1f0" visiable="true" bank="3"></ram-segment>				
			<ram-segment start-addr="1ff0" size="3" write-addr="1ff0" read-addr="1ff0" value-addr="1ff0" visiable="false" bank="-1"></ram-segment>				
		</ram>	
	</rams>
	<configs>
		<config-word index="0" or-value="0000" and-value="ffff" mapto="0"></config-word>
		<config-word index="1" or-value="0000" and-value="ffff" mapto="1"></config-word>	
		<config-word index="2" or-value="0000" and-value="ffff" mapto="3"></config-word>	
		<config-word index="3" or-value="0000" and-value="ffff" mapto="2"></config-word>			

		<config-item name="Pin PA5 Function" width="1" offset="12" default-value="0" enable="true" config-index="0">
			<config-item-value name="As RESET Pin" value="1"></config-item-value>
			<config-item-value name="As IO" value="0"></config-item-value>
			<description>PA5功能</description>
		</config-item>
		<config-item name="PWRT" width="3" offset="8" default-value="3" enable="true" config-index="0">
			<config-item-value name="PWRT=WDT=16ms" value="0"></config-item-value>
			<config-item-value name="PWRT=WDT=4ms" value="1"></config-item-value>
			<config-item-value name="PWRT=WDT=256ms" value="2"></config-item-value>
			<config-item-value name="PWRT=WDT=64ms" value="3"></config-item-value>
			<config-item-value name="PWRT=5ms,WDT=16ms" value="4"></config-item-value>
			<config-item-value name="PWRT=5ms,WDT=4ms" value="5"></config-item-value>
			<config-item-value name="PWRT=5ms,WDT=256ms" value="6"></config-item-value>
			<config-item-value name="PWRT=5ms,WDT=64ms" value="7"></config-item-value>
			<description>PWRT</description>
		</config-item>	
		<config-item name="LVR" width="3" offset="3" default-value="3" enable="true" config-index="0">
			<config-item-value name="Disable(1.65v)" value="0"></config-item-value>
			<config-item-value name="2.0v" value="1"></config-item-value>
			<config-item-value name="2.2v" value="2"></config-item-value>
			<config-item-value name="2.4v" value="3"></config-item-value>
			<config-item-value name="2.6v" value="4"></config-item-value>
			<config-item-value name="3.6v" value="5"></config-item-value>
			<description>当ENVDDL选择disable并且分频选择2分频时，LVR只能选择V2.0及以上；
			当ENVDDL选择enable，无论选择任何分频，LVR只能选择V2.0及以上
			</description>
		</config-item>	
		<config-item name="OSC" width="3" offset="0" default-value="0" enable="true" config-index="0">
			<config-item-value name="IRC" value="0"></config-item-value>
			<config-item-value name="IRC and RTC" value="4"></config-item-value>
			<description>
			IRC:内部高速RC
			IRC and RTC:内部高速RC与外部低速32.768Khz晶振共同有效
			</description>
		</config-item>	
		
		<config-item name="ENVDDL" width="1" offset="15" default-value="1" enable="true" config-index="1">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>自动锁存数据</description>
		</config-item>	
		<!--		
		<config-item name="CE_FL" width="1" offset="12" default-value="0" enable="true" config-index="1">
			<config-item-value name="always high" value="0"></config-item-value>
			<config-item-value name="following read" value="1"></config-item-value>
			<description>在半周期，低功耗模式下</description>
		</config-item>
		-->
		<config-item name="LVR Filter" width="1" offset="11" default-value="0" enable="true" config-index="1">
			<config-item-value name="Enable" value="0"></config-item-value>
			<config-item-value name="Disable" value="1"></config-item-value>
			<description>默认滤波</description>
		</config-item>
		<config-item name="Read Cycle" width="1" offset="10" default-value="0" enable="true" config-index="1">
			<config-item-value name="Full" value="0"></config-item-value>
			<config-item-value name="Half" value="1"></config-item-value>
			<description>选择OTP的读周期，半周期可省电。
			当ENVDDL选择disable并且分频选择2分频时，读周期只能选择FULL；
			当ENVDDL选择enable，无论选择任何分频，读周期只能选择FULL
			</description>
		</config-item>
		
		<!--
		<config-item name="Low power" width="1" offset="8" default-value="0" enable="true" config-index="1">
			<config-item-value name="Normal" value="0"></config-item-value>
			<config-item-value name="Low power" value="1"></config-item-value>
			<description>当主频小于1M时，可选择低功耗模式</description>
		</config-item>	
		-->
		<config-item name="Port Read" width="1" offset="5" default-value="0" enable="true" config-index="1">
			<config-item-value name="Form register" value="0"></config-item-value>
			<config-item-value name="Form pins" value="1"></config-item-value>
			<description>指端口为输出时，读port口，从哪里读入的</description>
		</config-item>			
		<config-item name="Fsys" width="3" offset="2" default-value="1" enable="true" config-index="1">
			<config-item-value name="4'clock" value="0"></config-item-value>
			<config-item-value name="2'clock" value="1"></config-item-value>
			<config-item-value name="8'clock" value="2"></config-item-value>
			<config-item-value name="16'clock" value="3"></config-item-value>
			<config-item-value name="32'clock" value="4"></config-item-value>
			<config-item-value name="64'clock" value="5"></config-item-value>
			<config-item-value name="128'clock" value="6"></config-item-value>
			<config-item-value name="256'clock" value="7"></config-item-value>
			<description>系统分频</description>
		</config-item>				
		<config-item name="Protect" width="1" offset="1" default-value="0" enable="true" config-index="1">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>加密</description>
		</config-item>	
		<config-item name="Watch Dog" width="1" offset="13" default-value="0" enable="true" config-index="1">
			<config-item-value name="Disable" value="1"></config-item-value>
			<config-item-value name="Enable" value="0"></config-item-value>
			<description>看门狗</description>
		</config-item>	
		<config-item name="Debug pin" width="2" offset="14" default-value="2" enable="true" config-index="3">
			<config-item-value name="PA0/PA1为GPIO" value="0"></config-item-value>
			<config-item-value name="PA0/PA1为仿真脚" value="2"></config-item-value>
			<description>仿真脚控制，=10时，PA0(SCK)变成输入脚，且纯模拟输入功能关闭，PA1(SDA)可输入输出，输出时开漏关闭，输入时变成输入脚，且纯模拟功能关闭</description>
		</config-item>			
		<config-item name="Freq" width="1" offset="3" default-value="0" enable="true" config-index="7">
			<config-item-value name="16M" value="0"></config-item-value>
			<!--<config-item-value name="24M" value="1"></config-item-value>-->
			<description>系统频率</description>
		</config-item>				
	</configs>
	
	<sfrs>
		<sfr>
			<reg name="ACC" addr="1ff0" read-addr="1ff0" write-addr="1ff0" value-addr="1ff0" addr-visiable="false" bank="-1"></reg>
			<reg name="INDF" addr="00" read-addr="00" write-addr="00" value-addr="00" addr-visiable="true" bank="0"></reg>
			<reg name="TMR0" addr="01"  read-addr="01" write-addr="01" value-addr="01" addr-visiable="true" bank="0"></reg>
			<reg name="PCL" addr="02" read-addr="02" write-addr="02" value-addr="02" addr-visiable="true" bank="0"></reg>
			
			<reg name="STATUS" addr="03" read-addr="03" write-addr="03" value-addr="03" addr-visiable="true" bank="0">
				<bit name="C" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="Z" offset="2"></bit>
				<bit name="PD" offset="3"></bit>
				<bit name="TO" offset="4"></bit>
				<bit name="RP0" offset="5"></bit>
				<bit name="RP1" offset="6"></bit>
				<bit name="IRP" offset="7"></bit>
			</reg>
			
			<reg name="FSR" addr="04"  read-addr="04" write-addr="04" value-addr="04" addr-visiable="true" bank="0"></reg>	
			<reg name="PORTA" addr="05"  read-addr="05" write-addr="05" value-addr="05" addr-visiable="true" bank="0"></reg>
			<reg name="PORTC" addr="07"  read-addr="07" write-addr="07" value-addr="07" addr-visiable="true" bank="0"></reg>
			<reg name="PCLATH" addr="0A"  read-addr="0a" write-addr="0a" value-addr="0a" addr-visiable="true" bank="0"></reg>
	
			<reg name="INTCON" addr="0b"  read-addr="0b" write-addr="0b" value-addr="0b" addr-visiable="true" bank="0">
				<bit name="PAIF" offset="0"></bit>
				<bit name="INTIF" offset="1"></bit>
				<bit name="T0IF" offset="2"></bit>	
				<bit name="PAIE" offset="3"></bit>	
				<bit name="INTIE" offset="4"></bit>	
				<bit name="T0IE" offset="5"></bit>	
				<bit name="PEIE" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>
	
			<reg name="PIR1" addr="0C"  read-addr="0c" write-addr="0c" value-addr="0c" addr-visiable="true" bank="0">
				<bit name="T1IF" offset="0"></bit>
				<bit name="P2IF" offset="1"></bit>
				<bit name="CCP1IF" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="ADCIF" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>
			
			<reg name="PRI2" addr="0D"  read-addr="0d" write-addr="0d" value-addr="0d" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="T3IF" offset="1"></bit>
				<bit name="T4IF" offset="2"></bit>	
				<bit name="T5IF" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="C1IF" offset="5"></bit>	
				<bit name="C2IF" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>
			
			<reg name="PCHCON" addr="12"  read-addr="12" write-addr="12" value-addr="12" addr-visiable="true" bank="0"></reg>
			<reg name="PCDCON" addr="13"  read-addr="13" write-addr="13" value-addr="13" addr-visiable="true" bank="0"></reg>
			<reg name="ADB1" addr="16"  read-addr="16" write-addr="16" value-addr="16" addr-visiable="true" bank="0"></reg>		
			<reg name="ADF0" addr="18"  read-addr="18" write-addr="18" value-addr="18" addr-visiable="true" bank="0"></reg>
			<reg name="ANSEL" addr="1A"  read-addr="1A" write-addr="1A" value-addr="1A" addr-visiable="true" bank="0"></reg>
						
			<reg name="ADM" addr="1B"  read-addr="1B" write-addr="1B" value-addr="1B" addr-visiable="true" bank="0">
				<bit name="CHS0" offset="0"></bit>
				<bit name="CHS1" offset="1"></bit>
				<bit name="CHS2" offset="2"></bit>	
				<bit name="CHS3" offset="3"></bit>	
				<bit name="GCHS" offset="4"></bit>	
				<bit name="EOC" offset="5"></bit>	
				<bit name="ADS" offset="6"></bit>
				<bit name="ADENB" offset="7"></bit>			
			</reg>			
			
			<reg name="ADB" addr="1C"  read-addr="1C" write-addr="1C" value-addr="1C" addr-visiable="true" bank="0"></reg>
			
			<reg name="ADR" addr="1D"  read-addr="1D" write-addr="1D" value-addr="1D" addr-visiable="true" bank="0">
				<bit name="ADB0" offset="0"></bit>
				<bit name="ADB1" offset="1"></bit>
				<bit name="ADB2" offset="2"></bit>	
				<bit name="ADB3" offset="3"></bit>	
				<bit name="ADCKS0" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="ADCKS1" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>		

			<reg name="ADT" addr="1E"  read-addr="1E" write-addr="1E" value-addr="1E" addr-visiable="true" bank="0">
				<bit name="ADT0" offset="0"></bit>
				<bit name="ADT1" offset="1"></bit>
				<bit name="ADT2" offset="2"></bit>	
				<bit name="ADT3" offset="3"></bit>	
				<bit name="ADTS0" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>		

			<reg name="VREF" addr="1F"  read-addr="1F" write-addr="1F" value-addr="1F" addr-visiable="true" bank="0">
				<bit name="VHS0" offset="0"></bit>
				<bit name="VHS1" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="EVHENB" offset="7"></bit>			
			</reg>	

			<reg name="OPTIONR" addr="81"  read-addr="180" write-addr="180" value-addr="81" addr-visiable="true" bank="1">
				<bit name="PS0" offset="0"></bit>
				<bit name="PS1" offset="1"></bit>
				<bit name="PS2" offset="2"></bit>	
				<bit name="PSA" offset="3"></bit>	
				<bit name="T0SE" offset="4"></bit>	
				<bit name="T0CS" offset="5"></bit>	
				<bit name="INTEDGE" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	

			<reg name="TRISA" addr="85"  read-addr="185" write-addr="185" value-addr="85" addr-visiable="true" bank="1"></reg>
			<reg name="TRISC" addr="87" read-addr="187" write-addr="187" value-addr="87" addr-visiable="true" bank="1"></reg>

			<reg name="PIE1" addr="8C" read-addr="18C" write-addr="18C" value-addr="8C" addr-visiable="true" bank="1">
				<bit name="T1IE" offset="0"></bit>
				<bit name="T2IE" offset="1"></bit>	
				<bit name="CCP1IE" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="ADCIE" offset="6"></bit>	
				<bit name="--" offset="7"></bit>			
			</reg>

			<reg name="PIE2" addr="8D" read-addr="18D" write-addr="18D" value-addr="8D" addr-visiable="true" bank="1">
				<bit name="--" offset="0"></bit>
				<bit name="T3IE" offset="1"></bit>	
				<bit name="T4IE" offset="2"></bit>
				<bit name="T5IE" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="C1IE" offset="5"></bit>
				<bit name="C2IE" offset="6"></bit>	
				<bit name="--" offset="7"></bit>			
			</reg>
			
			<reg name="PCON" addr="8E" read-addr="18E" write-addr="18E" value-addr="8E" addr-visiable="true" bank="1">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="LVDTE" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="WDTE" offset="7"></bit>
			</reg>				
			
			<reg name="WUACON" addr="8F" read-addr="18F" write-addr="18F" value-addr="8f" addr-visiable="true" bank="1"></reg>	
			<reg name="PAIC0" addr="90" read-addr="190" write-addr="190" value-addr="90" addr-visiable="true" bank="1"></reg>	
			<reg name="PCIC0" addr="91" read-addr="191" write-addr="191" value-addr="91" addr-visiable="true" bank="1"></reg>	
			<reg name="PAHCON" addr="92" read-addr="192" write-addr="192" value-addr="92" addr-visiable="true" bank="1"></reg>				
			<reg name="ADCCON" addr="93" read-addr="193" write-addr="193" value-addr="93" addr-visiable="true" bank="1"></reg>		
			
			<reg name="OSCM" addr="94" read-addr="194" write-addr="194" value-addr="94" addr-visiable="true" bank="1">
				<bit name="CLKMD" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="XTSEL" offset="2"></bit>	
				<bit name="SLCON" offset="3"></bit>	
				<bit name="TRCEN" offset="4"></bit>	
				<bit name="GREENEN" offset="5"></bit>	
				<bit name="WAKEMODE" offset="6"></bit>
				<bit name="MONIF" offset="7"></bit>			
			</reg>							
			
			<reg name="PAODCON" addr="95" read-addr="195" write-addr="195" value-addr="95" addr-visiable="true" bank="1"></reg>	
			<reg name="PWMP1CON" addr="96" read-addr="196" write-addr="196" value-addr="96" addr-visiable="true" bank="1">
				<bit name="P1AOE" offset="0"></bit>
				<bit name="P1BOE" offset="1"></bit>
				<bit name="P1COE" offset="2"></bit>	
				<bit name="P1DOE" offset="3"></bit>	
				<bit name="P1EOE" offset="4"></bit>	
				<bit name="P1FOE" offset="5"></bit>	
				<bit name="P1OS" offset="6"></bit>
				<bit name="AUX1EN" offset="7"></bit>				
			</reg>	
			<reg name="ECCPAS" addr="97" read-addr="197" write-addr="197" value-addr="97" addr-visiable="true" bank="1">
				<bit name="PSSBD0" offset="0"></bit>
				<bit name="PSSBD1" offset="1"></bit>
				<bit name="PSSAC0" offset="2"></bit>	
				<bit name="PSSAC1" offset="3"></bit>	
				<bit name="ECCPAC0" offset="4"></bit>	
				<bit name="ECCPAC1" offset="5"></bit>	
				<bit name="PCCPAC2" offset="6"></bit>
				<bit name="ECCPASE" offset="7"></bit>				
			</reg>	
			<reg name="CCPCON" addr="98" read-addr="198" write-addr="198" value-addr="98" addr-visiable="true" bank="1">
				<bit name="CCP1M0" offset="0"></bit>
				<bit name="CCP1M1" offset="1"></bit>
				<bit name="CCP1M2" offset="2"></bit>	
				<bit name="CCP1M3" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="P1M0" offset="6"></bit>
				<bit name="P1M1" offset="7"></bit>				
			</reg>	
			
			<reg name="CCPRH" addr="99" read-addr="199" write-addr="199" value-addr="99" addr-visiable="true" bank="1"></reg>						
			<reg name="CCPRL" addr="9A" read-addr="19A" write-addr="19A" value-addr="9A" addr-visiable="true" bank="1"></reg>
			
			<reg name="T1CON" addr="9B" read-addr="19B" write-addr="19B" value-addr="9B" addr-visiable="true" bank="1">
				<bit name="T1REN" offset="0"></bit>
				<bit name="T1CKS0" offset="1"></bit>
				<bit name="T1SYNC" offset="2"></bit>	
				<bit name="T1CKS1" offset="3"></bit>	
				<bit name="T1CK0" offset="4"></bit>	
				<bit name="T1CK1" offset="5"></bit>	
				<bit name="T1GE" offset="6"></bit>
				<bit name="T1GINV" offset="7"></bit>				
			</reg>	
			
			<reg name="T1TH" addr="9C" read-addr="19C" write-addr="19C" value-addr="9C" addr-visiable="true" bank="1"></reg>
			<reg name="T1TL" addr="9D" read-addr="19D" write-addr="19D" value-addr="9D" addr-visiable="true" bank="1"></reg>			
		
			<reg name="T2DTL" addr="9E" read-addr="19E" write-addr="19E" value-addr="9E" addr-visiable="true" bank="1"></reg>			
			<reg name="T2DTH" addr="9F" read-addr="19F" write-addr="19F" value-addr="9F" addr-visiable="true" bank="1"></reg>				
			
			<reg name="LVDCON" addr="10C" read-addr="20C" write-addr="20C" value-addr="10C" addr-visiable="true" bank="2">
				<bit name="LVDS0" offset="0"></bit>
				<bit name="LVDS1" offset="1"></bit>
				<bit name="LVDS2" offset="2"></bit>	
				<bit name="LVDS3" offset="3"></bit>	
				<bit name="LVDEN" offset="4"></bit>	
				<bit name="LVDIF" offset="5"></bit>	
				<bit name="MONEN" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>				
			
			<reg name="EEADR" addr="10D" read-addr="20D" write-addr="20D" value-addr="10D" addr-visiable="true" bank="2"></reg>	
			<reg name="EEDAT" addr="10E" read-addr="20E" write-addr="20E" value-addr="10E" addr-visiable="true" bank="2"></reg>			
			
			<reg name="EECON" addr="10F" read-addr="20F" write-addr="20F" value-addr="10F" addr-visiable="true" bank="2">
				<bit name="READEE" offset="0"></bit>
				<bit name="PROGEE" offset="1"></bit>
				<bit name="ERASEEE" offset="2"></bit>	
				<bit name="ERSALLEE" offset="3"></bit>	
				<bit name="ERS16" offset="4"></bit>	
				<bit name="TIMEE0" offset="5"></bit>	
				<bit name="TIMEE1" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>			
			
			<reg name="T3C0" addr="110" read-addr="210" write-addr="210" value-addr="110" addr-visiable="true" bank="2">
				<bit name="--" offset="0"></bit>
				<bit name="T3PWMEN" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="T3BUZEN" offset="3"></bit>	
				<bit name="T3PWNINV" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="T3REN" offset="7"></bit>				
			</reg>	
			<reg name="T3C1" addr="111" read-addr="211" write-addr="211" value-addr="111" addr-visiable="true" bank="2">
				<bit name="T3CK0" offset="0"></bit>
				<bit name="T3CK1" offset="1"></bit>
				<bit name="T3CK2" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="T3CKS0" offset="4"></bit>	
				<bit name="T3CKS1" offset="5"></bit>	
				<bit name="T3OUT0" offset="6"></bit>
				<bit name="--" offset="7"></bit>				
			</reg>	
			
			<reg name="T3TL" addr="112" read-addr="212" write-addr="212" value-addr="112" addr-visiable="true" bank="2"></reg>	
			<reg name="T3TH" addr="113" read-addr="213" write-addr="213" value-addr="113" addr-visiable="true" bank="2"></reg>	
			<reg name="T3PL" addr="114" read-addr="214" write-addr="214" value-addr="114" addr-visiable="true" bank="2"></reg>	
			<reg name="T3PH" addr="115" read-addr="215" write-addr="215" value-addr="115" addr-visiable="true" bank="2"></reg>
			
			<reg name="T3DL" addr="116" read-addr="216" write-addr="216" value-addr="116" addr-visiable="true" bank="2"></reg>									
			<reg name="T3DH" addr="117" read-addr="217" write-addr="217" value-addr="117" addr-visiable="true" bank="2"></reg>	
			
			<reg name="T2C0" addr="118" read-addr="218" write-addr="218" value-addr="118" addr-visiable="true" bank="2">
				<bit name="--" offset="0"></bit>
				<bit name="T2PWNEN" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="T2REN" offset="7"></bit>
			</reg>
			
			<reg name="T2C1" addr="119" read-addr="219" write-addr="219" value-addr="119" addr-visiable="true" bank="2">
				<bit name="T2CK0" offset="0"></bit>
				<bit name="T2CK1" offset="1"></bit>
				<bit name="T2CK2" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="T2CKS0" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="T2OUT0" offset="6"></bit>
				<bit name="PRSEN" offset="7"></bit>			
			</reg>	
			
			<reg name="T2TL" addr="11A" read-addr="21A" write-addr="21A" value-addr="11A" addr-visiable="true" bank="2"></reg>			
			<reg name="T2TH" addr="11B" read-addr="21B" write-addr="21B" value-addr="11B" addr-visiable="true" bank="2"></reg>		
			<reg name="T2PL" addr="11C" read-addr="21C" write-addr="21C" value-addr="11C" addr-visiable="true" bank="2"></reg>	
			<reg name="T2PH" addr="11D" read-addr="21D" write-addr="21D" value-addr="11D" addr-visiable="true" bank="2"></reg>
			<reg name="T2DL" addr="11E" read-addr="21E" write-addr="21E" value-addr="11E" addr-visiable="true" bank="2"></reg>			
			<reg name="T2DH" addr="11F" read-addr="21F" write-addr="21F" value-addr="11F" addr-visiable="true" bank="2"></reg>	
			
			<reg name="RCREG" addr="188" read-addr="308" write-addr="308" value-addr="188" addr-visiable="true" bank="3"></reg>
			<reg name="T4C0" addr="18D" read-addr="30D" write-addr="30D" value-addr="18D" addr-visiable="true" bank="3">
				<bit name="--" offset="0"></bit>
				<bit name="T4PWMEN" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="T4BUZEN" offset="3"></bit>	
				<bit name="T2PWMEN" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="T4REN" offset="7"></bit>				
			</reg>
			<reg name="T4C1" addr="18E" read-addr="30E" write-addr="30E" value-addr="18E" addr-visiable="true" bank="3">
				<bit name="T4CK0" offset="0"></bit>
				<bit name="T4CK1" offset="1"></bit>
				<bit name="T4CK2" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="T4CKS0" offset="4"></bit>	
				<bit name="T4CKS1" offset="5"></bit>	
				<bit name="T4OUT0" offset="6"></bit>
				<bit name="--" offset="7"></bit>				
			</reg>
			<reg name="T4TL" addr="18F" read-addr="30F" write-addr="30F" value-addr="18F" addr-visiable="true" bank="3"></reg>
			<reg name="T4TH" addr="190" read-addr="310" write-addr="310" value-addr="190" addr-visiable="true" bank="3"></reg>
			<reg name="T4PL" addr="191" read-addr="311" write-addr="311" value-addr="191" addr-visiable="true" bank="3"></reg>			
			<reg name="T4PH" addr="192" read-addr="312" write-addr="312" value-addr="192" addr-visiable="true" bank="3"></reg>				
			<reg name="T4DL" addr="193" read-addr="313" write-addr="313" value-addr="193" addr-visiable="true" bank="3"></reg>
			<reg name="T4DH" addr="194" read-addr="314" write-addr="314" value-addr="194" addr-visiable="true" bank="3"></reg>
			
			<reg name="T5C0" addr="195" read-addr="315" write-addr="315" value-addr="195" addr-visiable="true" bank="3">
				<bit name="--" offset="0"></bit>
				<bit name="T5PWMEN" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="T5BUZEN" offset="3"></bit>	
				<bit name="T5PWMEN" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="T5REN" offset="7"></bit>					
			</reg>
			
			<reg name="T5C1" addr="196" read-addr="316" write-addr="316" value-addr="196" addr-visiable="true" bank="3">
				<bit name="T5CK0" offset="0"></bit>
				<bit name="T5CK1" offset="1"></bit>
				<bit name="T5CK2" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="T5CKS0" offset="4"></bit>	
				<bit name="T5CKS1" offset="5"></bit>	
				<bit name="T5OUT0" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>
			<reg name="T5TL" addr="197" read-addr="317" write-addr="317" value-addr="197" addr-visiable="true" bank="3"></reg>
			<reg name="T5TH" addr="198" read-addr="318" write-addr="318" value-addr="198" addr-visiable="true" bank="3"></reg>			
			<reg name="T5PL" addr="199" read-addr="319" write-addr="319" value-addr="199" addr-visiable="true" bank="3"></reg>
			<reg name="T5PH" addr="19A" read-addr="31A" write-addr="31A" value-addr="19A" addr-visiable="true" bank="3"></reg>			
			<reg name="T5DL" addr="19B" read-addr="31B" write-addr="31B" value-addr="19B" addr-visiable="true" bank="3"></reg>							
			<reg name="T5DH" addr="19C" read-addr="31C" write-addr="31C" value-addr="19C" addr-visiable="true" bank="3"></reg>
			
			<reg name="CMCON0" addr="19D" read-addr="31D" write-addr="31D" value-addr="19D" addr-visiable="true" bank="3">
				<bit name="CMCH0" offset="0"></bit>
				<bit name="CMCH1" offset="1"></bit>
				<bit name="CMCH2" offset="2"></bit>	
				<bit name="CIS" offset="3"></bit>	
				<bit name="C1INV" offset="4"></bit>	
				<bit name="C2INV" offset="5"></bit>	
				<bit name="C1OUT" offset="6"></bit>
				<bit name="C2OUT" offset="7"></bit>			
			</reg>
			
			<reg name="CMCON1" addr="19E" read-addr="31E" write-addr="31E" value-addr="19E" addr-visiable="true" bank="3">
				<bit name="C2SYNC" offset="0"></bit>
				<bit name="TIGSS" offset="1"></bit>
				<bit name="C1FIEN" offset="2"></bit>	
				<bit name="C2FIEN" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>				
			</reg>
			
			
			<reg name="VRCON" addr="19F" read-addr="31F" write-addr="31F" value-addr="19F" addr-visiable="true" bank="3">
				<bit name="VR0" offset="0"></bit>
				<bit name="VR1" offset="1"></bit>
				<bit name="VR2" offset="2"></bit>	
				<bit name="VR3" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="VRR" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="VREN" offset="7"></bit>
			</reg>			
			<reg name="FLCON1" addr="1A0" read-addr="320" write-addr="320" value-addr="120" addr-visiable="true" bank="3">
				<bit name="READL" offset="0"></bit>
				<bit name="PROGL" offset="1"></bit>
				<bit name="ERASEL" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="TIMEL0" offset="5"></bit>	
				<bit name="TIMEL1" offset="6"></bit>
				<bit name="CEFL" offset="7"></bit>
			</reg>
			<reg name="FLCON2" addr="1A1" read-addr="321" write-addr="321" value-addr="121" addr-visiable="true" bank="3"></reg>
			<reg name="FLADRH" addr="1A2" read-addr="322" write-addr="322" value-addr="122" addr-visiable="true" bank="3"></reg>
			<reg name="FLADRL" addr="1A3" read-addr="323" write-addr="323" value-addr="123" addr-visiable="true" bank="3"></reg>
			<reg name="FLDATH" addr="1A4" read-addr="324" write-addr="324" value-addr="124" addr-visiable="true" bank="3"></reg>
			<reg name="FLDATL" addr="1A5" read-addr="325" write-addr="325" value-addr="125" addr-visiable="true" bank="3"></reg>
			
			<reg name="FLEF" addr="1A6" read-addr="326" write-addr="326" value-addr="127" addr-visiable="true" bank="3">
				<bit name="FOV" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>			
		</sfr>	
	</sfrs>
	<eeprom>
		<size>256</size>
		<addr>0</addr>	
		<update-addr>2B0</update-addr>
	</eeprom>
	<ccs-config>
		<!--默认擦除EE-->
		<config-item addr="548" bit="no">1</config-item>
	</ccs-config>		
	<insts>
		<inst name="call" value="1000" mask-value="3800"/>
		<inst name="return" value="007c" mask-value="3fff"/>
		<inst name="return" value="007e" mask-value="3fff"/>
		<inst name="return" value="3c00" mask-value="3c00"/>
	</insts>
	<compilers>
		<compiler>	
			<compiler-item type="c" name="cc1" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 4 -ram-bank 20-7f,a0-ef -common 70-7f -rst-addr 00h -int-addr 04h -tran-exe ptran2.exe  -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
				<action-before-compile>
				</action-before-compile> 
				<action-after-compile >
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="asm" name="ac0" command-path="$(DevEnvDir)\ac0.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -ram-start $(RamStartAddr) -ram-size $(RamSize) -reset-addr $(ResetAddr) -inst-set INST_SET_FM153 -otp-body-size $(OtpBodySize) -debug false -symbol-file true  -listfile true -workdir "$(ProjectDir)" -include-path "$GetFolders(';')" -file "$(EntryFile)" -output "$(OutDir)" -project-name "$(ProjectName)" -config "$(ConfigWord)"</option>
				<action-before-compile>
				</action-before-compile>
				<action-after-compile>
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="c" name="cc1" out-type="lib" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 4 -ram-bank 20-7f,a0-ef -common 70-7f -rst-addr 00h -int-addr 04h -tran-exe ptran2.exe  -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
			</compiler-item>			
		</compiler>
	</compilers>
	<debugers>
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>picc</debuger-c>
			<device type="4" version="0">
				<simulator type="4" version="0" code-first="false" config-item="false" config-item-id="-1">
					<pc-addr pcl="1ff1" pch="1ff2" />
					<config-word-addr>7F8</config-word-addr>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>			
		</debuger>		
	</debugers>
	<editor-language>
		<c-lang name="c1-lang"/>
		<asm-lang name="asm1-lang"/>
	</editor-language>	
</chip>