<?xml version="1.0" encoding="UTF-8"?>
<chip>
	<configure-file-ver>1.0</configure-file-ver>
	<chip-name>HS16F3612</chip-name>
	<chip-classes>Flash</chip-classes>
	<chip-id>A6</chip-id>
	<chip-id-debug>fe22</chip-id-debug>
	<chip-ver>0</chip-ver>
	<ccs-file-ver>4</ccs-file-ver>
	<ram-start-addr>0</ram-start-addr>
	<ram-size>256</ram-size>
	<otp-body-size>4096</otp-body-size>
	<user-rom-size>4064</user-rom-size>
	<reset-addr>0</reset-addr>
	<stack-level>8</stack-level>
	<config-word-count>5</config-word-count>
	<max-breakpoint>4</max-breakpoint>
	<asm-inc>$(DevEnvDir)\asm_inc\$(ChipName).inc</asm-inc>
	<clang-inc>$(DevEnvDir)\include\$(ChipName).h</clang-inc>		
	<description></description>
	<rams>
		<ram start-addr="0" length="512">
			<ram-segment start-addr="00" size="32" write-addr="00" read-addr="00" value-addr="00" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="20" size="80" write-addr="20" read-addr="20" value-addr="20" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="70" size="16" write-addr="70" read-addr="70" value-addr="70" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="80" size="32" write-addr="100" read-addr="100" value-addr="80" visiable="false" bank="1"></ram-segment>
			<ram-segment start-addr="a0" size="80" write-addr="120" read-addr="120" value-addr="a0" visiable="true" bank="1"></ram-segment>	
			<ram-segment start-addr="f0" size="16" write-addr="170" read-addr="170" value-addr="f0" visiable="true" bank="1"></ram-segment>	
			<ram-segment start-addr="100" size="32" write-addr="200" read-addr="200" value-addr="100" visiable="false" bank="2"></ram-segment>	
			<ram-segment start-addr="120" size="80" write-addr="220" read-addr="220" value-addr="120" visiable="true" bank="2"></ram-segment>
			<ram-segment start-addr="170" size="16" write-addr="270" read-addr="270" value-addr="170" visiable="true" bank="2"></ram-segment>		
			<ram-segment start-addr="180" size="32" write-addr="300" read-addr="300" value-addr="180" visiable="false" bank="3"></ram-segment>		
			<ram-segment start-addr="1a0" size="80" write-addr="320" read-addr="320" value-addr="1a0" visiable="true" bank="3"></ram-segment>		
			<ram-segment start-addr="1f0" size="16" write-addr="370" read-addr="370" value-addr="1f0" visiable="true" bank="3"></ram-segment>		
			<ram-segment start-addr="200" size="32" write-addr="400" read-addr="400" value-addr="200" visiable="true" bank="4"></ram-segment>	
			<ram-segment start-addr="280" size="32" write-addr="800" read-addr="800" value-addr="280" visiable="true" bank="5"></ram-segment>		
			<ram-segment start-addr="1ff0" size="3" write-addr="1ff0" read-addr="1ff0" value-addr="1ff0" visiable="false" bank="-1"></ram-segment>				
		</ram>	
	</rams>
	<configs>
		<config-word index="0" or-value="0000" and-value="ffff" mapto="0"></config-word>
		<config-word index="1" or-value="0000" and-value="ffff" mapto="1"></config-word>	
		<config-word index="2" or-value="0000" and-value="ffff" mapto="3"></config-word>	
		<config-word index="3" or-value="0000" and-value="ffff" mapto="2"></config-word>			
		<!--
		<config-item name="ENVDDL" width="1" offset="13" default-value="0" enable="false" config-index="0">
			<config-item-value name="不自动锁存数据" value="0"></config-item-value>
			<config-item-value name="自动锁存数据" value="1"></config-item-value>
			<description>自动锁存数据</description>
		</config-item>
		-->
		<config-item name="复位脚功能" width="1" offset="12" default-value="0" enable="true" config-index="0">
			<config-item-value name="As RESET Pin" value="1"></config-item-value>
			<config-item-value name="As IO" value="0"></config-item-value>
			<description>PB3功能</description>
		</config-item>
		<config-item name="OSC脚功能" width="1" offset="11" default-value="0" enable="true" config-index="0">
			<config-item-value name="As IO" value="0"></config-item-value>
			<config-item-value name="As OSCO" value="1"></config-item-value>
			<description>PB4功能</description>
		</config-item>		
		<config-item name="复位时间" width="3" offset="8" default-value="0" enable="true" config-index="0">
			<config-item-value name="PWRT=WDT=18ms" value="0"></config-item-value>
			<config-item-value name="PWRT=WDT=4.5ms" value="1"></config-item-value>
			<config-item-value name="PWRT=WDT=288ms" value="2"></config-item-value>
			<config-item-value name="PWRT=WDT=72ms" value="3"></config-item-value>
			<config-item-value name="PWRT=4.5ms,WDT=18ms" value="4"></config-item-value>
			<config-item-value name="PWRT=4.5ms,WDT=4.5ms" value="5"></config-item-value>
			<config-item-value name="PWRT=4.5ms,WDT=288ms" value="6"></config-item-value>
			<config-item-value name="PWRT=4.5ms,WDT=72ms" value="7"></config-item-value>
			<description>PWRT</description>
		</config-item>
		<config-item name="复位电压" width="3" offset="3" default-value="1" enable="true" config-index="0">
			<config-item-value name="Disable(1.65v)" value="0"></config-item-value>
			<config-item-value name="2.0v" value="1"></config-item-value>
			<config-item-value name="2.2v" value="2"></config-item-value>
			<config-item-value name="2.4v" value="3"></config-item-value>
			<config-item-value name="2.6v" value="4"></config-item-value>
			<config-item-value name="3.6v" value="5"></config-item-value>
			<description>LVD</description>
		</config-item>	
		<config-item name="时钟选择" width="3" offset="0" default-value="0" enable="true" config-index="0">
			<config-item-value name="IRC" value="0"></config-item-value>
			<config-item-value name="LP" value="1"></config-item-value>
			<config-item-value name="HS" value="2"></config-item-value>
			<config-item-value name="XT" value="3"></config-item-value>
			<config-item-value name="IRC and RTC" value="4"></config-item-value>
			<description>
			IRC:内部高速RC
			LP:外部低速32.768Khz晶振
			HS:外部高速16Mhz晶振
			XT:外部4Mhz晶振
			IRC and RTC:内部高速RC与外部低速32.768Khz晶振共同有效
			</description>
		</config-item>						
		<config-item name="BOR滤波" width="1" offset="11" default-value="0" enable="true" config-index="1">
			<config-item-value name="Enable" value="0"></config-item-value>
			<config-item-value name="Disable" value="1"></config-item-value>
			<description>BOR滤波</description>
		</config-item>	
		<config-item name="读周期" width="3" offset="8" default-value="0" enable="true" config-index="1">
			<config-item-value name="全周期,工作电压宽但电流较大" value="0"></config-item-value>
			<config-item-value name="半周期,工作电压稍窄电流稍小" value="4"></config-item-value>
			<config-item-value name="1/4周期,工作电流小，综合主频小于2MHZ" value="6"></config-item-value>
			<config-item-value name="低功耗模式,电流很小但综合主频小于1MHZ" value="5"></config-item-value>
			<description>读周期选择</description>
		</config-item>
		<config-item name="读端口" width="1" offset="5" default-value="0" enable="true" config-index="1">
			<config-item-value name="Form register" value="0"></config-item-value>
			<config-item-value name="Form Pins" value="1"></config-item-value>
			<description>读端口</description>
		</config-item>	
		<config-item name="时钟分频" width="3" offset="2" default-value="1" enable="true" config-index="1">
			<config-item-value name="4分频" value="0"></config-item-value>
			<config-item-value name="2分频" value="1"></config-item-value>
			<config-item-value name="8分频" value="2"></config-item-value>
			<config-item-value name="16分频" value="3"></config-item-value>
			<config-item-value name="32分频" value="4"></config-item-value>
			<config-item-value name="64分频" value="5"></config-item-value>
			<config-item-value name="128分频" value="6"></config-item-value>
			<config-item-value name="256分频" value="7"></config-item-value>
			<description>系统分频</description>
		</config-item>				
		<config-item name="加密" width="1" offset="1" default-value="1" enable="true" config-index="1">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>加密</description>
		</config-item>	
		<config-item name="看门狗" width="1" offset="0" default-value="1" enable="true" config-index="1">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>看门狗</description>
		</config-item>	
		<config-item name="触摸" width="1" offset="13" default-value="1" enable="true" config-index="3">
			<config-item-value name="Disable" value="1"></config-item-value>
			<config-item-value name="Enable" value="0"></config-item-value>
			<description></description>
		</config-item>			
		<config-item name="系统频率" width="1" offset="13" default-value="0" enable="true" config-index="2">
			<config-item-value name="8M" value="0"></config-item-value>
			<config-item-value name="16M" value="1"></config-item-value>
			<description>系统频率</description>
		</config-item>				
	</configs>
	
	<sfrs>
		<sfr>
			<reg name="ACC" addr="1ff0" read-addr="1ff0" write-addr="1ff0" value-addr="1ff0" addr-visiable="false" bank="-1"></reg>
			<reg name="INDF" addr="00" read-addr="00" write-addr="00" value-addr="00" addr-visiable="true" bank="0"></reg>
			<reg name="TMR0" addr="01"  read-addr="01" write-addr="01" value-addr="01" addr-visiable="true" bank="0"></reg>
			<reg name="PCL" addr="02" read-addr="02" write-addr="02" value-addr="02" addr-visiable="true" bank="0"></reg>
			
			<reg name="STATUS" addr="03" read-addr="03" write-addr="03" value-addr="03" addr-visiable="true" bank="0">
				<bit name="C" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="Z" offset="2"></bit>
				<bit name="PD" offset="3"></bit>
				<bit name="TO" offset="4"></bit>
				<bit name="RP0" offset="5"></bit>
				<bit name="RP1" offset="6"></bit>
				<bit name="IRP" offset="7"></bit>
			</reg>
			
			<reg name="FSR" addr="04"  read-addr="04" write-addr="04" value-addr="04" addr-visiable="true" bank="0"></reg>	
			<reg name="PORTA" addr="05"  read-addr="05" write-addr="05" value-addr="05" addr-visiable="true" bank="0"></reg>
			<reg name="PORTB" addr="06"  read-addr="06" write-addr="06" value-addr="06" addr-visiable="true" bank="0"></reg>
			<reg name="PORTC" addr="07"  read-addr="07" write-addr="07" value-addr="07" addr-visiable="true" bank="0"></reg>
			<reg name="BSREG" addr="09"  read-addr="09" write-addr="09" value-addr="09" addr-visiable="true" bank="0"></reg>
			<reg name="PCLATH" addr="0A"  read-addr="0a" write-addr="0a" value-addr="0a" addr-visiable="true" bank="0"></reg>
			
			<reg name="INTEN" addr="0B"  read-addr="0b" write-addr="0b" value-addr="0b" addr-visiable="true" bank="0">
				<bit name="T0IE" offset="0"></bit>
				<bit name="PBIE" offset="1"></bit>
				<bit name="INTIE" offset="2"></bit>	
				<bit name="TC1IE" offset="3"></bit>
				<bit name="T2IE" offset="4"></bit>	
				<bit name="INT1IE" offset="5"></bit>
				<bit name="T3IE" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>
			
			<reg name="INTFLAG" addr="0C"  read-addr="0c" write-addr="0c" value-addr="0c" addr-visiable="true" bank="0">
				<bit name="T0IF" offset="0"></bit>
				<bit name="PBIF" offset="1"></bit>
				<bit name="INTIF" offset="2"></bit>	
				<bit name="TC1IF" offset="3"></bit>	
				<bit name="T2IF" offset="4"></bit>	
				<bit name="INT1IF" offset="5"></bit>	
				<bit name="T3IF" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>
			
			<reg name="INTFLAG1" addr="0D"  read-addr="0d" write-addr="0d" value-addr="0d" addr-visiable="true" bank="0">
				<bit name="TKIF" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="ADCIF" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>
			
			<reg name="PBDCON" addr="0E"  read-addr="0e" write-addr="0e" value-addr="0e" addr-visiable="true" bank="0"></reg>
			<reg name="PBODCON" addr="0F"  read-addr="0f" write-addr="0f" value-addr="0f" addr-visiable="true" bank="0"></reg>
			<reg name="PBHCON" addr="10"  read-addr="10" write-addr="10" value-addr="10" addr-visiable="true" bank="0"></reg>
			
			<reg name="TC1M" addr="11"  read-addr="11" write-addr="11" value-addr="11" addr-visiable="true" bank="0">
				<bit name="TCCKS" offset="0"></bit>
				<bit name="RLOAD" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="TC1S0" offset="3"></bit>	
				<bit name="TC1S1" offset="4"></bit>	
				<bit name="TC1S2" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="TC1TR" offset="7"></bit>			
			</reg>			
			
			<reg name="TC1C" addr="12"  read-addr="12" write-addr="12" value-addr="12" addr-visiable="true" bank="0"></reg>
			<reg name="PBIC0" addr="13"  read-addr="13" write-addr="13" value-addr="13" addr-visiable="true" bank="0"></reg>
			<reg name="TC1R" addr="14"  read-addr="14" write-addr="14" value-addr="14" addr-visiable="true" bank="0"></reg>
			<reg name="ADBREG" addr="16"  read-addr="16" write-addr="16" value-addr="16" addr-visiable="true" bank="0"></reg>
			
			<reg name="ADF1" addr="17"  read-addr="17" write-addr="17" value-addr="17" addr-visiable="true" bank="0"></reg>
			<reg name="ADF0" addr="18"  read-addr="18" write-addr="18" value-addr="18" addr-visiable="true" bank="0"></reg>
			<reg name="ADPC1" addr="19"  read-addr="19" write-addr="19" value-addr="19" addr-visiable="true" bank="0"></reg>
			<reg name="ADPC" addr="1A"  read-addr="1A" write-addr="1A" value-addr="1A" addr-visiable="true" bank="0"></reg>
						
			<reg name="ADM" addr="1B"  read-addr="1B" write-addr="1B" value-addr="1B" addr-visiable="true" bank="0">
				<bit name="CHS0" offset="0"></bit>
				<bit name="CHS1" offset="1"></bit>
				<bit name="CHS2" offset="2"></bit>	
				<bit name="CHS3" offset="3"></bit>	
				<bit name="GCHS" offset="4"></bit>	
				<bit name="EOC" offset="5"></bit>	
				<bit name="ADS" offset="6"></bit>
				<bit name="ADENB" offset="7"></bit>			
			</reg>			
			
			<reg name="ADB" addr="1C"  read-addr="1C" write-addr="1C" value-addr="1C" addr-visiable="true" bank="0"></reg>
			
			<reg name="ADR" addr="1D"  read-addr="1D" write-addr="1D" value-addr="1D" addr-visiable="true" bank="0">
				<bit name="ADB0" offset="0"></bit>
				<bit name="ADB1" offset="1"></bit>
				<bit name="ADB2" offset="2"></bit>	
				<bit name="ADB3" offset="3"></bit>	
				<bit name="ADCKS" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="ADCKS1" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>		

			<reg name="ADT" addr="1E"  read-addr="1E" write-addr="1E" value-addr="1E" addr-visiable="true" bank="0">
				<bit name="ADT0" offset="0"></bit>
				<bit name="ADT1" offset="1"></bit>
				<bit name="ADT2" offset="2"></bit>	
				<bit name="ADT3" offset="3"></bit>	
				<bit name="ADTS0" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>		

			<reg name="VREF" addr="1F"  read-addr="1F" write-addr="1F" value-addr="1F" addr-visiable="true" bank="0">
				<bit name="VHS0" offset="0"></bit>
				<bit name="VHS1" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="EVHENB" offset="7"></bit>			
			</reg>	

			<reg name="OPTIONR" addr="81"  read-addr="180" write-addr="180" value-addr="81" addr-visiable="true" bank="1">
				<bit name="PA0" offset="0"></bit>
				<bit name="PA1" offset="1"></bit>
				<bit name="PA2" offset="2"></bit>	
				<bit name="PAA" offset="3"></bit>	
				<bit name="T0SE" offset="4"></bit>	
				<bit name="T0CS" offset="5"></bit>	
				<bit name="INTEDGE" offset="6"></bit>
				<bit name="INTIEDGE" offset="7"></bit>			
			</reg>	

			<reg name="TRISA" addr="85"  read-addr="185" write-addr="185" value-addr="85" addr-visiable="true" bank="1"></reg>
			<reg name="TRISB" addr="86" read-addr="186" write-addr="186" value-addr="86" addr-visiable="true" bank="1"></reg>
			<reg name="TRISC" addr="87" read-addr="187" write-addr="187" value-addr="87" addr-visiable="true" bank="1"></reg>

			<reg name="INTEN1" addr="8D" read-addr="18D" write-addr="18D" value-addr="8D" addr-visiable="true" bank="1">
				<bit name="TKIE" offset="0"></bit>
				<bit name="--" offset="1"></bit>	
				<bit name="ADCIE" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>	
				<bit name="--" offset="7"></bit>			
			</reg>
			
			<reg name="PCON" addr="8E" read-addr="18E" write-addr="18E" value-addr="8E" addr-visiable="true" bank="1">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="SMTS" offset="4"></bit>
				<bit name="LVDTE" offset="5"></bit>
				<bit name="EIS" offset="6"></bit>
				<bit name="WDTE" offset="7"></bit>
			</reg>			
			
			<reg name="WUBCON" addr="8F" read-addr="18F" write-addr="18F" value-addr="8f" addr-visiable="true" bank="1"></reg>	
			<reg name="PAIC0" addr="90" read-addr="190" write-addr="190" value-addr="90" addr-visiable="true" bank="1"></reg>	
			<reg name="PCIC0" addr="91" read-addr="191" write-addr="191" value-addr="91" addr-visiable="true" bank="1"></reg>	
			<reg name="PAHCON" addr="92" read-addr="192" write-addr="192" value-addr="92" addr-visiable="true" bank="1"></reg>				
			<reg name="ADCCON" addr="93" read-addr="193" write-addr="193" value-addr="93" addr-visiable="true" bank="1"></reg>		
			
			<reg name="OSCM" addr="94" read-addr="194" write-addr="194" value-addr="94" addr-visiable="true" bank="1">
				<bit name="CLKMD" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="XTSEL" offset="2"></bit>	
				<bit name="SLCON" offset="3"></bit>	
				<bit name="SLT0C" offset="4"></bit>	
				<bit name="GREENEN" offset="5"></bit>	
				<bit name="WAKEMODE" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>							
			
			<reg name="PAODCON" addr="95" read-addr="195" write-addr="195" value-addr="95" addr-visiable="true" bank="1"></reg>	
			<reg name="WUACON" addr="96" read-addr="196" write-addr="196" value-addr="96" addr-visiable="true" bank="1"></reg>	
			<reg name="PCHCON" addr="97" read-addr="197" write-addr="197" value-addr="97" addr-visiable="true" bank="1"></reg>	
			<reg name="PCDCON" addr="98" read-addr="198" write-addr="198" value-addr="98" addr-visiable="true" bank="1"></reg>	
			
			<reg name="RCSTA" addr="99" read-addr="199" write-addr="199" value-addr="99" addr-visiable="true" bank="1">
				<bit name="RX9D" offset="0"></bit>
				<bit name="OERR" offset="1"></bit>
				<bit name="FERR" offset="2"></bit>	
				<bit name="ADDEN" offset="3"></bit>	
				<bit name="CREN" offset="4"></bit>	
				<bit name="SREN" offset="5"></bit>	
				<bit name="RX9" offset="6"></bit>
				<bit name="SPEN" offset="7"></bit>			
			</reg>				
			
			<reg name="TXREG" addr="9A" read-addr="19A" write-addr="19A" value-addr="9A" addr-visiable="true" bank="1"></reg>	
			<reg name="RXREG" addr="9B" read-addr="19B" write-addr="19B" value-addr="9B" addr-visiable="true" bank="1"></reg>	
			
			<reg name="TXSTA" addr="9C" read-addr="19C" write-addr="19C" value-addr="9C" addr-visiable="true" bank="1">
				<bit name="TX9D" offset="0"></bit>
				<bit name="TRMT" offset="1"></bit>
				<bit name="BRGH" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="SYNC" offset="4"></bit>	
				<bit name="TXEN" offset="5"></bit>	
				<bit name="TX9" offset="6"></bit>
				<bit name="CSRC" offset="7"></bit>			
			</reg>				
			
			<reg name="SPBRG" addr="9D" read-addr="19D" write-addr="19D" value-addr="9D" addr-visiable="true" bank="1"></reg>
			<reg name="SPBRG1" addr="9E" read-addr="19E" write-addr="19E" value-addr="9E" addr-visiable="true" bank="1"></reg>
			
			<reg name="BAUDCTL" addr="9F" read-addr="19F" write-addr="19F" value-addr="9F" addr-visiable="true" bank="1">
				<bit name="IFTX" offset="0"></bit>
				<bit name="IFRX" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="BRG16" offset="3"></bit>	
				<bit name="TXIE" offset="4"></bit>	
				<bit name="RXIE" offset="5"></bit>	
				<bit name="CSKP" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>				
			
			<reg name="EEADRL" addr="10D" read-addr="20D" write-addr="20D" value-addr="10D" addr-visiable="true" bank="2"></reg>	
			<reg name="EEDATL" addr="10E" read-addr="20E" write-addr="20E" value-addr="10E" addr-visiable="true" bank="2"></reg>			
			
			<reg name="EECON" addr="10F" read-addr="20F" write-addr="20F" value-addr="10F" addr-visiable="true" bank="2">
				<bit name="READEE" offset="0"></bit>
				<bit name="PROGEE" offset="1"></bit>
				<bit name="ERASEEE" offset="2"></bit>	
				<bit name="ERSALLEE" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="TIMEE0" offset="5"></bit>	
				<bit name="TIMEE1" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>			
			
			<reg name="T2PWM0C1" addr="110" read-addr="210" write-addr="210" value-addr="110" addr-visiable="true" bank="2"></reg>				
			<reg name="T2PWM0EN1" addr="113" read-addr="213" write-addr="213" value-addr="113" addr-visiable="true" bank="2"></reg>	
			
			<reg name="TKC0" addr="116" read-addr="216" write-addr="216" value-addr="116" addr-visiable="true" bank="2">
				<bit name="TKPS0" offset="0"></bit>
				<bit name="TKPS1" offset="1"></bit>
				<bit name="TKPS2" offset="2"></bit>	
				<bit name="TKPS3" offset="3"></bit>	
				<bit name="CVS" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="TKST" offset="6"></bit>
				<bit name="TKEN" offset="7"></bit>			
			</reg>				
						
			<reg name="TK16PH" addr="117" read-addr="217" write-addr="217" value-addr="117" addr-visiable="true" bank="2"></reg>	
			<reg name="TK16PL" addr="118" read-addr="218" write-addr="218" value-addr="118" addr-visiable="true" bank="2"></reg>
			
			<reg name="TKC1" addr="119" read-addr="219" write-addr="219" value-addr="119" addr-visiable="true" bank="2">
				<bit name="DCTS0" offset="0"></bit>
				<bit name="DCTS1" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="CCFLT0" offset="4"></bit>	
				<bit name="CCFLT1" offset="5"></bit>	
				<bit name="CCFLT2" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	
			
			<reg name="TKC2" addr="11A" read-addr="21A" write-addr="21A" value-addr="11A" addr-visiable="true" bank="2">
				<bit name="CTS0" offset="0"></bit>
				<bit name="CTS1" offset="1"></bit>
				<bit name="CTS2" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="TKWKEN" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	
			
			<reg name="TKC3" addr="11B" read-addr="21B" write-addr="21B" value-addr="11B" addr-visiable="true" bank="2">
				<bit name="CVREFS0" offset="0"></bit>
				<bit name="CVREFS1" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="CPVS0" offset="3"></bit>	
				<bit name="CPVS1" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	
			
			<reg name="TKSTA" addr="11C" read-addr="21C" write-addr="21C" value-addr="11C" addr-visiable="true" bank="2">
				<bit name="--" offset="0"></bit>
				<bit name="SACMPO" offset="1"></bit>
				<bit name="ACMPO" offset="2"></bit>	
				<bit name="DCMPO" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="TMOUT" offset="7"></bit>			
			</reg>	

			<reg name="TKPDH" addr="11D" read-addr="21D" write-addr="21D" value-addr="11D" addr-visiable="true" bank="2"></reg>
			<reg name="TKPDL" addr="11E" read-addr="21E" write-addr="21E" value-addr="11E" addr-visiable="true" bank="2"></reg>			
			<reg name="PFACES" addr="11F" read-addr="21F" write-addr="21F" value-addr="11F" addr-visiable="true" bank="2"></reg>	
			
			<reg name="IRCREG" addr="188" read-addr="308" write-addr="308" value-addr="188" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM4DL" addr="18D" read-addr="30D" write-addr="30D" value-addr="18D" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM4DH" addr="18E" read-addr="30E" write-addr="30E" value-addr="18E" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM5DL" addr="18F" read-addr="30F" write-addr="30F" value-addr="18F" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM5DH" addr="190" read-addr="310" write-addr="310" value-addr="190" addr-visiable="true" bank="3"></reg>
			
			<reg name="T2PWM0EN" addr="191" read-addr="311" write-addr="311" value-addr="191" addr-visiable="true" bank="3">
				<bit name="T2PWMEN" offset="0"></bit>
				<bit name="PWM1M" offset="1"></bit>
				<bit name="PWM2M" offset="2"></bit>	
				<bit name="PWM3M" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="T2SELS" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="T2REN" offset="7"></bit>			
			</reg>	
			
			<reg name="T2PWM0C" addr="192" read-addr="312" write-addr="312" value-addr="192" addr-visiable="true" bank="3">
				<bit name="T2CK0" offset="0"></bit>
				<bit name="T2CK1" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="T2CK2" offset="6"></bit>
				<bit name="T2CK3" offset="7"></bit>			
			</reg>				
			
			
			<reg name="TP2PWM0TL" addr="193" read-addr="313" write-addr="313" value-addr="193" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM0TH" addr="194" read-addr="314" write-addr="314" value-addr="194" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM0PL" addr="195" read-addr="315" write-addr="315" value-addr="195" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM0PH" addr="196" read-addr="316" write-addr="316" value-addr="196" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM0DL" addr="197" read-addr="317" write-addr="317" value-addr="197" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM0DH" addr="198" read-addr="318" write-addr="318" value-addr="198" addr-visiable="true" bank="3"></reg>			
			<reg name="TP2PWM1DL" addr="199" read-addr="319" write-addr="319" value-addr="199" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM1DH" addr="19A" read-addr="31A" write-addr="31A" value-addr="19A" addr-visiable="true" bank="3"></reg>			
			
			<reg name="T2PWMPSC" addr="19B" read-addr="31B" write-addr="31B" value-addr="19B" addr-visiable="true" bank="3">
				<bit name="T2PWM0S0" offset="0"></bit>
				<bit name="T2PWM1S0" offset="1"></bit>
				<bit name="T2PWM0S1" offset="2"></bit>	
				<bit name="T2PWM1S1" offset="3"></bit>	
				<bit name="T2PWM0S2" offset="4"></bit>	
				<bit name="T2PWM1S2" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>					
			
			<reg name="TP2PWM2DL" addr="19C" read-addr="31C" write-addr="31C" value-addr="19C" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM2DH" addr="19D" read-addr="31D" write-addr="31D" value-addr="19D" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM3DL" addr="19E" read-addr="31E" write-addr="31E" value-addr="19E" addr-visiable="true" bank="3"></reg>
			<reg name="TP2PWM3DH" addr="19F" read-addr="31F" write-addr="31F" value-addr="19F" addr-visiable="true" bank="3"></reg>			
			
			<reg name="LOADREG" addr="20D" read-addr="40D" write-addr="40D" value-addr="20D" addr-visiable="true" bank="4"></reg>
			
			<reg name="FLCON1" addr="20E" read-addr="40E" write-addr="40E" value-addr="20E" addr-visiable="true" bank="4">
				<bit name="READL" offset="0"></bit>
				<bit name="PROGL" offset="1"></bit>
				<bit name="ERASEL" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="TIMEL0" offset="5"></bit>	
				<bit name="TIMEL1" offset="6"></bit>
				<bit name="CEFL" offset="7"></bit>			
			</reg>	
			
			<reg name="FLCON2" addr="20F" read-addr="40F" write-addr="40F" value-addr="20F" addr-visiable="true" bank="4"></reg>
			<reg name="FLADRH" addr="210" read-addr="410" write-addr="410" value-addr="210" addr-visiable="true" bank="4"></reg>
			<reg name="FLADRL" addr="211" read-addr="411" write-addr="411" value-addr="211" addr-visiable="true" bank="4"></reg>
			<reg name="FLDATH" addr="212" read-addr="412" write-addr="412" value-addr="212" addr-visiable="true" bank="4"></reg>
			<reg name="FLDATL" addr="213" read-addr="413" write-addr="413" value-addr="213" addr-visiable="true" bank="4"></reg>
			
			<reg name="FL_ERRF" addr="214" read-addr="414" write-addr="414" value-addr="214" addr-visiable="true" bank="3">
				<bit name="FOV" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>				
			
			<reg name="RCSTA1" addr="219" read-addr="419" write-addr="419" value-addr="219" addr-visiable="true" bank="4">
				<bit name="RX9D1" offset="0"></bit>
				<bit name="OERR1" offset="1"></bit>
				<bit name="FERR1" offset="2"></bit>	
				<bit name="ADDEN1" offset="3"></bit>	
				<bit name="CREN1" offset="4"></bit>	
				<bit name="SREN1" offset="5"></bit>	
				<bit name="RX91" offset="6"></bit>
				<bit name="SPEN1" offset="7"></bit>			
			</reg>
			
			<reg name="TXREG1" addr="21A" read-addr="41A" write-addr="41A" value-addr="21A" addr-visiable="true" bank="4"></reg>
			<reg name="RXREG1" addr="21B" read-addr="41B" write-addr="41B" value-addr="21B" addr-visiable="true" bank="4"></reg>			
					
			<reg name="TXSTA1" addr="21C" read-addr="41C" write-addr="41C" value-addr="21C" addr-visiable="true" bank="4">
				<bit name="TX9D1" offset="0"></bit>
				<bit name="TRMT1" offset="1"></bit>
				<bit name="BRGH1" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="SYNC1" offset="4"></bit>	
				<bit name="TXEN1" offset="5"></bit>	
				<bit name="TX91" offset="6"></bit>
				<bit name="CSRC1" offset="7"></bit>			
			</reg>			
			
			<reg name="SPBR1G" addr="21D" read-addr="41D" write-addr="41D" value-addr="21D" addr-visiable="true" bank="4"></reg>
			<reg name="SPBRGH1" addr="21E" read-addr="41E" write-addr="41E" value-addr="21E" addr-visiable="true" bank="4"></reg>				
			
			<reg name="BAUDCTL1" addr="21F" read-addr="41F" write-addr="41F" value-addr="21F" addr-visiable="true" bank="4">
				<bit name="IFTX1" offset="0"></bit>
				<bit name="IFRX1" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="BRG161" offset="3"></bit>	
				<bit name="TXIE1" offset="4"></bit>	
				<bit name="RXIE1" offset="5"></bit>	
				<bit name="CSKP1" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>				
			
			<reg name="T3PWM0EN" addr="291" read-addr="811" write-addr="811" value-addr="291" addr-visiable="true" bank="5">
				<bit name="T3PWMEN" offset="0"></bit>
				<bit name="T3PWM0E" offset="1"></bit>
				<bit name="T3PEM1E" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="T3SEL" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="T3REN" offset="7"></bit>			
			</reg>				
			
			<reg name="T3PWM0C" addr="292" read-addr="812" write-addr="812" value-addr="292" addr-visiable="true" bank="5">
				<bit name="T3CK0" offset="0"></bit>
				<bit name="T3CK1" offset="1"></bit>
				<bit name="T3PWM0S0" offset="2"></bit>	
				<bit name="T3PWM0S1" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="T3CK2" offset="6"></bit>
				<bit name="T3CK3" offset="7"></bit>			
			</reg>						
			
			<reg name="T3PWM0TL" addr="293" read-addr="813" write-addr="813" value-addr="293" addr-visiable="true" bank="5"></reg>
			<reg name="T3PWM0TH" addr="294" read-addr="814" write-addr="814" value-addr="294" addr-visiable="true" bank="5"></reg>
			<reg name="T3PWM0PL" addr="295" read-addr="815" write-addr="815" value-addr="295" addr-visiable="true" bank="5"></reg>
			<reg name="T3PWM0PH" addr="296" read-addr="816" write-addr="816" value-addr="296" addr-visiable="true" bank="5"></reg>
			<reg name="T3PWM0DL" addr="297" read-addr="817" write-addr="817" value-addr="297" addr-visiable="true" bank="5"></reg>
			<reg name="T3PWM0DH" addr="298" read-addr="818" write-addr="818" value-addr="298" addr-visiable="true" bank="5"></reg>
			<reg name="T3PWM1DL" addr="299" read-addr="819" write-addr="819" value-addr="299" addr-visiable="true" bank="5"></reg>
			<reg name="T3PWM1DH" addr="29A" read-addr="81A" write-addr="81A" value-addr="29A" addr-visiable="true" bank="5"></reg>			
			
			<reg name="T3PWMPSC" addr="29B" read-addr="81B" write-addr="81B" value-addr="29B" addr-visiable="true" bank="5">
				<bit name="T3PWM0S" offset="0"></bit>
				<bit name="T3PWM1S" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>				
						
			<reg name="T3PWM2DL" addr="29C" read-addr="81C" write-addr="81C" value-addr="29C" addr-visiable="true" bank="5"></reg>			
			<reg name="T3PWM2DH" addr="29D" read-addr="81D" write-addr="81D" value-addr="29D" addr-visiable="true" bank="5"></reg>	
		</sfr>	
	</sfrs>
	<eeprom>
		<size>128</size>
		<addr>0</addr>	
		<update-addr>2B0</update-addr>
	</eeprom>
	<ccs-config>
		<!--默认擦除EE-->
		<config-item addr="548" bit="no">1</config-item>
	</ccs-config>		
	<insts>
		<inst name="call" value="1000" mask-value="3800"/>
		<inst name="return" value="007c" mask-value="3fff"/>
		<inst name="return" value="007e" mask-value="3fff"/>
		<inst name="return" value="3c00" mask-value="3c00"/>
	</insts>
	<compilers>
		<compiler>	
			<compiler-item type="c" name="cc1" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 4 -ram-bank 20-7f,a0-ef,120-16f,1a0-1ef -common 70-7f -rst-addr 00h -int-addr 04h -tran-exe ptran2.exe  -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
				<action-before-compile>
				</action-before-compile> 
				<action-after-compile >
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="asm" name="ac0" command-path="$(DevEnvDir)\ac0.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -ram-start $(RamStartAddr) -ram-size $(RamSize) -reset-addr $(ResetAddr) -inst-set INST_SET_FM153 -otp-body-size $(OtpBodySize) -debug false -symbol-file true  -listfile true -workdir "$(ProjectDir)" -include-path "$GetFolders(';')" -file "$(EntryFile)" -output "$(OutDir)" -project-name "$(ProjectName)" -config "$(ConfigWord)"</option>
				<action-before-compile>
				</action-before-compile>
				<action-after-compile>
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="c" name="cc1" out-type="lib" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 4 -ram-bank 20-7f,a0-ef,120-16f,1a0-1ef -common 70-7f -rst-addr 00h -int-addr 04h -tran-exe ptran2.exe  -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
			</compiler-item>			
		</compiler>
	</compilers>
	<debugers>
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>picc</debuger-c>
			<device type="4" version="0">
				<simulator type="4" version="0" code-first="false" config-item="false" config-item-id="-1">
					<pc-addr pcl="1ff1" pch="1ff2" />
					<config-word-addr>FF8</config-word-addr>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>			
		</debuger>		
	</debugers>
	<editor-language>
		<c-lang name="c1-lang"/>
		<asm-lang name="asm1-lang"/>
	</editor-language>	
</chip>