#ifndef __SN8P2723__H
#define __SN8P2723__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FLVD24 = 0x86:4;
sbit	FLVD36 = 0x86:5;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	TC1M = 0xa0;
sbit	FPWM1OUT = 0xa0:0;
sbit	FTC1PO = 0xa0:1;
sbit	FTC1RATE0 = 0xa0:4;
sbit	FTC1RATE1 = 0xa0:5;
sbit	FTC1RATE2 = 0xa0:6;
sbit	FTC1ENB = 0xa0:7;
sfr	TC1C = 0xa1;
sfr	TC1R = 0xa2;
sfr	TC1D = 0xa3;
sfr	TC2M = 0xa4;
sbit	FPWM2OUT = 0xa4:0;
sbit	FTC2PO = 0xa4:1;
sbit	FTC2RATE0 = 0xa4:4;
sbit	FTC2RATE1 = 0xa4:5;
sbit	FTC2RATE2 = 0xa4:6;
sbit	FTC2ENB = 0xa4:7;
sfr	TC2C = 0xa5;
sfr	TC2R = 0xa6;
sfr	TC2D = 0xa7;
sfr	TC3M = 0xa8;
sbit	FPWM3OUT = 0xa8:0;
sbit	FTC3PO = 0xa8:1;
sbit	FTC3RATE0 = 0xa8:4;
sbit	FTC3RATE1 = 0xa8:5;
sbit	FTC3RATE2 = 0xa8:6;
sbit	FTC3ENB = 0xa8:7;
sfr	TC3C = 0xa9;
sfr	TC3R = 0xaa;
sfr	TC3D = 0xab;
sfr	PWCH = 0xac;
sbit	FPWCH10 = 0xac:0;
sbit	FPWCH11 = 0xac:1;
sbit	FPWCH20 = 0xac:2;
sbit	FPWCH21 = 0xac:3;
sbit	FPWCH30 = 0xac:4;
sbit	FPWCH31 = 0xac:5;
sfr	P4CON = 0xae;
sfr	P1CON = 0xaf;
sbit	FP2CON0 = 0xaf:0;
sbit	FP2CON1 = 0xaf:1;
sbit	FP1CON6 = 0xaf:6;
sbit	FP1CON7 = 0xaf:7;
sfr	VREFH = 0xB0;
sbit	FVHS0 = 0xB0:0;
sbit	FVHS1 = 0xB0:1;
sbit	FEVHENB = 0xB0:7;
sfr	ADM = 0xB1;
sbit	FCHS0 = 0xB1:0;
sbit	FCHS1 = 0xB1:1;
sbit	FCHS2 = 0xB1:2;
sbit	FCHS3 = 0xB1:3;
sbit	FGCHS = 0xB1:4;
sbit	FEOC = 0xB1:5;
sbit	FADS = 0xB1:6;
sbit	FADENB = 0xB1:7;
sfr	ADB = 0xB2;
sfr	ADR = 0xB3;
sbit	FADB0 = 0xB3:0;
sbit	FADB1 = 0xB3:1;
sbit	FADB2 = 0xB3:2;
sbit	FADB3 = 0xB3:3;
sbit	FADCKS0 = 0xB3:4;
sbit	FADLEN = 0xB3:5;
sbit	FADCKS1 = 0xB3:6;
sfr	ADT = 0xB4;
sbit	FADT0 = 0xB4:0;
sbit	FADT1 = 0xB4:1;
sbit	FADT2 = 0xB4:2;
sbit	FADT3 = 0xB4:3;
sbit	FADT4 = 0xB4:4;
sbit	FADTS0 = 0xB4:6;
sbit	FADTS1 = 0xB4:7;
sfr	PEDGE = 0xbf;
sbit	FP40G0 = 0xbf:0;
sbit	FP40G1 = 0xbf:1;
sbit	FP41G0 = 0xbf:2;
sbit	FP41G1 = 0xbf:3;
sbit	FP42G0 = 0xbf:4;
sbit	FP42G1 = 0xbf:5;
sfr	P1W = 0xc0;
sfr	P1M = 0xc1;
sbit	FP10M = 0xc1:0;
sbit	FP11M = 0xc1:1;
sbit	FP12M = 0xc1:2;
sbit	FP13M = 0xc1:3;
sbit	FP14M = 0xc1:4;
sbit	FP15M = 0xc1:5;
sbit	FP16M = 0xc1:6;
sbit	FP17M = 0xc1:7;
sfr	P2M = 0xc2;
sbit	FP20M = 0xc2:0;
sbit	FP21M = 0xc2:1;
sfr	P4M = 0xc4;
sbit	FP40M = 0xc4:0;
sbit	FP41M = 0xc4:1;
sbit	FP42M = 0xc4:2;
sbit	FP43M = 0xc4:3;
sbit	FP44M = 0xc4:4;
sbit	FP45M = 0xc4:5;
sbit	FP46M = 0xc4:6;
sbit	FP47M = 0xc4:7;
sfr	INTRQ1 = 0xc6;
sbit	FTC2IRQ = 0xc6:0;
sbit	FTC3IRQ = 0xc6:1;
sfr	INTEN1 = 0xc7;
sbit	FTC2IEN = 0xc7:0;
sbit	FTC3IEN = 0xc7:1;
sfr	INTRQ0 = 0xc8;
sbit	FP40IRQ = 0xc8:0;
sbit	FP41IRQ = 0xc8:1;
sbit	FP42IRQ = 0xc8:2;
sbit	FT0IRQ = 0xc8:4;
sbit	FTC0IRQ = 0xc8:5;
sbit	FTC1IRQ = 0xc8:6;
sbit	FADCIRQ = 0xc8:7;
sfr	INTEN0 = 0xc9;
sbit	FP40IEN = 0xc9:0;
sbit	FP41IEN = 0xc9:1;
sbit	FP42IEN = 0xc9:2;
sbit	FT0IEN = 0xc9:4;
sbit	FTC0IEN = 0xc9:5;
sbit	FTC1IEN = 0xc9:6;
sbit	FADCIEN = 0xc9:7;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P1 = 0xd1;
sbit	FP10 = 0xd1:0;
sbit	FP11 = 0xd1:1;
sbit	FP12 = 0xd1:2;
sbit	FP13 = 0xd1:3;
sbit	FP14 = 0xd1:4;
sbit	FP15 = 0xd1:5;
sbit	FP16 = 0xd1:6;
sbit	FP17 = 0xd1:7;
sfr	P2 = 0xd2;
sbit	FP20 = 0xd2:0;
sbit	FP21 = 0xd2:1;
sfr	P4 = 0xd4;
sbit	FP40 = 0xd4:0;
sbit	FP41 = 0xd4:1;
sbit	FP42 = 0xd4:2;
sbit	FP43 = 0xd4:3;
sbit	FP44 = 0xd4:4;
sbit	FP45 = 0xd4:5;
sbit	FP46 = 0xd4:6;
sbit	FP47 = 0xd4:7;
sfr	P1DR = 0xd6;
sbit	FP13DR = 0xd6:0;
sbit	FP14DR = 0xd6:1;
sbit	FP15DR = 0xd6:2;
sbit	FP16DR = 0xd6:3;
sbit	FP13SC = 0xd6:4;
sbit	FP14SC = 0xd6:5;
sbit	FP15SC = 0xd6:6;
sbit	FP16SC = 0xd6:7;
sfr	T0M = 0xd8;
sbit	FT0TB = 0xd8:0;
sbit	FT0RATE0 = 0xd8:4;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0ENB = 0xd8:7;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FPWM0OUT = 0xda:0;
sbit	FTC0PO = 0xda:1;
sbit	FTC0CKS = 0xda:3;
sbit	FTC0RATE0 = 0xda:4;
sbit	FTC0RATE1 = 0xda:5;
sbit	FTC0RATE2 = 0xda:6;
sbit	FTC0ENB = 0xda:7;
sfr	TC0C = 0xdb;
sfr	TC0R = 0xdc;
sfr	TC0D = 0xdd;
sfr	PWES = 0xde;
sbit	FPW1ES0 = 0xde:0;
sbit	FPW1ES1 = 0xde:1;
sbit	FPW2ES0 = 0xde:2;
sbit	FPW2ES1 = 0xde:3;
sbit	FPW3ES0 = 0xde:4;
sbit	FPW3ES1 = 0xde:5;
sfr	STKP = 0xdf;
sbit	FSTKPB0 = 0xdf:0;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB2 = 0xdf:2;
sbit	FGIE = 0xdf:7;
sfr	P1UR = 0xe1;
sfr	P2UR = 0xe2;
sfr	P4UR = 0xe4;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	STK7L = 0xF0;
sfr	STK7H = 0xF1;
sfr	STK6L = 0xF2;
sfr	STK6H = 0xF3;
sfr	STK5L = 0xF4;
sfr	STK5H = 0xF5;
sfr	STK4L = 0xF6;
sfr	STK4H = 0xF7;
sfr	STK3L = 0xF8;
sfr	STK3H = 0xF9;
sfr	STK2L = 0xFA;
sfr	STK2H = 0xFB;
sfr	STK1L = 0xFC;
sfr	STK1H = 0xFD;
sfr	STK0L = 0xFE;
sfr	STK0H = 0xFF;
#endif
