/******************************************************************
;UPDATA DATE:2020/04/15
;USER:Cuiyn
;HS23P6631
******************************************************************/
#ifndef _DEF_H
#define _DEF_H

/////////////////////////////////////////
struct bitRegister{
	unsigned bit0:1;
	unsigned bit1:1;
	unsigned bit2:1;
	unsigned bit3:1;
	unsigned bit4:1;
	unsigned bit5:1;
	unsigned bit6:1;
	unsigned bit7:1;
};
//////////////////////////////////////////
typedef unsigned char 	BYTE;
typedef unsigned long 	WORD;
typedef double 			DWORD;
////////////////////////////////////////////
//sfr define for HS23P6610
////////////////////////////////////////////
//=================================================
//¼Ä´æÆ÷ºê¶¨Òå 
//=================================================
//0X80~0X8F
sfr		L 		= 	0x80;
sfr		H		= 	0x81;
sfr		R		= 	0x82;
sfr		Z 		= 	0x83;
sfr		Y 		= 	0x84;

sfr		PFLAG 	= 	0x86;
sfr		STATUS 	= 	0x86;
	sbit	FZ		=	0x86:0;
	sbit	FDC		=	0x86:1;
	sbit	FC		=	0x86:2;
	
	sbit	FLVD24	=	0x86:4;
	sbit	FLVD36	=	0x86:5;
	sbit	FNPD	=	0x86:6;
	sbit	FNT0	=	0x86:7;
	
sfr		RBANK 	= 	0x87;
	sbit	FRBANKS0=	0x87:0;

//=================================================
//0XA0~0XAF
sfr		PTADCON	= 	0xA4;
	sbit	FP2CON1	=	0xA4:1;
	sbit	FP2CON2	=	0xA4:2;	
	sbit	FP2CON3	=	0xA4:3;	
	sbit	FP2CON4	=	0xA4:4;
	
sfr		ADCSEL	= 	0xA5;
	sbit	FAD7_VREF_SEL	=	0xA5:3;	
	sbit	FCHS0			=	0xA5:4;
	sbit	FCHS1			=	0xA5:5;
	sbit	FCHS2			=	0xA5:6;
	sbit	FGCHS			=	0xA5:7;
	
sfr		ADRES_H	= 	0xA6;
sfr		ADCON	= 	0xA7;
	sbit	FLDOEN			=	0xA7:0;
	sbit	FAD7EN			=	0xA7:1;
	sbit	FLIGHT_R_EN		=	0xA7:2;	
	sbit	FADC_CLK_SEL	=	0xA7:3;	
	sbit	FSAD7ONTM		=	0xA7:4;
	sbit	FSAD7SENS		=	0xA7:5;
	sbit	FSBPLP			=	0xA7:6;
	sbit	FSAD14D			=	0xA7:7;

sfr		OPTION	= 	0xA8;
	sbit	FWDT0		=	0xA8:0;
	sbit	FWDT1		=	0xA8:1;
	sbit	FWDT2		=	0xA8:2;	
	sbit	FP4CON0		=	0xA8:3;
	
	sbit	FP4CON1		=	0xA8:4;	
	sbit	FADC_CLK_D0	=	0xA8:5;
	sbit	FADC_CLK_D1	=	0xA8:6;
	sbit	F64KOSC_EN	=	0xA8:7;
	
sfr		ADRES_M	= 	0xA9;
sfr		ADRES_L	= 	0xAA;

//=================================================
//0XB0~0XBF
	
sfr		I2CCON	= 	0xB4;
	sbit	FI2CEN	=	0xB4:0;
	sbit	FI2CPU	=	0xB4:1;
	sbit	FCKP	=	0xB4:2;	
	sbit	FTXAK	=	0xB4:3;
	
	sbit	FSRW	=	0xB4:4;
	sbit	FHBB	=	0xB4:5;
	sbit	FHAAS	=	0xB4:6;
	sbit	FHCF	=	0xB4:7;
	
sfr		I2CADD	= 	0xB5;
sfr		I2CBUF	= 	0xB6;


sfr		P0M		= 	0xB8;
	sbit	FP00M	=	0xB8:0;
	sbit	FP01M	=	0xB8:1;
	sbit	FP04M	=	0xB8:4;
	
sfr		PEDGE	= 	0xBF;
	sbit	FP00G1	=	0xBF:4;
	sbit	FP00G0	=	0xBF:3;

//=================================================
//0XC0~0XCF
sfr		POW		= 	0xC0;
	sbit	FP04W	=	0xC0:4;	

sfr		P2M		= 	0xC2;
	sbit	FP20M	=	0xC2:0;
	sbit	FP21M	=	0xC2:1;
	sbit	FP22M	=	0xC2:2;
	sbit	FP23M	=	0xC2:3;
	
sfr		P4M		= 	0xC4;
	sbit	FP40M	=	0xC4:0;
	sbit	FP41M	=	0xC4:1;

sfr		P5M		= 	0xC5;
	sbit	FP53M	=	0xC5:3;
	sbit	FP54M	=	0xC5:4;


sfr		INTRQ	= 	0xC8;
	sbit	FP00IRQ	=	0xC8:0;
	sbit	FINT0IF	=	0xC8:0;	
	sbit	FP01IRQ	=	0xC8:1;	
	sbit	FINT1IF	=	0xC8:1;	
	sbit	FI2CIRQ	=	0xC8:2;	
	sbit	I2CIF	=	0xC8:2;	
	
	sbit	FTC0IRQ	=	0xC8:5;	
	sbit	FTC0IF	=	0xC8:5;	
	sbit	FTC1IRQ	=	0xC8:6;	
	sbit	FTC1IF	=	0xC8:6;	
	sbit	FADCIRQ	=	0xC8:7;	
	sbit	FADCIF	=	0xC8:7;	
	
sfr		INTEN	= 	0xC9;
	sbit	FP00IEN	= 	0xC9:0;
	sbit	FINT0IE	= 	0xC9:0;
	sbit	FP01IEN	= 	0xC9:1;
	sbit	FINT1IE	= 	0xC9:1;
	sbit	FI2CIEN	= 	0xC9:2;
	sbit	FI2CIE	= 	0xC9:2;
	
	sbit	FTC0IEN	= 	0xC9:5;
	sbit	FTC0IE	= 	0xC9:5;
	sbit	FTC1IEN	= 	0xC9:6;
	sbit	FTC1IE	= 	0xC9:6;
	sbit	FADCIEN	= 	0xC9:7;
	sbit	FADCIE	= 	0xC9:7;
	
sfr		OSCM	= 	0xCA;
	sbit	FCPUM1	= 	0xCA:4;
	sbit	FCPUM0	= 	0xCA:3;	
	sbit	FCLKMD	= 	0xCA:2;	
	sbit	FSTPHX	= 	0xCA:1;
	
//sfr		WDTC	= 	0xCB;
sfr		WDTR	= 	0xCC;
sfr		TC0R	= 	0xCD;
	sfr		TCH	= 	0xCD;
	
sfr		PCL		= 	0xCE;
sfr		PCH		= 	0xCF;

//=================================================
//0XD0~0XDF
sfr		P0		= 	0xD0;
	sbit	FP00	= 	0xD0:0;	
	sbit	FP01	= 	0xD0:1;	
	sbit	FP04	= 	0xD0:4;	
	
sfr		P2		= 	0xD2;
	sbit	FP20	= 	0xD2:0;
	sbit	FP21	= 	0xD2:1;		
	sbit	FP22	= 	0xD2:2;		
	sbit	FP23	= 	0xD2:3;		
	
sfr		P4		= 	0xD4;
	sbit	FP40	= 	0xD4:0;
	sbit	FP41	= 	0xD4:1;
	
sfr		P5		= 	0xD5;
	sbit	FP53	= 	0xD5:3;
	sbit	FP54	= 	0xD5:4;
	
sfr		T0M		= 	0xD8;
	sbit	FTC0GN		= 	0xD8:1;
	sbit	FTC0X8		= 	0xD8:2;
	sbit	FTC1X8		= 	0xD8:3;
	sbit	FTC0S16		= 	0xD8:4;
	sbit	FTC1S16		= 	0xD8:5;
	
//sfr		PWMCON	= 	0xD9;
sfr		TC0M	= 	0xDA;
	sbit	FTC0ENB		= 	0xDA:7;
	sbit	FTC0R		= 	0xDA:7;
	sbit	FTC0RATE2	= 	0xDA:6;
	sbit	FTC0PS2		= 	0xDA:6;
	sbit	FTC0RATE1	= 	0xDA:5;
	sbit	FTC0PS1		= 	0xDA:5;
	sbit	FTC0RATE0	= 	0xDA:4;
	sbit	FTC0PS0		= 	0xDA:4;
	
	sbit	FTC0CKS		= 	0xDA:3;
	sbit	FALOAD0		= 	0xDA:2;
	sbit	FTC0OUT		= 	0xDA:1;
	sbit	FPWM0OUT	= 	0xDA:0;
	sbit	FPWM0EN		= 	0xDA:0;

sfr		TC0C	= 	0xDB;
sfr		TC1M	= 	0xDC;
	sbit	FTC1ENB		= 	0xDC:7;
	sbit	FTC1R		= 	0xDC:7;
	sbit	FTC1RATE2	= 	0xDC:6;
	sbit	FTC1PS2		= 	0xDC:6;
	sbit	FTC1RATE1	= 	0xDC:5;
	sbit	FTC1PS1		= 	0xDC:5;
	sbit	FTC1RATE0	= 	0xDC:4;
	sbit	FTC1PS0		= 	0xDC:4;
	
	sbit	FTC1CKS		= 	0xDC:3;
	sbit	FALOAD1    	= 	0xDC:2;
	sbit	FTC1OUT    	= 	0xDC:1;
	sbit	FPWM1OUT   	= 	0xDC:0;
	sbit	FPWM1EN   	= 	0xDC:0;
	
sfr		TC1C	= 	0xDD;
sfr		TC1R	= 	0xDE;
sfr		STKP	= 	0xDF;
	sbit	FGIE		= 	0xDF:7;
	sbit	FSTKPB2		= 	0xDF:2;
	sbit	FSTKPB1		= 	0xDF:1;
	sbit	FSTKPB0		= 	0xDF:0;

//=================================================
//0XE0~0XEF
sfr		P0UR	= 	0xE0;
	sbit	FP00R		= 	0xE0:0;
	sbit	FP01R		= 	0xE0:1;
	
sfr		P2UR	= 	0xE2;
	sbit	FP20R		= 	0xE2:0;
	sbit	FP21R		= 	0xE2:1;
	sbit	FP22R		= 	0xE2:2;
	sbit	FP23R		= 	0xE2:3;

sfr		P4UR		= 	0xE4;
	sbit	FP40R		= 	0xE4:0;
	sbit	FP41R		= 	0xE4:1;
	
sfr		P5UR		= 	0xE5;
	sbit	FP53R		= 	0xE5:3;
	sbit	FP54R		= 	0xE5:4;
	
sfr		_HL		= 	0xE6;
sfr		_YZ		= 	0xE7;

sfr		TC0R0	= 	0xE9;
sfr		TC0R1	= 	0xEA;
sfr		TC0R2	= 	0xEB;

//=================================================
//0XF0~0XFF
sfr		STK7L	= 	0xF0;
sfr		STK7H	= 	0xF1;
sfr		STK6L	= 	0xF2;
sfr		STK6H	= 	0xF3;
sfr		STK5L	= 	0xF4;
sfr		STK5H	= 	0xF5;
sfr		STK4L	= 	0xF6;
sfr		STK4H	= 	0xF7;

sfr		STK3L	= 	0xF8;
sfr		STK3H	= 	0xF9;
sfr		STK2L	= 	0xFA;
sfr		STK2H	= 	0xFB;
sfr		STK1L	= 	0xFC;
sfr		STK1H	= 	0xFD;
sfr		STK0L	= 	0xFE;
sfr		STK0H	= 	0xFF;

//=================================================
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}

/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
#define HIBYTE(wval)		*(((BYTE*)(&wval))+1)
#define LWBYTE(wval)		*(((BYTE*)(&wval))+0)

#define HIWORD(wval)		*(((WORD*)(&wval))+1)
#define LWWORD(wval)		*(((WORD*)(&wval))+0)


#endif
