
/**************************************************************
//V1.1：
//Special function register definitions
IC Type Support:
	HS16F2612,
	HS16F2612,
//Updata:20230801
//Designer:WYH
//------------------------------------------------------------
//Updata:20230808
//Designer:(LvBuWei-CHECK-)
**************************************************************/
#ifndef __HS16F2612_H
#define __HS16F2612_H


/*
 通用寄存器：
 bank0:20H~6FH【80-bytes】;
 bank1:A0H~EFH【80-bytes】;
 bank0~3:70H~7FH【16-bytes】public;
 
 EEPROM：256*8
*/


//------------------------------------------------------------
// BANK0~3 public Special function register definitions
//------------------------------------------------------------

// Register: INDF
volatile unsigned char		INDF	@ 0x000;

// Register: PCL
volatile unsigned char      PCL		@ 0x002;

// Register: STATUS
volatile unsigned char      STATUS	@ 0x003;
	volatile bit FC                	@ ((unsigned)&STATUS*8)+0;
	volatile bit FDC                @ ((unsigned)&STATUS*8)+1;
	volatile bit FZ                 @ ((unsigned)&STATUS*8)+2;
	volatile bit FPD                @ ((unsigned)&STATUS*8)+3;
	volatile bit FTO                @ ((unsigned)&STATUS*8)+4;
	volatile bit RP0                @ ((unsigned)&STATUS*8)+5;
	volatile bit RP1                @ ((unsigned)&STATUS*8)+6;
	volatile bit IRP                @ ((unsigned)&STATUS*8)+7;

	volatile bit CARRY               @ ((unsigned)&STATUS*8)+0;
	volatile bit C	                 @ ((unsigned)&STATUS*8)+0;
	volatile bit DC                  @ ((unsigned)&STATUS*8)+1;
	volatile bit Z                   @ ((unsigned)&STATUS*8)+2;
	volatile bit ZERO                @ ((unsigned)&STATUS*8)+2;
	volatile bit NPD                 @ ((unsigned)&STATUS*8)+3;
	volatile bit nPD                 @ ((unsigned)&STATUS*8)+3;
	volatile bit NTO                 @ ((unsigned)&STATUS*8)+4;
	volatile bit nTO                 @ ((unsigned)&STATUS*8)+4;
	volatile bit RST                 @ ((unsigned)&STATUS*8)+7;

// Register: FSR
volatile unsigned char		FSR		@ 0x004;
	volatile bit FSR7               @ ((unsigned)&FSR*8)+7;

// Register: PCHBUF
volatile unsigned char		PCLATH		@ 0x00A;
#define 	PCHBUF	PCLATH 	 
	volatile bit PCH0                 @ ((unsigned)&PCLATH*8)+0;
	volatile bit PCH1                 @ ((unsigned)&PCLATH*8)+1;
	volatile bit PCH2                 @ ((unsigned)&PCLATH*8)+2;

// Register: INTCON
volatile unsigned char		INTCON		@ 0x00B;
	volatile bit FPAIF					@ ((unsigned)&INTCON*8)+0;
	volatile bit FINTIF					@ ((unsigned)&INTCON*8)+1;
	volatile bit FT0IF					@ ((unsigned)&INTCON*8)+2;
	volatile bit FPAIE					@ ((unsigned)&INTCON*8)+3;
	volatile bit FINTIE					@ ((unsigned)&INTCON*8)+4;
	volatile bit FT0IE					@ ((unsigned)&INTCON*8)+5;
	volatile bit FPEIE					@ ((unsigned)&INTCON*8)+6;
	volatile bit FGIE					@ ((unsigned)&INTCON*8)+7;
	
	volatile bit PAIF					@ ((unsigned)&INTCON*8)+0;
	volatile bit INTIF					@ ((unsigned)&INTCON*8)+1;
	volatile bit T0IF					@ ((unsigned)&INTCON*8)+2;
	volatile bit PAIE					@ ((unsigned)&INTCON*8)+3;
	volatile bit INTIE					@ ((unsigned)&INTCON*8)+4;
	volatile bit T0IE					@ ((unsigned)&INTCON*8)+5;
	volatile bit PEIE					@ ((unsigned)&INTCON*8)+6;
	volatile bit GIE					@ ((unsigned)&INTCON*8)+7;



//------------------------------------------------------------
// BANK0 Special function register definitions
//------------------------------------------------------------
// Register: TMR0
volatile unsigned char      TMR0	@ 0x001;

// Register: PORTA
volatile unsigned char		PORTA	@ 0x005;
volatile unsigned char      RA      @ 0x005;
volatile unsigned char      PA      @ 0x005;
// bit and bitfield definitions
	volatile bit FRA0                 @ ((unsigned)&PORTA*8)+0;
	volatile bit FRA1                 @ ((unsigned)&PORTA*8)+1;
	volatile bit FRA2                 @ ((unsigned)&PORTA*8)+2;
	volatile bit FRA3                 @ ((unsigned)&PORTA*8)+3;
	volatile bit FRA4                 @ ((unsigned)&PORTA*8)+4;
	volatile bit FRA5                 @ ((unsigned)&PORTA*8)+5;
	volatile bit FRA6                 @ ((unsigned)&PORTA*8)+6;
	volatile bit FRA7                 @ ((unsigned)&PORTA*8)+7;

	volatile bit RA0                 @ ((unsigned)&PORTA*8)+0;
	volatile bit RA1                 @ ((unsigned)&PORTA*8)+1;
	volatile bit RA2                 @ ((unsigned)&PORTA*8)+2;
	volatile bit RA3                 @ ((unsigned)&PORTA*8)+3;
	volatile bit RA4                 @ ((unsigned)&PORTA*8)+4;
	volatile bit RA5                 @ ((unsigned)&PORTA*8)+5;
	volatile bit RA6                 @ ((unsigned)&PORTA*8)+6;
	volatile bit RA7                 @ ((unsigned)&PORTA*8)+7;

	volatile bit FPA0                 @ ((unsigned)&PORTA*8)+0;
	volatile bit FPA1                 @ ((unsigned)&PORTA*8)+1;
	volatile bit FPA2                 @ ((unsigned)&PORTA*8)+2;
	volatile bit FPA3                 @ ((unsigned)&PORTA*8)+3;
	volatile bit FPA4                 @ ((unsigned)&PORTA*8)+4;
	volatile bit FPA5                 @ ((unsigned)&PORTA*8)+5;
	volatile bit FPA6                 @ ((unsigned)&PORTA*8)+6;
	volatile bit FPA7                 @ ((unsigned)&PORTA*8)+7;

	volatile bit PA0                 @ ((unsigned)&PORTA*8)+0;
	volatile bit PA1                 @ ((unsigned)&PORTA*8)+1;
	volatile bit PA2                 @ ((unsigned)&PORTA*8)+2;
	volatile bit PA3                 @ ((unsigned)&PORTA*8)+3;
	volatile bit PA4                 @ ((unsigned)&PORTA*8)+4;
	volatile bit PA5                 @ ((unsigned)&PORTA*8)+5;
	volatile bit PA6                 @ ((unsigned)&PORTA*8)+6;
	volatile bit PA7                 @ ((unsigned)&PORTA*8)+7;

// Register: PORTB
volatile unsigned char		PORTC	@ 0x007;
volatile unsigned char     	RC      @ 0x007;
volatile unsigned char     	PC      @ 0x007;
// bit and bitfield definitions
	volatile bit FRC0                 @ ((unsigned)&PORTC*8)+0;
	volatile bit FRC1                 @ ((unsigned)&PORTC*8)+1;
	volatile bit FRC2                 @ ((unsigned)&PORTC*8)+2;
	volatile bit FRC3                 @ ((unsigned)&PORTC*8)+3;
	volatile bit FRC4                 @ ((unsigned)&PORTC*8)+4;
	volatile bit FRC5                 @ ((unsigned)&PORTC*8)+5;

	volatile bit RC0                 @ ((unsigned)&PORTC*8)+0;
	volatile bit RC1                 @ ((unsigned)&PORTC*8)+1;
	volatile bit RC2                 @ ((unsigned)&PORTC*8)+2;
	volatile bit RC3                 @ ((unsigned)&PORTC*8)+3;
	volatile bit RC4                 @ ((unsigned)&PORTC*8)+4;
	volatile bit RC5                 @ ((unsigned)&PORTC*8)+5;

	volatile bit FPC0                 @ ((unsigned)&PORTC*8)+0;
	volatile bit FPC1                 @ ((unsigned)&PORTC*8)+1;
	volatile bit FPC2                 @ ((unsigned)&PORTC*8)+2;
	volatile bit FPC3                 @ ((unsigned)&PORTC*8)+3;
	volatile bit FPC4                 @ ((unsigned)&PORTC*8)+4;
	volatile bit FPC5                 @ ((unsigned)&PORTC*8)+5;

	volatile bit PC0                 @ ((unsigned)&PORTC*8)+0;
	volatile bit PC1                 @ ((unsigned)&PORTC*8)+1;
	volatile bit PC2                 @ ((unsigned)&PORTC*8)+2;
	volatile bit PC3                 @ ((unsigned)&PORTC*8)+3;
	volatile bit PC4                 @ ((unsigned)&PORTC*8)+4;
	volatile bit PC5                 @ ((unsigned)&PORTC*8)+5;

// Register: PIR1
volatile unsigned char		PIR1		@ 0x00C;
	volatile bit FT1IF					@ ((unsigned)&PIR1*8)+0;
	volatile bit FT2IF					@ ((unsigned)&PIR1*8)+1;
	volatile bit FCCP1IF				@ ((unsigned)&PIR1*8)+2;
	volatile bit FADCIF					@ ((unsigned)&PIR1*8)+6;
	
	volatile bit T1IF					@ ((unsigned)&PIR1*8)+0;
	volatile bit T2IF					@ ((unsigned)&PIR1*8)+1;
	volatile bit CCP1IF					@ ((unsigned)&PIR1*8)+2;
	volatile bit ADCIF					@ ((unsigned)&PIR1*8)+6;

// Register: PIR2
volatile unsigned char		PIR2	  @ 0x00D;
	volatile bit FT3IF					@ ((unsigned)&PIR2*8)+1;
	volatile bit FT4IF					@ ((unsigned)&PIR2*8)+2;
	volatile bit FT5IF					@ ((unsigned)&PIR2*8)+3;
	volatile bit FC1IF					@ ((unsigned)&PIR2*8)+5;
	volatile bit FC2IF					@ ((unsigned)&PIR2*8)+6;
	
	volatile bit T3IF					@ ((unsigned)&PIR2*8)+1;
	volatile bit T4IF					@ ((unsigned)&PIR2*8)+2;
	volatile bit T5IF					@ ((unsigned)&PIR2*8)+3;
	volatile bit C1IF					@ ((unsigned)&PIR2*8)+5;
	volatile bit C2IF					@ ((unsigned)&PIR2*8)+6;

// Register: PCHCON
volatile unsigned char		PCHCON		@ 0x012;
	volatile bit FPHC0					@ ((unsigned)&PCHCON*8)+0;
	volatile bit FPHC1					@ ((unsigned)&PCHCON*8)+1;
	volatile bit FPHC2					@ ((unsigned)&PCHCON*8)+2;
	volatile bit FPHC3					@ ((unsigned)&PCHCON*8)+3;
	volatile bit FPHC4					@ ((unsigned)&PCHCON*8)+4;
	volatile bit FPHC5					@ ((unsigned)&PCHCON*8)+5;
	
	volatile bit PHC0					@ ((unsigned)&PCHCON*8)+0;
	volatile bit PHC1					@ ((unsigned)&PCHCON*8)+1;
	volatile bit PHC2					@ ((unsigned)&PCHCON*8)+2;
	volatile bit PHC3					@ ((unsigned)&PCHCON*8)+3;
	volatile bit PHC4					@ ((unsigned)&PCHCON*8)+4;
	volatile bit PHC5					@ ((unsigned)&PCHCON*8)+5;

// Register: PCDCON
volatile unsigned char		PCDCON		@ 0x013;
	volatile bit FPDC0					@ ((unsigned)&PCDCON*8)+0;
	volatile bit FPDC1					@ ((unsigned)&PCDCON*8)+1;
	volatile bit FPDC2					@ ((unsigned)&PCDCON*8)+2;
	volatile bit FPDC3					@ ((unsigned)&PCDCON*8)+3;
	volatile bit FPDC4					@ ((unsigned)&PCDCON*8)+4;
	volatile bit FPDC5					@ ((unsigned)&PCDCON*8)+5;
	
	volatile bit PDC0					@ ((unsigned)&PCDCON*8)+0;
	volatile bit PDC1					@ ((unsigned)&PCDCON*8)+1;
	volatile bit PDC2					@ ((unsigned)&PCDCON*8)+2;
	volatile bit PDC3					@ ((unsigned)&PCDCON*8)+3;
	volatile bit PDC4					@ ((unsigned)&PCDCON*8)+4;
	volatile bit PDC5					@ ((unsigned)&PCDCON*8)+5;

// Register: ADB1
volatile unsigned char		ADB1		@ 0x016;

// Register: ADF0
volatile unsigned char      ADF0		@ 0x018;
	volatile bit ADF7					@ ((unsigned)&PCDCON*8)+7;

// Register: ANSEL
volatile unsigned char		ANSEL		@ 0x01A;
	volatile bit FANSEL0				@ ((unsigned)&ANSEL*8)+0;
	volatile bit FANSEL1				@ ((unsigned)&ANSEL*8)+1;
	volatile bit FANSEL2				@ ((unsigned)&ANSEL*8)+2;
	volatile bit FANSEL3				@ ((unsigned)&ANSEL*8)+3;
	volatile bit FANSEL4				@ ((unsigned)&ANSEL*8)+4;
	volatile bit FANSEL5				@ ((unsigned)&ANSEL*8)+5;
	volatile bit FANSEL6				@ ((unsigned)&ANSEL*8)+6;

	volatile bit ANSEL0					@ ((unsigned)&ANSEL*8)+0;
	volatile bit ANSEL1					@ ((unsigned)&ANSEL*8)+1;
	volatile bit ANSEL2					@ ((unsigned)&ANSEL*8)+2;
	volatile bit ANSEL3					@ ((unsigned)&ANSEL*8)+3;
	volatile bit ANSEL4					@ ((unsigned)&ANSEL*8)+4;
	volatile bit ANSEL5					@ ((unsigned)&ANSEL*8)+5;
	volatile bit ANSEL6					@ ((unsigned)&ANSEL*8)+6;
	
// Register: ADM
volatile unsigned char		ADM		  @ 0x01B;
	volatile bit FCHS0					@ ((unsigned)&ADM*8)+0;
	volatile bit FCHS1					@ ((unsigned)&ADM*8)+1;
	volatile bit FCHS2					@ ((unsigned)&ADM*8)+2;
	volatile bit FCHS3					@ ((unsigned)&ADM*8)+3;
	volatile bit FGCHS					@ ((unsigned)&ADM*8)+4;
	volatile bit FEOC					@ ((unsigned)&ADM*8)+5;
	volatile bit FADS					@ ((unsigned)&ADM*8)+6;
	volatile bit FADENB					@ ((unsigned)&ADM*8)+7;
	
	volatile bit CHS0					@ ((unsigned)&ADM*8)+0;
	volatile bit CHS1					@ ((unsigned)&ADM*8)+1;
	volatile bit CHS2					@ ((unsigned)&ADM*8)+2;
	volatile bit CHS3					@ ((unsigned)&ADM*8)+3;
	volatile bit GCHS					@ ((unsigned)&ADM*8)+4;
	volatile bit EOC					@ ((unsigned)&ADM*8)+5;
	volatile bit ADS					@ ((unsigned)&ADM*8)+6;
	volatile bit ADENB					@ ((unsigned)&ADM*8)+7;

// Register: ADB
volatile unsigned char		ADB		  @ 0x01C;

// Register: ADR
volatile unsigned char      ADR		  @ 0x01D;
	volatile bit FADCKS0				@ ((unsigned)&ADR*8)+4;
	volatile bit FADCKS1				@ ((unsigned)&ADR*8)+6;
	
	volatile bit ADCKS0					@ ((unsigned)&ADR*8)+4;
	volatile bit ADCKS1					@ ((unsigned)&ADR*8)+6;

// Register: ADT
volatile unsigned char		ADT		  @ 0x01E;

// Register: VREF
volatile unsigned char		VREF	  @ 0x01F;
#define 	VREFH 		VREF
	volatile bit FVHS0					@ ((unsigned)&VREF*8)+0;
	volatile bit FVHS1					@ ((unsigned)&VREF*8)+1;
	volatile bit FEVHENB				@ ((unsigned)&VREF*8)+7;
	
	volatile bit VHS0					@ ((unsigned)&VREF*8)+0;
	volatile bit VHS1					@ ((unsigned)&VREF*8)+1;
	volatile bit EVHENB					@ ((unsigned)&VREF*8)+7;

//------------------------------------------------------------
// BANK1 Special function register definitions
//------------------------------------------------------------
// Register: OPTIONR
volatile unsigned char	OPTIONR			@ 0x081;
#define 	OPTION 		OPTIONR
#define 	OPTION_REG 	OPTIONR
// bit and bitfield definitions
	volatile bit FPS0               @ ((unsigned)&OPTIONR*8)+0;
	volatile bit FPS1               @ ((unsigned)&OPTIONR*8)+1;
	volatile bit FPS2               @ ((unsigned)&OPTIONR*8)+2;
	volatile bit FPSA               @ ((unsigned)&OPTIONR*8)+3;
	volatile bit FT0SE              @ ((unsigned)&OPTIONR*8)+4;
	volatile bit FT0CS              @ ((unsigned)&OPTIONR*8)+5;
	volatile bit FINTEDGE			@ ((unsigned)&OPTIONR*8)+6;
	
	volatile bit PS0				@ ((unsigned)&OPTIONR*8)+0;
	volatile bit PS1				@ ((unsigned)&OPTIONR*8)+1;
	volatile bit PS2				@ ((unsigned)&OPTIONR*8)+2;
	volatile bit PSA				@ ((unsigned)&OPTIONR*8)+3;
	volatile bit T0SE				@ ((unsigned)&OPTIONR*8)+4;
	volatile bit T0CS				@ ((unsigned)&OPTIONR*8)+5;
	volatile bit INTEDGE			@ ((unsigned)&OPTIONR*8)+6;

// Register: TRISA
volatile unsigned char           TRISA		@ 0x085;
	volatile bit FTRISA0				@ ((unsigned)&TRISA*8)+0;
	volatile bit FTRISA1				@ ((unsigned)&TRISA*8)+1;
	volatile bit FTRISA2				@ ((unsigned)&TRISA*8)+2;
	volatile bit FTRISA3				@ ((unsigned)&TRISA*8)+3;
	volatile bit FTRISA4				@ ((unsigned)&TRISA*8)+4;
	volatile bit FTRISA5				@ ((unsigned)&TRISA*8)+5;
	volatile bit FTRISA6				@ ((unsigned)&TRISA*8)+6;
	volatile bit FTRISA7				@ ((unsigned)&TRISA*8)+7;
	
	volatile bit TRISA0					@ ((unsigned)&TRISA*8)+0;
	volatile bit TRISA1					@ ((unsigned)&TRISA*8)+1;
	volatile bit TRISA2					@ ((unsigned)&TRISA*8)+2;
	volatile bit TRISA3					@ ((unsigned)&TRISA*8)+3;
	volatile bit TRISA4					@ ((unsigned)&TRISA*8)+4;
	volatile bit TRISA5					@ ((unsigned)&TRISA*8)+5;
	volatile bit TRISA6					@ ((unsigned)&TRISA*8)+6;
	volatile bit TRISA7					@ ((unsigned)&TRISA*8)+7;

// Register: TRISC
volatile unsigned char           TRISC		  @ 0x087;
	volatile bit FTRISC0				@ ((unsigned)&TRISC*8)+0;
	volatile bit FTRISC1				@ ((unsigned)&TRISC*8)+1;
	volatile bit FTRISC2				@ ((unsigned)&TRISC*8)+2;
	volatile bit FTRISC3				@ ((unsigned)&TRISC*8)+3;
	volatile bit FTRISC4				@ ((unsigned)&TRISC*8)+4;
	volatile bit FTRISC5				@ ((unsigned)&TRISC*8)+5;

	volatile bit TRISC0				@ ((unsigned)&TRISC*8)+0;
	volatile bit TRISC1				@ ((unsigned)&TRISC*8)+1;
	volatile bit TRISC2				@ ((unsigned)&TRISC*8)+2;
	volatile bit TRISC3				@ ((unsigned)&TRISC*8)+3;
	volatile bit TRISC4				@ ((unsigned)&TRISC*8)+4;
	volatile bit TRISC5				@ ((unsigned)&TRISC*8)+5;
	
// Register: PIE1
volatile unsigned char           PIE1		  @ 0x08C;
	volatile bit FT1IE					@ ((unsigned)&PIE1*8)+0;
	volatile bit FT2IE					@ ((unsigned)&PIE1*8)+1;
	volatile bit FCCP1IE				@ ((unsigned)&PIE1*8)+2;
	volatile bit FADCIE					@ ((unsigned)&PIE1*8)+6;
	
	volatile bit T1IE					@ ((unsigned)&PIE1*8)+0;
	volatile bit T2IE					@ ((unsigned)&PIE1*8)+1;
	volatile bit CCP1IE					@ ((unsigned)&PIE1*8)+2;
	volatile bit ADCIE					@ ((unsigned)&PIE1*8)+6;

// Register: PIE2
volatile unsigned char           PIE2		  @ 0x08D;
	volatile bit FT3IE					@ ((unsigned)&PIE2*8)+1;
	volatile bit FT4IE					@ ((unsigned)&PIE2*8)+2;
	volatile bit FT5IE					@ ((unsigned)&PIE2*8)+3;
	volatile bit FC1IE					@ ((unsigned)&PIE2*8)+5;
	volatile bit FC2IE					@ ((unsigned)&PIE2*8)+6;
	
	volatile bit T3IE					@ ((unsigned)&PIE2*8)+1;
	volatile bit T4IE					@ ((unsigned)&PIE2*8)+2;
	volatile bit T5IE					@ ((unsigned)&PIE2*8)+3;
	volatile bit C1IE					@ ((unsigned)&PIE2*8)+5;
	volatile bit C2IE					@ ((unsigned)&PIE2*8)+6;

// Register: PCON
volatile unsigned char           PCON		  @ 0x08E;
	volatile bit FLVDTE					@ ((unsigned)&PCON*8)+5;
	volatile bit FWDTE					@ ((unsigned)&PCON*8)+7;

	volatile bit LVDTE					@ ((unsigned)&PCON*8)+5;
	volatile bit WDTE					@ ((unsigned)&PCON*8)+7;

// Register: WUACON
volatile unsigned char           WUACON		  @ 0x08F;
	volatile bit FWUA0					@ ((unsigned)&WUACON*8)+0;
	volatile bit FWUA1					@ ((unsigned)&WUACON*8)+1;
	volatile bit FWUA2					@ ((unsigned)&WUACON*8)+2;
	volatile bit FWUA3					@ ((unsigned)&WUACON*8)+3;
	volatile bit FWUA4					@ ((unsigned)&WUACON*8)+4;
	volatile bit FWUA5					@ ((unsigned)&WUACON*8)+5;
	volatile bit FWUA6					@ ((unsigned)&WUACON*8)+6;
	volatile bit FWUA7					@ ((unsigned)&WUACON*8)+7;
	
	volatile bit WUA0					@ ((unsigned)&WUACON*8)+0;
	volatile bit WUA1					@ ((unsigned)&WUACON*8)+1;
	volatile bit WUA2					@ ((unsigned)&WUACON*8)+2;
	volatile bit WUA3					@ ((unsigned)&WUACON*8)+3;
	volatile bit WUA4					@ ((unsigned)&WUACON*8)+4;
	volatile bit WUA5					@ ((unsigned)&WUACON*8)+5;
	volatile bit WUA6					@ ((unsigned)&WUACON*8)+6;
	volatile bit WUA7					@ ((unsigned)&WUACON*8)+7;

// Register: PAIC0
volatile unsigned char           PAIC0		 @ 0x090;
	volatile bit FPAIC00					@ ((unsigned)&PAIC0*8)+0;
	volatile bit FPAIC01					@ ((unsigned)&PAIC0*8)+1;
	volatile bit FPAIC02					@ ((unsigned)&PAIC0*8)+2;
	volatile bit FPAIC03					@ ((unsigned)&PAIC0*8)+3;
	volatile bit FPAIC04					@ ((unsigned)&PAIC0*8)+4;
	volatile bit FPAIC05					@ ((unsigned)&PAIC0*8)+5;
	volatile bit FPAIC06					@ ((unsigned)&PAIC0*8)+6;
	volatile bit FPAIC07					@ ((unsigned)&PAIC0*8)+7;
	
	volatile bit PAIC00					@ ((unsigned)&PAIC0*8)+0;
	volatile bit PAIC01					@ ((unsigned)&PAIC0*8)+1;
	volatile bit PAIC02					@ ((unsigned)&PAIC0*8)+2;
	volatile bit PAIC03					@ ((unsigned)&PAIC0*8)+3;
	volatile bit PAIC04					@ ((unsigned)&PAIC0*8)+4;
	volatile bit PAIC05					@ ((unsigned)&PAIC0*8)+5;
	volatile bit PAIC06					@ ((unsigned)&PAIC0*8)+6;
	volatile bit PAIC07					@ ((unsigned)&PAIC0*8)+7;

// Register: PCIC0
volatile unsigned char           PCIC0	  @ 0x091;
	volatile bit FPCIC00					@ ((unsigned)&PCIC0*8)+0;
	volatile bit FPCIC01					@ ((unsigned)&PCIC0*8)+1;
	volatile bit FPCIC02					@ ((unsigned)&PCIC0*8)+2;
	volatile bit FPCIC03					@ ((unsigned)&PCIC0*8)+3;
	volatile bit FPCIC04					@ ((unsigned)&PCIC0*8)+4;
	volatile bit FPCIC05					@ ((unsigned)&PCIC0*8)+5;
	volatile bit FPCIC06					@ ((unsigned)&PCIC0*8)+6;
	volatile bit FPCIC07					@ ((unsigned)&PCIC0*8)+7;
	
	volatile bit PCIC00					@ ((unsigned)&PCIC0*8)+0;
	volatile bit PCIC01					@ ((unsigned)&PCIC0*8)+1;
	volatile bit PCIC02					@ ((unsigned)&PCIC0*8)+2;
	volatile bit PCIC03					@ ((unsigned)&PCIC0*8)+3;
	volatile bit PCIC04					@ ((unsigned)&PCIC0*8)+4;
	volatile bit PCIC05					@ ((unsigned)&PCIC0*8)+5;
	volatile bit PCIC06					@ ((unsigned)&PCIC0*8)+6;
	volatile bit PCIC07					@ ((unsigned)&PCIC0*8)+7;

// Register: PAHCON
volatile unsigned char           PAHCON		  @ 0x092;
	volatile bit FPAHCON0				@ ((unsigned)&PAHCON*8)+0;
	volatile bit FPAHCON1				@ ((unsigned)&PAHCON*8)+1;
	volatile bit FPAHCON2				@ ((unsigned)&PAHCON*8)+2;
	volatile bit FPAHCON3				@ ((unsigned)&PAHCON*8)+3;
	volatile bit FPAHCON4				@ ((unsigned)&PAHCON*8)+4;
	volatile bit FPAHCON5				@ ((unsigned)&PAHCON*8)+5;
	volatile bit FPAHCON6				@ ((unsigned)&PAHCON*8)+6;
	volatile bit FPAHCON7				@ ((unsigned)&PAHCON*8)+7;
	
	volatile bit PAHCON0				@ ((unsigned)&PAHCON*8)+0;
	volatile bit PAHCON1				@ ((unsigned)&PAHCON*8)+1;
	volatile bit PAHCON2				@ ((unsigned)&PAHCON*8)+2;
	volatile bit PAHCON3				@ ((unsigned)&PAHCON*8)+3;
	volatile bit PAHCON4				@ ((unsigned)&PAHCON*8)+4;
	volatile bit PAHCON5				@ ((unsigned)&PAHCON*8)+5;
	volatile bit PAHCON6				@ ((unsigned)&PAHCON*8)+6;
	volatile bit PAHCON7				@ ((unsigned)&PAHCON*8)+7;

// Register: PADCON
volatile unsigned char           PADCON		 @ 0x093;
	volatile bit FPADCON0				@ ((unsigned)&PADCON*8)+0;
	volatile bit FPADCON1				@ ((unsigned)&PADCON*8)+1;
	volatile bit FPADCON2				@ ((unsigned)&PADCON*8)+2;
	volatile bit FPADCON3				@ ((unsigned)&PADCON*8)+3;
	volatile bit FPADCON4				@ ((unsigned)&PADCON*8)+4;
	volatile bit FPADCON5				@ ((unsigned)&PADCON*8)+5;
	volatile bit FPADCON6				@ ((unsigned)&PADCON*8)+6;
	volatile bit FPADCON7				@ ((unsigned)&PADCON*8)+7;
	
	volatile bit PADCON0				@ ((unsigned)&PADCON*8)+0;
	volatile bit PADCON1				@ ((unsigned)&PADCON*8)+1;
	volatile bit PADCON2				@ ((unsigned)&PADCON*8)+2;
	volatile bit PADCON3				@ ((unsigned)&PADCON*8)+3;
	volatile bit PADCON4				@ ((unsigned)&PADCON*8)+4;
	volatile bit PADCON5				@ ((unsigned)&PADCON*8)+5;
	volatile bit PADCON6				@ ((unsigned)&PADCON*8)+6;
	volatile bit PADCON7				@ ((unsigned)&PADCON*8)+7;

// Register: OSCM
volatile unsigned char           OSCM	  @ 0x094;
	volatile bit FCLKMD						@ ((unsigned)&OSCM*8)+0;
	volatile bit FSTPHX						@ ((unsigned)&OSCM*8)+1;
	volatile bit FXTSEL						@ ((unsigned)&OSCM*8)+2;
	volatile bit FSLCON						@ ((unsigned)&OSCM*8)+3;
	volatile bit FRTCEN						@ ((unsigned)&OSCM*8)+4;
	volatile bit FGREENEN					@ ((unsigned)&OSCM*8)+5;
	volatile bit FWAKEMODE					@ ((unsigned)&OSCM*8)+6;
	volatile bit FMONIF						@ ((unsigned)&OSCM*8)+7;
	
	volatile bit CLKMD						@ ((unsigned)&OSCM*8)+0;
	volatile bit STPHX						@ ((unsigned)&OSCM*8)+1;
	volatile bit XTSEL						@ ((unsigned)&OSCM*8)+2;
	volatile bit SLCON						@ ((unsigned)&OSCM*8)+3;
	volatile bit RTCEN						@ ((unsigned)&OSCM*8)+4;
	volatile bit GREENEN					@ ((unsigned)&OSCM*8)+5;
	volatile bit WAKEMODE					@ ((unsigned)&OSCM*8)+6;
	volatile bit MONIF						@ ((unsigned)&OSCM*8)+7;

// Register: PAODCON
volatile unsigned char           PAODCON		  @ 0x095;
	volatile bit FPAODCON0				@ ((unsigned)&PAODCON*8)+0;
	volatile bit FPAODCON1				@ ((unsigned)&PAODCON*8)+1;
	volatile bit FPAODCON2				@ ((unsigned)&PAODCON*8)+2;
	volatile bit FPAODCON3				@ ((unsigned)&PAODCON*8)+3;
	volatile bit FPAODCON4				@ ((unsigned)&PAODCON*8)+4;
	volatile bit FPAODCON5				@ ((unsigned)&PAODCON*8)+5;
	volatile bit FPAODCON6				@ ((unsigned)&PAODCON*8)+6;
	volatile bit FPAODCON7				@ ((unsigned)&PAODCON*8)+7;
	
	volatile bit PAODCON0				@ ((unsigned)&PAODCON*8)+0;
	volatile bit PAODCON1				@ ((unsigned)&PAODCON*8)+1;
	volatile bit PAODCON2				@ ((unsigned)&PAODCON*8)+2;
	volatile bit PAODCON3				@ ((unsigned)&PAODCON*8)+3;
	volatile bit PAODCON4				@ ((unsigned)&PAODCON*8)+4;
	volatile bit PAODCON5				@ ((unsigned)&PAODCON*8)+5;
	volatile bit PAODCON6				@ ((unsigned)&PAODCON*8)+6;
	volatile bit PAODCON7				@ ((unsigned)&PAODCON*8)+7;

// Register: PWMP1CON
volatile unsigned char           PWMP1CON		  @ 0x096;
	volatile bit FP1AOE						@ ((unsigned)&PWMP1CON*8)+0;
	volatile bit FP1BOE						@ ((unsigned)&PWMP1CON*8)+1;
	volatile bit FP1COE						@ ((unsigned)&PWMP1CON*8)+2;
	volatile bit FP1DOE						@ ((unsigned)&PWMP1CON*8)+3;
	volatile bit FP1EOE						@ ((unsigned)&PWMP1CON*8)+4;
	volatile bit FP1FOE						@ ((unsigned)&PWMP1CON*8)+5;
	volatile bit FP1OS						@ ((unsigned)&PWMP1CON*8)+6;
	volatile bit FAUX1EN					@ ((unsigned)&PWMP1CON*8)+7;
	
	volatile bit P1AOE						@ ((unsigned)&PWMP1CON*8)+0;
	volatile bit P1BOE						@ ((unsigned)&PWMP1CON*8)+1;
	volatile bit P1COE						@ ((unsigned)&PWMP1CON*8)+2;
	volatile bit P1DOE						@ ((unsigned)&PWMP1CON*8)+3;
	volatile bit P1EOE						@ ((unsigned)&PWMP1CON*8)+4;
	volatile bit P1FOE						@ ((unsigned)&PWMP1CON*8)+5;
	volatile bit P1OS						@ ((unsigned)&PWMP1CON*8)+6;
	volatile bit AUX1EN						@ ((unsigned)&PWMP1CON*8)+7;

// Register: ECCPAS
volatile unsigned char           ECCPAS		  @ 0x097;
	volatile bit FPSSBD0					@ ((unsigned)&ECCPAS*8)+0;
	volatile bit FPSSBD1					@ ((unsigned)&ECCPAS*8)+1;
	volatile bit FPSSAC0					@ ((unsigned)&ECCPAS*8)+2;
	volatile bit FPSSAC1					@ ((unsigned)&ECCPAS*8)+3;
	volatile bit FECCPAC0					@ ((unsigned)&ECCPAS*8)+4;
	volatile bit FECCPAC1					@ ((unsigned)&ECCPAS*8)+5;
	volatile bit FECCPAC2					@ ((unsigned)&ECCPAS*8)+6;
	volatile bit FECCPASE					@ ((unsigned)&ECCPAS*8)+7;
	
	volatile bit PSSBD0						@ ((unsigned)&ECCPAS*8)+0;
	volatile bit PSSBD1						@ ((unsigned)&ECCPAS*8)+1;
	volatile bit PSSAC0						@ ((unsigned)&ECCPAS*8)+2;
	volatile bit PSSAC1						@ ((unsigned)&ECCPAS*8)+3;
	volatile bit ECCPAC0					@ ((unsigned)&ECCPAS*8)+4;
	volatile bit ECCPAC1					@ ((unsigned)&ECCPAS*8)+5;
	volatile bit ECCPAC2					@ ((unsigned)&ECCPAS*8)+6;
	volatile bit ECCPASE					@ ((unsigned)&ECCPAS*8)+7;

// Register: CCPCON
volatile unsigned char           CCPCON		 @ 0x098;
	volatile bit FCCP1M0					@ ((unsigned)&CCPCON*8)+0;
	volatile bit FCCP1M1					@ ((unsigned)&CCPCON*8)+1;
	volatile bit FCCP1M2					@ ((unsigned)&CCPCON*8)+2;
	volatile bit FCCP1M3					@ ((unsigned)&CCPCON*8)+3;
	volatile bit FP1M0						@ ((unsigned)&CCPCON*8)+6;
	volatile bit FP1M1						@ ((unsigned)&CCPCON*8)+7;

	volatile bit CCP1M0						@ ((unsigned)&CCPCON*8)+0;
	volatile bit CCP1M1						@ ((unsigned)&CCPCON*8)+1;
	volatile bit CCP1M2						@ ((unsigned)&CCPCON*8)+2;
	volatile bit CCP1M3						@ ((unsigned)&CCPCON*8)+3;
	volatile bit P1M0						@ ((unsigned)&CCPCON*8)+6;
	volatile bit P1M1						@ ((unsigned)&CCPCON*8)+7;

// Register: CCPRH
volatile unsigned char           CCPRH		  @ 0x099;
// Register: CCPRL
volatile unsigned char           CCPRL		  @ 0x09A;

// Register: T1CON
volatile unsigned char           T1CON		  @ 0x09B;
	volatile bit FT1REN						@ ((unsigned)&T1CON*8)+0;
	volatile bit FT1CKS0					@ ((unsigned)&T1CON*8)+1;
	volatile bit FT1SYNC					@ ((unsigned)&T1CON*8)+2;
	volatile bit FT1CKS1					@ ((unsigned)&T1CON*8)+3;
	volatile bit FT1CK0						@ ((unsigned)&T1CON*8)+4;
	volatile bit FT1CK1						@ ((unsigned)&T1CON*8)+5;
	volatile bit FT1GE						@ ((unsigned)&T1CON*8)+6;
	volatile bit FT1GINV					@ ((unsigned)&T1CON*8)+7;
	
	volatile bit T1REN						@ ((unsigned)&T1CON*8)+0;
	volatile bit T1CKS0						@ ((unsigned)&T1CON*8)+1;
	volatile bit T1SYNC						@ ((unsigned)&T1CON*8)+2;
	volatile bit T1CKS1						@ ((unsigned)&T1CON*8)+3;
	volatile bit T1CK0						@ ((unsigned)&T1CON*8)+4;
	volatile bit T1CK1						@ ((unsigned)&T1CON*8)+5;
	volatile bit T1GE						@ ((unsigned)&T1CON*8)+6;
	volatile bit T1GINV						@ ((unsigned)&T1CON*8)+7;

// Register: T1TH
volatile unsigned char           T1TH		  @ 0x09C;

// Register: T1TL
volatile unsigned char           T1TL		  @ 0x09D;

// Register: T2DTL
volatile unsigned char           T2DTL		  @ 0x09E;

// Register: T2DTH
volatile unsigned char           T2DTH		  @ 0x09F;


//------------------------------------------------------------
// BANK2 Special function register definitions
//------------------------------------------------------------
// Register: 
volatile unsigned char           LVDCON			  @ 0x10C;
	volatile bit FLVDS0						@ ((unsigned)&LVDCON*8)+0;
	volatile bit FLVDS1						@ ((unsigned)&LVDCON*8)+1;
	volatile bit FLVDS2						@ ((unsigned)&LVDCON*8)+2;
	volatile bit FLVDS3						@ ((unsigned)&LVDCON*8)+3;
	volatile bit FLVDEN						@ ((unsigned)&LVDCON*8)+4;
	volatile bit FLVDIF						@ ((unsigned)&LVDCON*8)+5;
	volatile bit FMONEN						@ ((unsigned)&LVDCON*8)+6;
	
	volatile bit LVDS0						@ ((unsigned)&LVDCON*8)+0;
	volatile bit LVDS1						@ ((unsigned)&LVDCON*8)+1;
	volatile bit LVDS2						@ ((unsigned)&LVDCON*8)+2;
	volatile bit LVDS3						@ ((unsigned)&LVDCON*8)+3;
	volatile bit LVDEN						@ ((unsigned)&LVDCON*8)+4;
	volatile bit LVDIF						@ ((unsigned)&LVDCON*8)+5;
	volatile bit MONEN						@ ((unsigned)&LVDCON*8)+6;

// Register: EEADR
volatile unsigned char           EEADR			  @ 0x10D;
volatile unsigned char           EEADRL			  @ 0x10D;

// Register: EEDAT
volatile unsigned char           EEDAT			  @ 0x10E;
volatile unsigned char           EEDATL			  @ 0x10E;

// Register: 
volatile unsigned char           EECON			  @ 0x10F;
	volatile bit FREADEE					@ ((unsigned)&EECON*8)+0;
	volatile bit FPROGEE					@ ((unsigned)&EECON*8)+1;
	volatile bit FERASEEE					@ ((unsigned)&EECON*8)+2;
	volatile bit FERSALLEE					@ ((unsigned)&EECON*8)+3;
	volatile bit FERS16						@ ((unsigned)&EECON*8)+4;
	volatile bit FTIMEE0					@ ((unsigned)&EECON*8)+5;
	volatile bit FTIMEE1					@ ((unsigned)&EECON*8)+6;
	
	volatile bit READEE					@ ((unsigned)&EECON*8)+0;
	volatile bit PROGEE					@ ((unsigned)&EECON*8)+1;
	volatile bit ERASEEE				@ ((unsigned)&EECON*8)+2;
	volatile bit ERSALLEE				@ ((unsigned)&EECON*8)+3;
	volatile bit ERS16					@ ((unsigned)&EECON*8)+4;
	volatile bit TIMEE0					@ ((unsigned)&EECON*8)+5;
	volatile bit TIMEE1					@ ((unsigned)&EECON*8)+6;

// Register: 
volatile unsigned char           T3C0		@ 0x110;
	volatile bit FT3PWMEN					@ ((unsigned)&T3C0*8)+1;
	volatile bit FT3BUZEN					@ ((unsigned)&T3C0*8)+3;
	volatile bit FT3PWMINV					@ ((unsigned)&T3C0*8)+4;
	volatile bit FT3REN						@ ((unsigned)&T3C0*8)+7;
	
	volatile bit T3PWMEN					@ ((unsigned)&T3C0*8)+1;
	volatile bit T3BUZEN					@ ((unsigned)&T3C0*8)+3;
	volatile bit T3PWMINV					@ ((unsigned)&T3C0*8)+4;
	volatile bit T3REN						@ ((unsigned)&T3C0*8)+7;

// Register: 
volatile unsigned char           T3C1	  @ 0x111;
	volatile bit FT3CK0						@ ((unsigned)&T3C1*8)+0;
	volatile bit FT3CK1						@ ((unsigned)&T3C1*8)+1;
	volatile bit FT3CK2						@ ((unsigned)&T3C1*8)+2;
	volatile bit FT3CKS0					@ ((unsigned)&T3C1*8)+4;
	volatile bit FT3CKS1					@ ((unsigned)&T3C1*8)+6;
	volatile bit FT3OUT0					@ ((unsigned)&T3C1*8)+7;
	
	volatile bit T3CK0						@ ((unsigned)&T3C1*8)+0;
	volatile bit T3CK1						@ ((unsigned)&T3C1*8)+1;
	volatile bit T3CK2						@ ((unsigned)&T3C1*8)+2;
	volatile bit T3CKS0						@ ((unsigned)&T3C1*8)+4;
	volatile bit T3CKS1						@ ((unsigned)&T3C1*8)+6;
	volatile bit T3OUT0						@ ((unsigned)&T3C1*8)+7;

// Register: 
volatile unsigned char           T3TL	  @ 0x112;
// Register: 
volatile unsigned char           T3TH	  @ 0x113;

// Register: 
volatile unsigned char           T3PL	  @ 0x114;
// Register: 
volatile unsigned char           T3PH	  @ 0x115;

// Register: 
volatile unsigned char           T3DL	  @ 0x116;
// Register: 
volatile unsigned char           T3DH	  @ 0x117;

// Register: 
volatile unsigned char           T2C0	  @ 0x118;
	volatile bit FT2PWMEN					@ ((unsigned)&T2C0*8)+1;
	volatile bit FT2REN						@ ((unsigned)&T2C0*8)+7;
	
	volatile bit T2PWMEN					@ ((unsigned)&T2C0*8)+1;
	volatile bit T2REN						@ ((unsigned)&T2C0*8)+7;

// Register: 
volatile unsigned char           T2C1	  @ 0x119;
	volatile bit FT2CK0						@ ((unsigned)&T2C1*8)+0;
	volatile bit FT2CK1						@ ((unsigned)&T2C1*8)+1;
	volatile bit FT2CK2						@ ((unsigned)&T2C1*8)+2;
	volatile bit FT2CKS0					@ ((unsigned)&T2C1*8)+4;
	volatile bit FT2OUT0					@ ((unsigned)&T2C1*8)+6;
	volatile bit FPRSEN						@ ((unsigned)&T2C1*8)+7;
	
	volatile bit T2CK0						@ ((unsigned)&T2C1*8)+0;
	volatile bit T2CK1						@ ((unsigned)&T2C1*8)+1;
	volatile bit T2CK2						@ ((unsigned)&T2C1*8)+2;
	volatile bit T2CKS0						@ ((unsigned)&T2C1*8)+4;
	volatile bit T2OUT0						@ ((unsigned)&T2C1*8)+6;
	volatile bit PRSEN						@ ((unsigned)&T2C1*8)+7;

// Register: 
volatile unsigned char           T2TL	  @ 0x11A;
// Register: 
volatile unsigned char           T2TH	  @ 0x11B;

// Register: 
volatile unsigned char           T2PL	  @ 0x11C;
// Register: 
volatile unsigned char           T2PH	  @ 0x11D;

// Register: 
volatile unsigned char           T2DL	  @ 0x11E;
// Register: 
volatile unsigned char           T2DH	  @ 0x11F;

//------------------------------------------------------------
// BANK3 Special function register definitions
//------------------------------------------------------------
// Register: RCREG
volatile unsigned char           RCREG		@ 0x188;

// Register: 
volatile unsigned char           T4C0		@ 0x18D;
	volatile bit FT4PWMEN					@ ((unsigned)&T4C0*8)+1;
	volatile bit FT4BUZEN					@ ((unsigned)&T4C0*8)+3;
	volatile bit FT4PWMINV					@ ((unsigned)&T4C0*8)+4;
	volatile bit FT4REN						@ ((unsigned)&T4C0*8)+7;
	
	volatile bit T4PWMEN					@ ((unsigned)&T4C0*8)+1;
	volatile bit T4BUZEN					@ ((unsigned)&T4C0*8)+3;
	volatile bit T4PWMINV					@ ((unsigned)&T4C0*8)+4;
	volatile bit T4REN						@ ((unsigned)&T4C0*8)+7;

// Register: 
volatile unsigned char           T4C1	  @ 0x18E;
	volatile bit FT4CK0						@ ((unsigned)&T4C1*8)+0;
	volatile bit FT4CK1						@ ((unsigned)&T4C1*8)+1;
	volatile bit FT4CK2						@ ((unsigned)&T4C1*8)+2;
	volatile bit FT4CKS0					@ ((unsigned)&T4C1*8)+4;
	volatile bit FT4CKS1					@ ((unsigned)&T4C1*8)+5;
	volatile bit FT4OUT0					@ ((unsigned)&T4C1*8)+6;
	
	volatile bit T4CK0						@ ((unsigned)&T4C1*8)+0;
	volatile bit T4CK1						@ ((unsigned)&T4C1*8)+1;
	volatile bit T4CK2						@ ((unsigned)&T4C1*8)+2;
	volatile bit T4CKS0						@ ((unsigned)&T4C1*8)+4;
	volatile bit T4CKS1						@ ((unsigned)&T4C1*8)+5;
	volatile bit T4OUT0						@ ((unsigned)&T4C1*8)+6;

// Register: 
volatile unsigned char           T4TL	  @ 0x18F;
// Register: 
volatile unsigned char           T4TH	  @ 0x190;

// Register: 
volatile unsigned char           T4PL	  @ 0x191;
// Register: 
volatile unsigned char           T4PH	  @ 0x192;

// Register: 
volatile unsigned char           T4DL	  @ 0x193;
// Register: 
volatile unsigned char           T4DH	  @ 0x194;

// Register: 
volatile unsigned char           T5C0	  @ 0x195;
	volatile bit FT5PWMEN						@ ((unsigned)&T5C0*8)+1;
	volatile bit FT5BUZEN						@ ((unsigned)&T5C0*8)+3;
	volatile bit FT5PWMINV						@ ((unsigned)&T5C0*8)+4;
	volatile bit FT5REN							@ ((unsigned)&T5C0*8)+7;
	
	volatile bit T5PWMEN						@ ((unsigned)&T5C0*8)+1;
	volatile bit T5BUZEN						@ ((unsigned)&T5C0*8)+3;
	volatile bit T5PWMINV						@ ((unsigned)&T5C0*8)+4;
	volatile bit T5REN							@ ((unsigned)&T5C0*8)+7;

// Register: 
volatile unsigned char           T5C1	  @ 0x196;
	volatile bit FT5CK0							@ ((unsigned)&T5C1*8)+0;
	volatile bit FT5CK1							@ ((unsigned)&T5C1*8)+1;
	volatile bit FT5CK2							@ ((unsigned)&T5C1*8)+2;
	volatile bit FT5CKS0						@ ((unsigned)&T5C1*8)+4;
	volatile bit FT5CKS1						@ ((unsigned)&T5C1*8)+5;
	volatile bit FT5OUT0						@ ((unsigned)&T5C1*8)+6;
	
	volatile bit T5CK0							@ ((unsigned)&T5C1*8)+0;
	volatile bit T5CK1							@ ((unsigned)&T5C1*8)+1;
	volatile bit T5CK2							@ ((unsigned)&T5C1*8)+2;
	volatile bit T5CKS0							@ ((unsigned)&T5C1*8)+4;
	volatile bit T5CKS1							@ ((unsigned)&T5C1*8)+5;
	volatile bit T5OUT0							@ ((unsigned)&T5C1*8)+6;

// Register: 
volatile unsigned char           T5TL	  @ 0x197;
// Register: 
volatile unsigned char           T5TH	  @ 0x198;

// Register: 
volatile unsigned char           T5PL	  @ 0x199;
// Register: 
volatile unsigned char           T5PH	  @ 0x19A;

// Register: 
volatile unsigned char           T5DL	  @ 0x19B;
// Register: 
volatile unsigned char           T5DH	  @ 0x19C;

// Register: 
volatile unsigned char           CMCON0	  @ 0x19D;
	volatile bit FCMCH0						@ ((unsigned)&CMCON0*8)+0;
	volatile bit FCMCH1						@ ((unsigned)&CMCON0*8)+1;
	volatile bit FCMCH2						@ ((unsigned)&CMCON0*8)+2;
	volatile bit FCIS						@ ((unsigned)&CMCON0*8)+3;
	volatile bit FC1INV						@ ((unsigned)&CMCON0*8)+4;
	volatile bit FC2INV						@ ((unsigned)&CMCON0*8)+5;
	volatile bit FC1OUT						@ ((unsigned)&CMCON0*8)+6;
	volatile bit FC2OUT						@ ((unsigned)&CMCON0*8)+7;
	
	volatile bit CMCH0						@ ((unsigned)&CMCON0*8)+0;
	volatile bit CMCH1						@ ((unsigned)&CMCON0*8)+1;
	volatile bit CMCH2						@ ((unsigned)&CMCON0*8)+2;
	volatile bit CIS						@ ((unsigned)&CMCON0*8)+3;
	volatile bit C1INV						@ ((unsigned)&CMCON0*8)+4;
	volatile bit C2INV						@ ((unsigned)&CMCON0*8)+5;
	volatile bit C1OUT						@ ((unsigned)&CMCON0*8)+6;
	volatile bit C2OUT						@ ((unsigned)&CMCON0*8)+7;

// Register: 
volatile unsigned char           CMCON1	  @ 0x19E;
	volatile bit FC2SYNC					@ ((unsigned)&CMCON1*8)+0;
	volatile bit FT1GSS						@ ((unsigned)&CMCON1*8)+1;
	volatile bit FC1FIEN					@ ((unsigned)&CMCON1*8)+2;
	volatile bit FC2FIEN					@ ((unsigned)&CMCON1*8)+3;
	
	volatile bit C2SYNC						@ ((unsigned)&CMCON1*8)+0;
	volatile bit T1GSS						@ ((unsigned)&CMCON1*8)+1;
	volatile bit C1FIEN						@ ((unsigned)&CMCON1*8)+2;
	volatile bit C2FIEN						@ ((unsigned)&CMCON1*8)+3;

// Register: 
volatile unsigned char           VRCON	  @ 0x19F;
	volatile bit FVR0						@ ((unsigned)&VRCON*8)+0;
	volatile bit FVR1						@ ((unsigned)&VRCON*8)+1;
	volatile bit FVR2						@ ((unsigned)&VRCON*8)+2;
	volatile bit FVR3						@ ((unsigned)&VRCON*8)+3;
	volatile bit FVRR						@ ((unsigned)&VRCON*8)+5;
	volatile bit FVREN						@ ((unsigned)&VRCON*8)+7;
	
	volatile bit VR0						@ ((unsigned)&VRCON*8)+0;
	volatile bit VR1						@ ((unsigned)&VRCON*8)+1;
	volatile bit VR2						@ ((unsigned)&VRCON*8)+2;
	volatile bit VR3						@ ((unsigned)&VRCON*8)+3;
	volatile bit VRR						@ ((unsigned)&VRCON*8)+5;
	volatile bit VREN						@ ((unsigned)&VRCON*8)+7;

// Register: 
volatile unsigned char           FLCON1      @ 0x1A0;
	volatile bit FREADL						@ ((unsigned)&FLCON1*8)+0;
	volatile bit FPROGL						@ ((unsigned)&FLCON1*8)+1;
	volatile bit FERASEL					@ ((unsigned)&FLCON1*8)+2;
	volatile bit FTIMEL0					@ ((unsigned)&FLCON1*8)+5;
	volatile bit FTIMEL1					@ ((unsigned)&FLCON1*8)+6;
	volatile bit FCEFL						@ ((unsigned)&FLCON1*8)+7;
	
	volatile bit READL						@ ((unsigned)&FLCON1*8)+0;
	volatile bit PROGL						@ ((unsigned)&FLCON1*8)+1;
	volatile bit ERASEL						@ ((unsigned)&FLCON1*8)+2;
	volatile bit TIMEL0						@ ((unsigned)&FLCON1*8)+5;
	volatile bit TIMEL1						@ ((unsigned)&FLCON1*8)+6;
	volatile bit CEFL						@ ((unsigned)&FLCON1*8)+7;

// Register: 
volatile unsigned char           FLCON2         @ 0x1A1;

// Register: 
volatile unsigned char           FLADRH         @ 0x1A2;
// Register: 
volatile unsigned char           FLADRL         @ 0x1A3;

// Register: 
volatile unsigned char           FLDATH         @ 0x1A4;
// Register: 
volatile unsigned char           FLDATL         @ 0x1A5;
// Register: 

volatile unsigned char           FLEF           @ 0x1A6;
	volatile bit FOV						@ ((unsigned)&FLEF*8)+0;
	volatile bit FFOV						@ ((unsigned)&FLEF*8)+0;

//------------------------------------------------------------
// BANK-end Special function register definitions
//------------------------------------------------------------


/*******************************************************
					位定义
********************************************************/
#define	Set(x,y)	((x) |= (1 << (y)))				//位置1
#define	Clr(x,y)	((x) &= ~ (1 << (y)))			//位清0

#define	b0(x,y)		(((x) & (1 << (y))) == 0)		//位0判断 if(b0(x,y)) 判断是否为0
#define	b1(x,y)		((x) & (1 << (y)))				//位1判断 if(b1(x,y)) 判断是否为1
























/*
#ifndef _LIB_BUILD
volatile union {
    struct {
        unsigned	MULTS0              : 1;
        unsigned	MULTS1              : 1;
        unsigned	OPAMEN              : 1;
        unsigned	COMMS               : 1; 
        unsigned						: 4;
    };
} OPAMbits @ 0x0DB;
#endif
*/
//$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
//$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

/*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
变量定义 ：
bit				1	==布尔型位变量，0或1两种取值
char			8	==有符号或无符号字符变量，
unsigned char	8	==无符号字符变量
short			16	==有符号整型数
unsigned short	16	==无符号整型数
int				16	==有符号整型数
unsigned int	16	==无符号整型数
long			32	==有符号长整型
unsigned long	32	==无符号长整型
float			24	==浮点数
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
BANK数据寄存器定义的管理
如果没有特别说明，所定义的变量降被定义在Bank0;除了Bank0内的变量声明不需要特殊处理外，
定义在其它Bank内的变量前面必须加上相应的bank序号，例如
	bank1 unsigned char buffer[2]	;变量定位在bank0
	bank2 bit flag1,flag2	;变量定位在bank2(如果硬件有bank2)
	bank3 int U16_tmp0,U16_tmp1	;变量定位在bank3(如果硬件有bank3)
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
其它变量修饰关键词:
extern - 外部变量声明；如果在一个C程序文件中要使用一些变量但其原型定义写在另外的文件中，
	那么在本文件中必须将这些变量声明成“extern ”外部类型。

volatile —易变型变量声明。
const  —  常数型变量声明。
persistent —  非初始化变量声明。
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*



*/
#endif

