/*************************************************************** 
文件名:  HS23P6315.h 	
文件描述:头文件
开发者:  lcs
编写时间:2020.07.7
***************************************************************/
#ifndef _HS23P6315_H
#define _HS23P6315_H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }

//=================================================
//sfr define for HS23P6516
//=================================================
struct bitRegister{
	unsigned bit0:1;
	unsigned bit1:1;
	unsigned bit2:1;
	unsigned bit3:1;
	unsigned bit4:1;
	unsigned bit5:1;
	unsigned bit6:1;
	unsigned bit7:1;
};
//=================================================
typedef unsigned char BYTE;
typedef unsigned long WORD;
typedef double DWORD;
//=================================================
//寄存器宏定义 
//=================================================
//0X80~0X8F
sfr		L 		= 	0x80;
sfr		H		= 	0x81;
sfr		R		= 	0x82;
sfr		Z 		= 	0x83;

sfr		Y 		= 	0x84;
sfr		X 		= 	0x85;
sfr		PFLAG 	= 	0x86;
	sbit	FZ		=	0x86:0;
	sbit	FDC		=	0x86:1;
	sbit	FC		=	0x86:2;
	
	//sbit	FLVD24	=	0x86:4;
	//sbit	FLVD36	=	0x86:5;
	sbit	FNPD	=	0x86:6;
	sbit	FNT0	=	0x86:7;
	
sfr		RBANK 	= 	0x87;
	sbit	FRBANKS0=	0x87:0;

sfr		W0 	= 	0x88;
sfr		W1 	= 	0x89;
sfr		W2 	= 	0x8A;
sfr		W3 	= 	0x8B;
sfr		W4 	= 	0x8C;
sfr		W5 	= 	0x8D;
sfr		W6 	= 	0x8E;
sfr		W7 	= 	0x8F;

//=================================================
//0X90~0X9F
sfr		_HL		= 	0x090;
//sfr		@HL		= 	0x090;
sfr		_YZ		= 	0x091;
//sfr		@YZ		= 	0x091;
sfr		REG_92H	= 	0x092;
sfr		PCL		= 	0x093;

sfr		PCH		= 	0x094;
sfr		OSCM	= 	0x095;
	sbit	FSTPHX 		=	0x95:1;
	sbit	FCLKMD		=	0x95:2;	
	sbit	FCPUM0		=	0x95:3;
	sbit	FCPUM1 		=	0x95:4;
	sbit	FXT_sel		=	0x95:5;	
	
sfr		WDTR	= 	0x096;
sfr		INTRQ0	= 	0x097;
	sbit	FINT0IF	 	=	0x97:0;
	sbit	FINT1IF 	=	0x97:1;
	sbit	FINT2IF		=	0x97:2;	
	sbit	FADCIF		=	0x97:3;
	sbit	FT1IF 		=	0x97:4;
	sbit	FTC0IF		=	0x97:5;	
	sbit	FT2IF		=	0x97:6;

sfr		REG_98H	= 	0x098;
sfr		INTEN0	= 	0x099;
	sbit	FINT0IE	 	=	0x99:0;
	sbit	FINT1IE 	=	0x99:1;
	sbit	FINT2IE		=	0x99:2;	
	sbit	FADCIE		=	0x99:3;
	sbit	FT1IE 		=	0x99:4;
	sbit	FTC0IE		=	0x99:5;	
	sbit	FT2IE		=	0x99:6;
	
sfr		REG_9AH	= 	0x09A;
sfr		P0W		= 	0x09B;
	sbit	FP0W0	 	=	0x09B:0;
	sbit	FP0W1	 	=	0x09B:1;
	sbit	FP0W2		=	0x09B:2;	
	sbit	FP0W3		=	0x09B:3;
	
	sbit	FP0W4 		=	0x09B:4;
	sbit	FP0W5		=	0x09B:5;	
	sbit	FP0W7		=	0x09B:7;

sfr		P1W		= 	0x09C;
	sbit	FP1W0	 	=	0x09C:0;
	sbit	FP1W1	 	=	0x09C:1;
	sbit	FP1W2		=	0x09C:2;	
	sbit	FP1W3		=	0x09C:3;
	
	sbit	FP1W4 		=	0x09C:4;
	sbit	FP1W5		=	0x09C:5;	
	sbit	FP1W6		=	0x09C:6;	
	sbit	FP1W7		=	0x09C:7;
	
sfr		P2W		= 	0x09D;
	sbit	FP2W0	 	=	0x09D:0;
	sbit	FP2W1	 	=	0x09D:1;
	sbit	FP2W2		=	0x09D:2;	
	sbit	FP2W3		=	0x09D:3;
	
	sbit	FP2W4 		=	0x09D:4;
	sbit	FP2W5		=	0x09D:5;	
	sbit	FP2W6		=	0x09D:6;	
	sbit	FP2W7		=	0x09D:7;
	
sfr		P4W		= 	0x09E;
	sbit	FP4W0	 	=	0x09E:0;
	sbit	FP4W1	 	=	0x09E:1;
	sbit	FP4W2		=	0x09E:2;	
	sbit	FP4W3		=	0x09E:3;
	sbit	FP4W4 		=	0x09E:4;
	
sfr		PEDGE	= 	0x09F;
	sbit	FP15G0	 	=	0x9F:0;
	sbit	FP15G1	 	=	0x9F:1;
//=================================================
//0XA0~0XAF
sfr		P0M		= 	0x0A0;
	sbit	FP0M0	 	=	0x0A0:0;
	sbit	FP0M1	 	=	0x0A0:1;
	sbit	FP0M2		=	0x0A0:2;	
	sbit	FP0M3		=	0x0A0:3;
	
	sbit	FP0M4 		=	0x0A0:4;
	sbit	FP0M5		=	0x0A0:5;	
	sbit	FP0M7		=	0x0A0:7;
	
sfr		P1M		= 	0x0A1;
	sbit	FP1M0	 	=	0x0A1:0;
	sbit	FP1M1	 	=	0x0A1:1;
	sbit	FP1M2		=	0x0A1:2;	
	sbit	FP1M3		=	0x0A1:3;
	
	sbit	FP1M4 		=	0x0A1:4;
	sbit	FP1M5		=	0x0A1:5;	
	sbit	FP1M6		=	0x0A1:6;	
	sbit	FP1M7		=	0x0A1:7;
	
sfr		P2M		= 	0x0A2;
	sbit	FP2M0	 	=	0x0A2:0;
	sbit	FP2M1	 	=	0x0A2:1;
	sbit	FP2M2		=	0x0A2:2;	
	sbit	FP2M3		=	0x0A2:3;
	
	sbit	FP2M4 		=	0x0A2:4;
	sbit	FP2M5		=	0x0A2:5;	
	sbit	FP2M6		=	0x0A2:6;	
	sbit	FP2M7		=	0x0A2:7;
	
sfr		P4M		= 	0x0A3;
	sbit	FP4M0	 	=	0x0A3:0;
	sbit	FP4M1	 	=	0x0A3:1;
	sbit	FP4M2		=	0x0A3:2;	
	sbit	FP4M3		=	0x0A3:3;
	sbit	FP4M4 		=	0x0A3:4;

sfr		REG_A4H	= 	0x0A4;
sfr		P0		= 	0x0A5;
	sbit	FP00	 	=	0x0A5:0;
	sbit	FP01	 	=	0x0A5:1;
	sbit	FP02		=	0x0A5:2;	
	sbit	FP03		=	0x0A5:3;
	
	sbit	FP04 		=	0x0A5:4;
	sbit	FP05		=	0x0A5:5;	
	sbit	FP07		=	0x0A5:7;
	
sfr		P1		= 	0x0A6;
	sbit	FP10	 	=	0x0A6:0;
	sbit	FP11	 	=	0x0A6:1;
	sbit	FP12		=	0x0A6:2;	
	sbit	FP13		=	0x0A6:3;
	
	sbit	FP14 		=	0x0A6:4;
	sbit	FP15		=	0x0A6:5;	
	sbit	FP16		=	0x0A6:6;	
	sbit	FP17		=	0x0A6:7;
	
sfr		P2		= 	0x0A7;
	sbit	FP20	 	=	0x0A7:0;
	sbit	FP21	 	=	0x0A7:1;
	sbit	FP22		=	0x0A7:2;	
	sbit	FP23		=	0x0A7:3;
	
	sbit	FP24 		=	0x0A7:4;
	sbit	FP25		=	0x0A7:5;	
	sbit	FP26		=	0x0A7:6;	
	sbit	FP27		=	0x0A7:7;

sfr		P4		= 	0x0A8;
	sbit	FP40	 	=	0x0A8:0;
	sbit	FP41	 	=	0x0A8:1;
	sbit	FP42		=	0x0A8:2;	
	sbit	FP43		=	0x0A8:3;
	sbit	FP44 		=	0x0A8:4;
	
sfr		REG_A9H	= 	0x0A9;
sfr		P0UR	= 	0x0AA;
	sbit	FP0UR0	 	=	0x0AA:0;
	sbit	FP0UR1	 	=	0x0AA:1;
	sbit	FP0UR2		=	0x0AA:2;	
	sbit	FP0UR3		=	0x0AA:3;
	
	sbit	FP0UR4 		=	0x0AA:4;
	sbit	FP0UR5		=	0x0AA:5;	
	sbit	FP0UR7		=	0x0AA:7;
	
sfr		P1UR	= 	0x0AB;
	sbit	FP1UR0	 	=	0x0AB:0;
	sbit	FP1UR1	 	=	0x0AB:1;
	sbit	FP1UR2		=	0x0AB:2;	
	sbit	FP1UR3		=	0x0AB:3;
	
	sbit	FP1UR4 		=	0x0AB:4;
	sbit	FP1UR5		=	0x0AB:5;	
	sbit	FP1UR6		=	0x0AB:6;	
	sbit	FP1UR7		=	0x0AB:7;

sfr		P2UR	= 	0x0AC;
	sbit	FP2UR0	 	=	0x0AC:0;
	sbit	FP2UR1	 	=	0x0AC:1;
	sbit	FP2UR2		=	0x0AC:2;	
	sbit	FP2UR3		=	0x0AC:3;
	
	sbit	FP2UR4 		=	0x0AC:4;
	sbit	FP2UR5		=	0x0AC:5;	
	sbit	FP2UR6		=	0x0AC:6;	
	sbit	FP2UR7		=	0x0AC:7;
	
sfr		P4UR	= 	0x0AD;
	sbit	FP4UR0	 	=	0x0AD:0;
	sbit	FP4UR1	 	=	0x0AD:1;
	sbit	FP4UR2		=	0x0AD:2;	
	sbit	FP4UR3		=	0x0AD:3;
	
	sbit	FP4UR4 		=	0x0AD:4;
	sbit	FP4UR5		=	0x0AD:5;	
	sbit	FP4UR6		=	0x0AD:6;	
	sbit	FP4UR7		=	0x0AD:7;
	
sfr		REG_AEH	= 	0x0AE;
sfr		REMcon	= 	0x0AF;
sfr		REMCON	= 	0x0AF;
	sbit	FRem_sel_0	=	0x0AF:0;
	sbit	FRem_sel_1	=	0x0AF:1;
	sbit	FRem_sel_2	=	0x0AF:2;	
	sbit	FRem_sel_3	=	0x0AF:3;
	
	sbit	FRem_sel_4	=	0x0AF:4;
	sbit	FELE_en		=	0x0AF:5;
	sbit	FD_sel		=	0x0AF:6;
	sbit	FIE_sel		=	0x0AF:7;

//=================================================
//0XB0~0XBF
sfr		LCD_CT0		= 	0xB0;
	sbit	FSCANSEL	=	0xB0:0;
	//sbit	FRSEL		=	0xB0:1;
	sbit	FLCDPR		=	0xB0:2;
	sbit	FBIASEN		=	0xB0:3;
	
	sbit	FDUTY0		=	0xB0:4;
	sbit	FDUTY1		=	0xB0:5;
	sbit	FPUMPEN		=	0xB0:6;	
	sbit	FLCDEN		=	0xB0:7;
	
sfr		LCD_DB		= 	0xB1;
	sbit	FLCD_B0		=	0xB1:0;
	sbit	FLCD_B1		=	0xB1:1;
	sbit	FLCD_B2		=	0xB1:2;
	sbit	FLCD_B3		=	0xB1:3;
	sbit	FLCD_B4		=	0xB1:4;
	sbit	FLCD_B5		=	0xB1:5;
	sbit	FLCD_B6		=	0xB1:6;	
	sbit	FLCD_B7		=	0xB1:7;
	
sfr		LCD_ADDR	= 	0xB2;
	sbit	FLCD_A0		=	0xB2:0;
	sbit	FLCD_A1		=	0xB2:1;
	sbit	FLCD_A2		=	0xB2:2;
	sbit	FLCD_A3		=	0xB2:3;
	sbit	FLCD_A4		=	0xB2:4;
	
sfr		LCD_CT1		= 	0xB3;//?
	
sfr		LCD_CT2		= 	0xB4;
	sbit	FCOMSX0	=	0xB4:0;
	sbit	FCOMSX1	=	0xB4:1;
	//sbit	FCKP	=	0xB4:2;	
	//sbit	FTXAK	=	0xB4:3;	
	sbit	FCOMS4	=	0xB4:4;
	sbit	FCOMS5	=	0xB4:5;
	sbit	FCOMS6	=	0xB4:6;
	sbit	FCOMS7	=	0xB4:7;
	
sfr		T1M0	= 	0xB5;
	sbit	FTC0GN		=	0xB5:0;
	//sbit		=	0xB5:1;
	sbit	FT1CK		=	0xB5:2;	
	sbit	FTP1SEL		=	0xB5:3;
	
	sbit	FTP1S0		=	0xB5:4;
	sbit	FTP1S1		=	0xB5:5;
	sbit	FTP1S2		=	0xB5:6;
	sbit	FTR1		=	0xB5:7;
	
sfr		T1C_L	= 	0xB6;
sfr		T1C_H	= 	0xB7;

sfr		TC0M	= 	0xB8;
	sbit	FPWM0OUT	=	0xB8:0;
	//sbit		=	0xB8:1;
	sbit	FTC0I0		=	0xB8:2;	
	sbit	FTC0I1		=	0xB8:3;
	
	sbit	FTC0S0		=	0xB8:4;
	sbit	FTC0S1		=	0xB8:5;
	sbit	FTC0S2		=	0xB8:6;
	sbit	FTC0TR		=	0xB8:7;
	
sfr		TC0C	= 	0xB9;
sfr		TC0R	= 	0xBA;
sfr		TC0D	= 	0xBB;

sfr		TC0M1	= 	0xBC;
	sbit	FPWM1OUT	=	0xBC:0;
	sbit	FPWM2OUT	=	0xBC:1;
	sbit	FTC0M12		=	0xBC:2;	
	sbit	FTC0M13		=	0xBC:3;
	
sfr		TC0D1	= 	0xBD;
sfr		TC0D2	= 	0xBE;
sfr		REG_BFH	= 	0xBF;

//=================================================
//0XC0~0XCF
sfr		P0SS	= 	0xC0;
sfr		P1SS	= 	0xC1;
sfr		P2SS	= 	0xC2;
sfr		P4SS	= 	0xC3;

sfr		REG_C4H	= 	0xC4;
sfr		REG_C5	= 	0xC5;
sfr		PCTRL	= 	0xC6;
sfr		Pctrl	= 	0xC6;
	sbit	FLOSCEN		=	0xC6:7;
	
sfr		ADPCON	= 	0xC7;
	sbit	FADPCON0		=	0xC7:0;
	sbit	FADPCON1		=	0xC7:1;
	sbit	FADPCON2		=	0xC7:2;	
	sbit	FADPCON3		=	0xC7:3;	
	sbit	FADPCON4		=	0xC7:4;
	//sbit					=	0xC7:5;
	sbit	FADPCON6		=	0xC7:6;
	sbit	FADPCON7		=	0xC7:7;

sfr		ADM		= 	0xC8;
	sbit	FCHS0		=	0xC8:0;
	sbit	FCHS1		=	0xC8:1;
	sbit	FCHS2		=	0xC8:2;	
	//sbit				=	0xC8:3;	
	sbit	FGCHS		=	0xC8:4;
	sbit	FEOC		=	0xC8:5;
	sbit	FADS		=	0xC8:6;
	sbit	FADENB		=	0xC8:7;
	
sfr		ADB		= 	0xC9;
sfr		ADR		= 	0xCA;
	sbit	FADB0		=	0xCA:0;
	sbit	FADB1		=	0xCA:1;
	sbit	FADB2		=	0xCA:2;	
	sbit	FADB3		=	0xCA:3;	
	sbit	FADCKS0		=	0xCA:4;
	//sbit			=	0xCA:5;
	sbit	FADCKS1		=	0xCA:6;
	//sbit			=	0xCA:7;
	
sfr		ADT		= 	0xCB;

sfr		WDTcon	= 	0xCC;
sfr		WDTCON	= 	0xCC;
	sbit	FLCD_T0		=	0xCC:0;
	sbit	FLCD_T1		=	0xCC:1;
	sbit	FLCD_T2		=	0xCC:2;	
	sbit	FLCD_T3		=	0xCC:3;
	
	sbit	FWDT_pre0	=	0xCC:4;
	sbit	FWDT_pre1	=	0xCC:5;
	sbit	FWDT_pre2	=	0xCC:6;
	sbit	FWDT_EN		=	0xCC:7;
	
sfr		REG_CDH	= 	0xCD;
sfr		VREF	= 	0xCE;
sfr		VREFH	= 	0xCE;
sfr		LVDcon	= 	0xCF;
sfr		LVDCON	= 	0xCF;
	sbit	FLVD18		=	0xCF:0;
	sbit	FLVD2X		=	0xCF:1;
	//sbit			=	0xCF:2;	
	sbit	FLVDS_0		=	0xCF:3;
	
	sbit	FLVDS_1		=	0xCF:4;
	sbit	FREM_sel_5	=	0xCF:5;
	sbit	FREM_sel_6	=	0xCF:6;
	sbit	FREM_sel_7	=	0xCF:7;

//=================================================
//0XD0~0XDF
sfr		P0SD		= 	0xD0;
	sbit	FP0SD0	 	=	0xD0:0;
	sbit	FP0SD1	 	=	0xD0:1;
	sbit	FP0SD2		=	0xD0:2;	
	sbit	FP0SD3		=	0xD0:3;
	
	sbit	FP0SD4 		=	0xD0:4;
	sbit	FP0SD5		=	0xD0:5;	
	sbit	FP0SD7		=	0xD0:7;
	
sfr		P1SD		= 	0xD1;
	sbit	FP1SD0	 	=	0xD1:0;
	sbit	FP1SD1	 	=	0xD1:1;
	sbit	FP1SD2		=	0xD1:2;	
	sbit	FP1SD3		=	0xD1:3;
	
	sbit	FP1SD4 		=	0xD1:4;
	sbit	FP1SD5		=	0xD1:5;	
	sbit	FP1SD6		=	0xD1:6;	
	sbit	FP1SD7		=	0xD1:7;
	
sfr		P2SD		= 	0xD2;
	sbit	FP2SD0	 	=	0xD2:0;
	sbit	FP2SD1	 	=	0xD2:1;
	sbit	FP2SD2		=	0xD2:2;	
	sbit	FP2SD3		=	0xD2:3;
	
	sbit	FP2SD4 		=	0xD2:4;
	sbit	FP2SD5		=	0xD2:5;	
	sbit	FP2SD6		=	0xD2:6;	
	sbit	FP2SD7		=	0xD2:7;
	
sfr		P4SD		= 	0xD3;
	sbit	FP4SD0	 	=	0xD3:0;
	sbit	FP4SD1	 	=	0xD3:1;
	sbit	FP4SD2		=	0xD3:2;	
	sbit	FP4SD3		=	0xD3:3;
	
	sbit	FP4SD4 		=	0xD3:4;
	sbit	FP4SD5		=	0xD3:5;	
	sbit	FP4SD6		=	0xD3:6;	
	sbit	FP4SD7		=	0xD3:7;

sfr		REG_D4H		= 	0xD4;
sfr		REG_D5H		= 	0xD5;
sfr		REG_D6H		= 	0xD6;
sfr		REG_D7H		= 	0xD7;

sfr		REG_D8H		= 	0xD8;
sfr		REG_D9H		= 	0xD9;
sfr		REG_DAH		= 	0xDA;
sfr		REG_DBH		= 	0xDB;

sfr		REG_DCH		= 	0xDC;
sfr		REG_DDH		= 	0xDD;
sfr		AD_fu0		= 	0xDE;
sfr		AD_fu1		= 	0xDF;

//=================================================
//0XE0~0XEF
sfr		P0SU		= 	0xE0;
	sbit	FP0SU0	 	=	0xE0:0;
	sbit	FP0SU1	 	=	0xE0:1;
	sbit	FP0SU2		=	0xE0:2;	
	sbit	FP0SU3		=	0xE0:3;
	
	sbit	FP0SU4 		=	0xE0:4;
	sbit	FP0SU5		=	0xE0:5;	
	sbit	FP0SU7		=	0xE0:7;
	
sfr		P1SU		= 	0xE1;
	sbit	FP1SU0	 	=	0xE1:0;
	sbit	FP1SU1	 	=	0xE1:1;
	sbit	FP1SU2		=	0xE1:2;	
	sbit	FP1SU3		=	0xE1:3;
	
	sbit	FP1SU4 		=	0xE1:4;
	sbit	FP1SU5		=	0xE1:5;	
	sbit	FP1SU6		=	0xE1:6;	
	sbit	FP1SU7		=	0xE1:7;
	
sfr		P2SU		= 	0xE2;
	sbit	FP2SU0	 	=	0xE2:0;
	sbit	FP2SU1	 	=	0xE2:1;
	sbit	FP2SU2		=	0xE2:2;	
	sbit	FP2SU3		=	0xE2:3;
	
	sbit	FP2SU4 		=	0xE2:4;
	sbit	FP2SU5		=	0xE2:5;	
	sbit	FP2SU6		=	0xE2:6;	
	sbit	FP2SU7		=	0xE2:7;
	
sfr		P4SU		= 	0xE3;
	sbit	FP4SU0	 	=	0xE3:0;
	sbit	FP4SU1	 	=	0xE3:1;
	sbit	FP4SU2		=	0xE3:2;	
	sbit	FP4SU3		=	0xE3:3;
	
	sbit	FP4SU4 		=	0xE3:4;
	sbit	FP4SU5		=	0xE3:5;	
	sbit	FP4SU6		=	0xE3:6;	
	sbit	FP4SU7		=	0xE3:7;

sfr		REG_E4H		= 	0xE4;
sfr		REG_E5H		= 	0xE5;
sfr		REG_E6H		= 	0xE6;
sfr		REG_E7H		= 	0xE7;

sfr		REG_E8H		= 	0xE8;
sfr		T1M1		= 	0xE9;
	sbit	FT1_OVW		=	0xE9:0;
	sbit	FT1_OVS		=	0xE9:1;
	sbit	FINT1_W		=	0xE9:2;	
	sbit	FPWM2_W1		=	0xE9:3;	
	sbit	FPWM2_W2		=	0xE9:4;
	
sfr		T2M			= 	0xEA;
	sbit	FTP2S0		=	0xEA:3;
	sbit	FTP2S1		=	0xEA:4;
	sbit	FTP2S2		=	0xEA:5;	
	sbit	FT2_W		=	0xEA:6;	
	sbit	FTR2		=	0xEA:7;
	
sfr		T2CL		= 	0xEB;
sfr		T2CH		= 	0xEC;
sfr		REG_EDH		= 	0xED;
sfr		REG_EEH		= 	0xEE;

sfr		STKP		= 	0xEF;
	sbit	FSTKPB0		=	0xEF:0;
	sbit	FSTKPB1		=	0xEF:1;
	sbit	FSTKPB2		=	0xEF:2;	

	sbit	FGIE		=	0xEF:7;	
//=================================================
//0XF0~0XFF
sfr		STK7L	= 	0xF0;
sfr		STK7H	= 	0xF1;
sfr		STK6L	= 	0xF2;
sfr		STK6H	= 	0xF3;

sfr		STK5L	= 	0xF4;
sfr		STK5H	= 	0xF5;
sfr		STK4L	= 	0xF6;
sfr		STK4H	= 	0xF7;

sfr		STK3L	= 	0xF8;
sfr		STK3H	= 	0xF9;
sfr		STK2L	= 	0xFA;
sfr		STK2H	= 	0xFB;

sfr		STK1L	= 	0xFC;
sfr		STK1H	= 	0xFD;
sfr		STK0L	= 	0xFE;
sfr		STK0H	= 	0xFF;
//=================================================
#define	SLEEPMODE	__asm{SleepMode}
#define	GREENMODE	__asm{GreenMode}
#define	SLOWMODE	__asm{SlowMode}
#define	SLOW2NORMAL	__asm{Slow2Normal}
//=================================================
//取数据高低位
#define HIBYTE(wval)		*(((BYTE*)(&wval))+1)
#define LWBYTE(wval)		*(((BYTE*)(&wval))+0)

#define HIWORD(wval)		*(((WORD*)(&wval))+1)
#define LWWORD(wval)		*(((WORD*)(&wval))+0)

#endif
