<?xml version="1.0" encoding="UTF-8"?>
<chip>
	<configure-file-ver>1.0</configure-file-ver>
	<chip-name>HS26F2728S</chip-name>
	<chip-classes>FLASH</chip-classes>
	<chip-id>9E</chip-id>
	<chip-id-debug>FF19</chip-id-debug>
	<chip-ver>0</chip-ver>
	<ccs-file-ver>4</ccs-file-ver>
	<ram-start-addr>0</ram-start-addr>
	<ram-size>256</ram-size>
	<otp-body-size>8192</otp-body-size>
	<user-rom-size>7936</user-rom-size>
	<reset-addr>0</reset-addr>
	<stack-level>8</stack-level>
	<config-word-count>6</config-word-count>	
	<max-breakpoint>8</max-breakpoint>	
	<asm-inc>$(DevEnvDir)\asm_inc\$(ChipName).inc</asm-inc>
	<clang-inc>$(DevEnvDir)\include\$(ChipName).h</clang-inc>			
	<description></description>
	<rams>
		<ram start-addr="0" length="768">
			<ram-segment start-addr="00" size="128" write-addr="00" read-addr="00" value-addr="00" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="80" size="128" write-addr="80" read-addr="80" value-addr="80" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="180" size="128" write-addr="880" read-addr="880" value-addr="880" visiable="false" bank="1"></ram-segment>	
			<ram-segment start-addr="280" size="128" write-addr="1080" read-addr="1080" value-addr="1080" visiable="false" bank="2"></ram-segment>		
			<ram-segment start-addr="100" size="256" write-addr="100" read-addr="100" value-addr="100" visiable="true" bank="1"></ram-segment>		
			<ram-segment start-addr="ff0" size="3" write-addr="ff0" read-addr="ff0" value-addr="ff0" visiable="false" bank="0"></ram-segment>	
		</ram>	
	</rams>
	<configs>
		<config-word index="0" or-value="0000" and-value="ffff" mapto="0"></config-word>
		<config-word index="1" or-value="0000" and-value="ffff" mapto="1"></config-word>		
		<config-word index="2" or-value="0000" and-value="ffff" mapto="3"></config-word>			
		<config-word index="3" or-value="0000" and-value="ffff" mapto="2"></config-word>			
		<config-word index="4" or-value="0000" and-value="ffff" mapto="4"></config-word>		
		<config-word index="5" or-value="0000" and-value="ffff" mapto="5"></config-word>		
		<config-word index="6" or-value="0000" and-value="ffff" mapto="6"></config-word>	
		<config-word index="7" or-value="0000" and-value="ffff" mapto="7"></config-word>

		
		<config-item name="LVD_SEL" width="3" offset="12" default-value="0" enable="true" config-index="0">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="2.0V" value="1"></config-item-value>
			<config-item-value name="2.2V" value="2"></config-item-value>
			<config-item-value name="2.4V" value="3"></config-item-value>
			<config-item-value name="2.6V" value="4"></config-item-value>
			<config-item-value name="3.0V" value="5"></config-item-value>
			<config-item-value name="3.6V" value="6"></config-item-value>
			<config-item-value name="3.6V" value="7"></config-item-value>
			<description></description>
		</config-item>
		<config-item name="Fcpu" width="3" offset="9" default-value="0" enable="true" config-index="0">
			<config-item-value name="Fcpu=Fosc/2" value="0"></config-item-value>
			<config-item-value name="Fcpu=Fosc/4" value="1"></config-item-value>
			<config-item-value name="Fcpu=Fosc/8" value="2"></config-item-value>
			<config-item-value name="Fcpu=Fosc/16" value="3"></config-item-value>
			<config-item-value name="Fcpu=Fosc/32" value="4"></config-item-value>
			<description>选择指令周期</description>
		</config-item>	
		<config-item name="RST_SEL" width="1" offset="8" default-value="0" enable="true" config-index="0">
			<config-item-value name="IO" value="0"></config-item-value>
			<config-item-value name="RST_PIN" value="1"></config-item-value>
			<description>P0.4是否作为复位脚</description>
		</config-item>
		<config-item name="WDTEN" width="1" offset="7" default-value="1" enable="true" config-index="0">
			<config-item-value name="Enable" value="0"></config-item-value>
			<config-item-value name="Disable" value="1"></config-item-value>
			<description>看门狗设置</description>
		</config-item>
		<config-item name="RST_TIME" width="2" offset="5" default-value="0" enable="true" config-index="0">
			<config-item-value name="32ms" value="0"></config-item-value>
			<config-item-value name="64ms" value="1"></config-item-value>
			<config-item-value name="128ms" value="2"></config-item-value>
			<config-item-value name="16ms" value="3"></config-item-value>
			<description>上电复位时间选择</description>
		</config-item>		
		<config-item name="OSC" width="3" offset="2" default-value="1" enable="true" config-index="0">
			<config-item-value name="IRC" value="0"></config-item-value>
			<config-item-value name="LP" value="1"></config-item-value>
			<config-item-value name="HS" value="2"></config-item-value>
			<config-item-value name="XT" value="3"></config-item-value>
			<config-item-value name="IRC_RTC" value="4"></config-item-value>				
			<description>时钟源选择</description>
		</config-item>				
		<config-item name="ENVDDL" width="1" offset="1" default-value="0" enable="false" config-index="0">
			<config-item-value name="Disable,不自动锁存数据" value="0"></config-item-value>
			<config-item-value name="Enable,自动锁存数据" value="1"></config-item-value>
			<description>自动锁存数据</description>
		</config-item>	
		<config-item name="NoiseF" width="1" offset="0" default-value="1" enable="true" config-index="0">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>噪声抑制</description>
		</config-item>					
		<config-item name="TouchEnable" width="1" offset="7" default-value="0" enable="true" config-index="1">
			<config-item-value name="Enable" value="0"></config-item-value>
			<config-item-value name="Disable" value="1"></config-item-value>
			<description>
			两个触摸模块TK和TK1的总使能位
			</description>
		</config-item>				
		<config-item name="OTP_ReadCycle" width="3" offset="2" default-value="0" enable="true" config-index="1">
			<config-item-value name="全指令周期" value="0"></config-item-value>
			<config-item-value name="半指令周期" value="4"></config-item-value>
			<config-item-value name="1/4指令周期" value="6"></config-item-value>
			<config-item-value name="power low" value="5"></config-item-value>
			<description>

			</description>
		</config-item>	
		<config-item name="Protect" width="1" offset="1" default-value="0" enable="true" config-index="1">
			<config-item-value name="Enable" value="1"></config-item-value>			
			<config-item-value name="Disable" value="0"></config-item-value>
			<description>

			</description>
		</config-item>		
		<config-item name="BorFilter" width="1" offset="0" default-value="0" enable="true" config-index="1">
			<config-item-value name="Enable" value="0"></config-item-value>
			<config-item-value name="Disable" value="1"></config-item-value>
			<description>

			</description>
		</config-item>				
		<config-item name="FIRC" width="2" offset="4" default-value="0" enable="true" config-index="7">
			<config-item-value name="12M" value="0"></config-item-value>
			<config-item-value name="14M" value="1"></config-item-value>
			<config-item-value name="16M" value="2"></config-item-value>
			<description>
			</description>
		</config-item>
		<config-item name="LOAD程序区选择位" width="3" offset="11" default-value="0" enable="true" config-index="5">
			<config-item-value name="默认8K" value="0"></config-item-value>
			<config-item-value name="最后1K" value="2"></config-item-value>
			<config-item-value name="最后2K" value="4"></config-item-value>
			<config-item-value name="最后4K" value="6"></config-item-value>
			<config-item-value name="最后0.5K" value="7"></config-item-value>
			<description>
			</description>
		</config-item>	
		<config-item name="DebugEnable" width="2" offset="8" default-value="0" enable="false" config-index="5">
			<config-item-value name="Enable" value="0"></config-item-value>
			<config-item-value name="Disable" value="1"></config-item-value>
			<description>
			</description>
		</config-item>				
	</configs>
	
	
	<sfrs>
		<sfr>
			<reg name="A" addr="ff0" read-addr="ff0" write-addr="ff0" value-addr="ff0" addr-visiable="false" bank="-1"></reg>

			<reg name="L" addr="80" read-addr="80" write-addr="80" value-addr="80" addr-visiable="false" bank="0"></reg>
			<reg name="H" addr="81" read-addr="81" write-addr="81" value-addr="81" addr-visiable="false" bank="0"></reg>
			<reg name="R" addr="82" read-addr="82" write-addr="82" value-addr="82" addr-visiable="false" bank="0"></reg>
			<reg name="Z" addr="83" read-addr="83" write-addr="83" value-addr="83" addr-visiable="false" bank="0"></reg>
			<reg name="Y" addr="84" read-addr="84" write-addr="84" value-addr="84" addr-visiable="false" bank="0"></reg>
			<reg name="X" addr="85" read-addr="85" write-addr="85" value-addr="85" addr-visiable="false" bank="0"></reg>
		
			<reg name="PFLAG" addr="86"  read-addr="86" write-addr="86" value-addr="86" addr-visiable="false" bank="0">
				<bit name="Z" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="C" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="PD" offset="6"></bit>
				<bit name="TO" offset="7"></bit>
			</reg>

			<reg name="W0" addr="88" read-addr="88" write-addr="88" value-addr="88" addr-visiable="true" bank="0"></reg>
			<reg name="W1" addr="89" read-addr="89" write-addr="89" value-addr="89" addr-visiable="true" bank="0"></reg>
			<reg name="W2" addr="8a" read-addr="8a" write-addr="8a" value-addr="8a" addr-visiable="true" bank="0"></reg>
			<reg name="W3" addr="8b" read-addr="8b" write-addr="8b" value-addr="8b" addr-visiable="true" bank="0"></reg>
			<reg name="W4" addr="8c" read-addr="8c" write-addr="8c" value-addr="8c" addr-visiable="true" bank="0"></reg>
			<reg name="W5" addr="8d" read-addr="8d" write-addr="8d" value-addr="8d" addr-visiable="true" bank="0"></reg>
			<reg name="W6" addr="8e" read-addr="8e" write-addr="8e" value-addr="8e" addr-visiable="true" bank="0"></reg>
			<reg name="W7" addr="8f" read-addr="8f" write-addr="8f" value-addr="8f" addr-visiable="true" bank="0"></reg>

			<reg name="@HL" addr="90" read-addr="90" write-addr="90" value-addr="90" addr-visiable="true" bank="0"></reg>
			<reg name="@YZ" addr="91" read-addr="91" write-addr="91" value-addr="91" addr-visiable="true" bank="0"></reg>
			<reg name="PCL" addr="93" read-addr="93" write-addr="93" value-addr="93" addr-visiable="true" bank="0"></reg>
			<reg name="PCH" addr="94" read-addr="94" write-addr="94" value-addr="94" addr-visiable="true" bank="0"></reg>

			<reg name="OSCM" addr="95" read-addr="95" write-addr="95" value-addr="95" addr-visiable="true" bank="0">
				<bit name="8M32KSEL" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="CLKMD" offset="2"></bit>
				<bit name="CPUM0" offset="3"></bit>
				<bit name="CPUM1" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="LRCSXT" offset="6"></bit>
				<bit name="LRCS32K" offset="7"></bit>
			</reg>

			<reg name="WDTR" addr="96" read-addr="96" write-addr="96" value-addr="96" addr-visiable="true" bank="0"></reg>

			<reg name="INTRQ0" addr="97" read-addr="97" write-addr="97" value-addr="97" addr-visiable="true" bank="0">
				<bit name="INT0IF" offset="0"></bit>
				<bit name="INT1IF" offset="1"></bit>
				<bit name="INT2IF" offset="2"></bit>
				<bit name="ADCIF" offset="3"></bit>
				<bit name="T0IF" offset="4"></bit>
				<bit name="TC0IF" offset="5"></bit>
				<bit name="T2IF" offset="6"></bit>
				<bit name="PBIF" offset="7"></bit>
			</reg>

			<reg name="INTRQ1" addr="98" read-addr="98" write-addr="98" value-addr="98" addr-visiable="true" bank="0">
				<bit name="TM1IF" offset="0"></bit>
				<bit name="TM2IF" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="TM3IF" offset="3"></bit>
				<bit name="CMPIF" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="I2CIF" offset="6"></bit>
				<bit name="SPIIF" offset="7"></bit>
			</reg>

			<reg name="INTEN0" addr="99" read-addr="99" write-addr="99" value-addr="99" addr-visiable="true" bank="0">
				<bit name="INT0IE" offset="0"></bit>
				<bit name="INT1IE" offset="1"></bit>
				<bit name="INT2IE" offset="2"></bit>
				<bit name="ADCIE" offset="3"></bit>
				<bit name="T0IE" offset="4"></bit>
				<bit name="TC0IE" offset="5"></bit>
				<bit name="T2IE" offset="6"></bit>
				<bit name="PBIE" offset="7"></bit>
			</reg>

			<reg name="INTEN1" addr="9A" read-addr="9A" write-addr="9A" value-addr="9A" addr-visiable="true" bank="0">
				<bit name="TM1IE" offset="0"></bit>
				<bit name="TM2IE" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="TM3IE" offset="3"></bit>
				<bit name="CMPIE" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="I2CIE" offset="6"></bit>
				<bit name="SPIIE" offset="7"></bit>
			</reg>

			<reg name="P0W" addr="9B" read-addr="9B" write-addr="9B" value-addr="9B" addr-visiable="true" bank="0"></reg>
			<reg name="P1W" addr="9C" read-addr="9C" write-addr="9C" value-addr="9C" addr-visiable="true" bank="0"></reg>
			<reg name="P2W" addr="9D" read-addr="9D" write-addr="9D" value-addr="9D" addr-visiable="true" bank="0"></reg>
			<reg name="P4W" addr="9E" read-addr="9E" write-addr="9E" value-addr="9E" addr-visiable="true" bank="0"></reg>

			<reg name="PEDGE" addr="9D" read-addr="9D" write-addr="9D" value-addr="9D" addr-visiable="true" bank="0">
				<bit name="P15G0" offset="0"></bit>
				<bit name="P15G1" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="INTS" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="IRXO" offset="5"></bit>
				<bit name="IRXEN" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="P0M" addr="A0" read-addr="A0" write-addr="A0" value-addr="A0" addr-visiable="true" bank="0"></reg>
			<reg name="P1M" addr="A1" read-addr="A1" write-addr="A1" value-addr="A1" addr-visiable="true" bank="0"></reg>
			<reg name="P2M" addr="A2" read-addr="A2" write-addr="A2" value-addr="A2" addr-visiable="true" bank="0"></reg>
			<reg name="P4M" addr="A3" read-addr="A3" write-addr="A3" value-addr="A3" addr-visiable="true" bank="0"></reg>

			<reg name="P0" addr="A5" read-addr="A5" write-addr="A5" value-addr="A5" addr-visiable="true" bank="0"></reg>
			<reg name="P1" addr="A6" read-addr="A6" write-addr="A6" value-addr="A6" addr-visiable="true" bank="0"></reg>
			<reg name="P2" addr="A7" read-addr="A7" write-addr="A7" value-addr="A7" addr-visiable="true" bank="0"></reg>
			<reg name="P4" addr="A8" read-addr="A8" write-addr="A8" value-addr="A8" addr-visiable="true" bank="0"></reg>

			<reg name="P0UP" addr="AA" read-addr="AA" write-addr="AA" value-addr="AA" addr-visiable="true" bank="0"></reg>
			<reg name="P1UP" addr="AB" read-addr="AB" write-addr="AB" value-addr="AB" addr-visiable="true" bank="0"></reg>
			<reg name="P2UP" addr="AC" read-addr="AC" write-addr="AC" value-addr="AC" addr-visiable="true" bank="0"></reg>
			<reg name="P4UP" addr="AD" read-addr="AD" write-addr="AD" value-addr="AD" addr-visiable="true" bank="0"></reg>

			<reg name="REMC" addr="AF" read-addr="AF" write-addr="AF" value-addr="AF" addr-visiable="true" bank="0">
				<bit name="REM_SEL0" offset="0"></bit>
				<bit name="REM_SEL1" offset="1"></bit>
				<bit name="REM_SEL2" offset="2"></bit>
				<bit name="REM_SEL3" offset="3"></bit>
				<bit name="REM_SEL4" offset="4"></bit>
				<bit name="ELE_EN" offset="5"></bit>
				<bit name="D_SEL" offset="6"></bit>
				<bit name="IE_SEL" offset="7"></bit>
			</reg>

			<reg name="LCDCT0" addr="B0" read-addr="B0" write-addr="B0" value-addr="B0" addr-visiable="true" bank="0">
				<bit name="SCANSEL" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="DUTY0" offset="4"></bit>
				<bit name="DUTY1" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="LCDEN" offset="7"></bit>
			</reg>

			<reg name="LCDDB" addr="B1" read-addr="B1" write-addr="B1" value-addr="B1" addr-visiable="true" bank="0"></reg>
			<reg name="LCDADR" addr="B2" read-addr="B2" write-addr="B2" value-addr="B2" addr-visiable="true" bank="0"></reg>

			<reg name="LCDCT1" addr="B3" read-addr="B3" write-addr="B3" value-addr="B3" addr-visiable="true" bank="0">
				<bit name="LCDCLKS0" offset="0"></bit>
				<bit name="LCDCLKS1" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="VLO0" offset="3"></bit>
				<bit name="VLO1" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="LEDEN" offset="7"></bit>
			</reg>

			<reg name="LCDCT2" addr="B4" read-addr="B4" write-addr="B4" value-addr="B4" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DL" addr="B5" read-addr="B5" write-addr="B5" value-addr="B5" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DH" addr="B6" read-addr="B6" write-addr="B6" value-addr="B6" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0PL" addr="B7" read-addr="B7" write-addr="B7" value-addr="B7" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0PH" addr="B8" read-addr="B8" write-addr="B8" value-addr="B8" addr-visiable="true" bank="0"></reg>

			<reg name="PWM0EN" addr="B9" read-addr="B9" write-addr="B9" value-addr="B9" addr-visiable="true" bank="0">
				<bit name="PWM0_EN" offset="0"></bit>
				<bit name="PWM0_OEN" offset="1"></bit>
				<bit name="PWM01_OEN" offset="2"></bit>
				<bit name="PWM0M" offset="3"></bit>
				<bit name="PWM1_OEN" offset="4"></bit>
				<bit name="TM1SEL8" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="TM1EN" offset="7"></bit>
			</reg>

			<reg name="PWM0C" addr="BA" read-addr="BA" write-addr="BA" value-addr="BA" addr-visiable="true" bank="0">
				<bit name="CK00" offset="0"></bit>
				<bit name="CK01" offset="1"></bit>
				<bit name="PWM0SL0" offset="2"></bit>
				<bit name="PWM0SL1" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="CK02" offset="6"></bit>
				<bit name="CK03" offset="7"></bit>
			</reg>

			<reg name="PWM0TL" addr="BB" read-addr="BB" write-addr="BB" value-addr="BB" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0TH" addr="BC" read-addr="BC" write-addr="BC" value-addr="BC" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DTL" addr="BD" read-addr="BD" write-addr="BD" value-addr="BD" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DTH" addr="BE" read-addr="BE" write-addr="BE" value-addr="BE" addr-visiable="true" bank="0"></reg>

			<reg name="PWMPSC" addr="BF" read-addr="BF" write-addr="BF" value-addr="BF" addr-visiable="true" bank="0">
				<bit name="PWM0S0" offset="0"></bit>
				<bit name="PWM01S0" offset="1"></bit>
				<bit name="PWM1S0" offset="2"></bit>
				<bit name="PWM0S1" offset="3"></bit>
				<bit name="PWM01S1" offset="4"></bit>
				<bit name="PWM1S1" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="P0SS" addr="C0" read-addr="C0" write-addr="C0" value-addr="C0" addr-visiable="true" bank="0"></reg>
			<reg name="P1SS" addr="C1" read-addr="C1" write-addr="C1" value-addr="C1" addr-visiable="true" bank="0"></reg>
			<reg name="P2SS" addr="C2" read-addr="C2" write-addr="C2" value-addr="C2" addr-visiable="true" bank="0"></reg>
			<reg name="P4SS" addr="C3" read-addr="C3" write-addr="C3" value-addr="C3" addr-visiable="true" bank="0"></reg>

			<reg name="ADPCON1" addr="C5" read-addr="C5" write-addr="C5" value-addr="C5" addr-visiable="true" bank="0"></reg>
			<reg name="ADPCON" addr="C7" read-addr="C7" write-addr="C7" value-addr="C7" addr-visiable="true" bank="0"></reg>

			<reg name="ADM" addr="C8" read-addr="C8" write-addr="C8" value-addr="C8" addr-visiable="true" bank="0">
				<bit name="CHS0" offset="0"></bit>
				<bit name="CHS1" offset="1"></bit>
				<bit name="CHS2" offset="2"></bit>
				<bit name="CHS3" offset="3"></bit>
				<bit name="GCHS" offset="4"></bit>
				<bit name="EOC" offset="5"></bit>
				<bit name="ADS" offset="6"></bit>
				<bit name="ADENB" offset="7"></bit>
			</reg>

			<reg name="ADB" addr="C9" read-addr="C9" write-addr="C9" value-addr="C9" addr-visiable="true" bank="0"></reg>

			<reg name="ADR" addr="CA" read-addr="CA" write-addr="CA" value-addr="CA" addr-visiable="true" bank="0">
				<bit name="ADB0" offset="0"></bit>
				<bit name="ADB1" offset="1"></bit>
				<bit name="ADB2" offset="2"></bit>
				<bit name="ADB3" offset="3"></bit>
				<bit name="ADCKS0" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="ASCKS1" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="ADT" addr="CB" read-addr="CB" write-addr="CB" value-addr="CB" addr-visiable="true" bank="0">
				<bit name="ADT0" offset="0"></bit>
				<bit name="ADT1" offset="1"></bit>
				<bit name="ADT2" offset="2"></bit>
				<bit name="ADT3" offset="3"></bit>
				<bit name="ADTS0" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="WDTC" addr="CC" read-addr="CC" write-addr="CC" value-addr="CC" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="WDTC2" offset="2"></bit>
				<bit name="WDTC3" offset="3"></bit>
				<bit name="WDTPRE0" offset="4"></bit>
				<bit name="WDTPRE1" offset="5"></bit>
				<bit name="WDTPRE2" offset="6"></bit>
				<bit name="WDTEN" offset="7"></bit>
			</reg>

			<reg name="SBANK" addr="CD" read-addr="CD" write-addr="CD" value-addr="CD" addr-visiable="true" bank="0"></reg>

			<reg name="VREFH" addr="CE" read-addr="CE" write-addr="CE" value-addr="CE" addr-visiable="true" bank="0">
				<bit name="VHS0" offset="0"></bit>
				<bit name="VHS1" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="EVHENB" offset="7"></bit>
			</reg>

			<reg name="LVDC" addr="CF" read-addr="CF" write-addr="CF" value-addr="CF" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="LVDTE" offset="7"></bit>
			</reg>

			<reg name="P0PD" addr="D0" read-addr="D0" write-addr="D0" value-addr="D0" addr-visiable="true" bank="0"></reg>
			<reg name="P1PD" addr="D1" read-addr="D1" write-addr="D1" value-addr="D1" addr-visiable="true" bank="0"></reg>
			<reg name="P2PD" addr="D2" read-addr="D2" write-addr="D2" value-addr="D2" addr-visiable="true" bank="0"></reg>
			<reg name="P4PD" addr="D3" read-addr="D3" write-addr="D3" value-addr="D3" addr-visiable="true" bank="0"></reg>

			<reg name="TKC0" addr="D5" read-addr="D5" write-addr="D5" value-addr="D5" addr-visiable="true" bank="0">
				<bit name="TKPS0" offset="0"></bit>
				<bit name="TKPS1" offset="1"></bit>
				<bit name="TKPS2" offset="2"></bit>
				<bit name="TKPS3" offset="3"></bit>
				<bit name="CHRVS" offset="4"></bit>
				<bit name="TKGCHS" offset="5"></bit>
				<bit name="TKST" offset="6"></bit>
				<bit name="TKEN" offset="7"></bit>
			</reg>

			<reg name="TK16DH" addr="D6" read-addr="D6" write-addr="D6" value-addr="D6" addr-visiable="true" bank="0"></reg>
			<reg name="TK16DL" addr="D7" read-addr="D7" write-addr="D7" value-addr="D7" addr-visiable="true" bank="0"></reg>

			<reg name="TKC1" addr="D8" read-addr="D8" write-addr="D8" value-addr="D8" addr-visiable="true" bank="0">
				<bit name="DCTS0" offset="0"></bit>
				<bit name="DCTS1" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="CCFLT0" offset="4"></bit>
				<bit name="CCFLT1" offset="5"></bit>
				<bit name="CCFLT2" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="TKC2" addr="D9" read-addr="D9" write-addr="D9" value-addr="D9" addr-visiable="true" bank="0">
				<bit name="CTS0" offset="0"></bit>
				<bit name="CTS1" offset="1"></bit>
				<bit name="CTS2" offset="2"></bit>
				<bit name="CTS3" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="TKC3" addr="DA" read-addr="DA" write-addr="DA" value-addr="DA" addr-visiable="true" bank="0">
				<bit name="CVREFS0" offset="0"></bit>
				<bit name="CVREFS1" offset="1"></bit>
				<bit name="CVREFS2" offset="2"></bit>
				<bit name="CVREFS3" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="TKSTA" addr="DB" read-addr="DB" write-addr="DB" value-addr="DB" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="SACMP0" offset="1"></bit>
				<bit name="ACMPO" offset="2"></bit>
				<bit name="DCMPO" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TKINTIE" offset="5"></bit>
				<bit name="TKINTIF" offset="6"></bit>
				<bit name="TMOUT" offset="7"></bit>
			</reg>

			<reg name="TKPDH" addr="DC" read-addr="DC" write-addr="DC" value-addr="DC" addr-visiable="true" bank="0"></reg>
			<reg name="TKPDL" addr="DD" read-addr="DD" write-addr="DD" value-addr="DD" addr-visiable="true" bank="0"></reg>

			<reg name="ADF1" addr="DE" read-addr="DE" write-addr="DE" value-addr="DE" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="ADF17" offset="7"></bit>
			</reg>

			<reg name="ADF0" addr="DC" read-addr="DC" write-addr="DC" value-addr="DC" addr-visiable="true" bank="0"></reg>
			<reg name="P0OD" addr="E0" read-addr="E0" write-addr="E0" value-addr="E0" addr-visiable="true" bank="0"></reg>
			<reg name="P1OD" addr="E1" read-addr="E1" write-addr="E1" value-addr="E1" addr-visiable="true" bank="0"></reg>
			<reg name="P2OD" addr="E2" read-addr="E2" write-addr="E2" value-addr="E2" addr-visiable="true" bank="0"></reg>
			<reg name="P4OD" addr="E3" read-addr="E3" write-addr="E3" value-addr="E3" addr-visiable="true" bank="0"></reg>
			<reg name="SMTS" addr="E4" read-addr="E4" write-addr="E4" value-addr="E4" addr-visiable="true" bank="0"></reg>

			<reg name="TC0D2" addr="E6" read-addr="E6" write-addr="E6" value-addr="E6" addr-visiable="true" bank="0"></reg>

			<reg name="TC0M1" addr="E7" read-addr="E7" write-addr="E7" value-addr="E7" addr-visiable="true" bank="0">
				<bit name="PWM1EN" offset="0"></bit>
				<bit name="PWM2EN" offset="1"></bit>
				<bit name="PWM0S0" offset="2"></bit>
				<bit name="PWM1S0" offset="3"></bit>
				<bit name="PWM2S0" offset="4"></bit>
				<bit name="PWM0S0" offset="5"></bit>
				<bit name="PWM1S0" offset="6"></bit>
				<bit name="PWM2S0" offset="7"></bit>
			</reg>

			<reg name="PWM1DL" addr="E8" read-addr="E8" write-addr="E8" value-addr="E8" addr-visiable="true" bank="0"></reg>
			<reg name="PWM1DH" addr="E9" read-addr="E9" write-addr="E9" value-addr="E9" addr-visiable="true" bank="0"></reg>

			<reg name="TC0M" addr="EA" read-addr="EA" write-addr="EA" value-addr="EA" addr-visiable="true" bank="0">
				<bit name="PWM0" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="INT0CK" offset="2"></bit>
				<bit name="TCCKS" offset="3"></bit>
				<bit name="TC0S0" offset="4"></bit>
				<bit name="TC0S1" offset="5"></bit>
				<bit name="TC0S2" offset="6"></bit>
				<bit name="TC0TR" offset="7"></bit>
			</reg>

			<reg name="TC0R" addr="EB" read-addr="EB" write-addr="EB" value-addr="EB" addr-visiable="true" bank="0"></reg>
			<reg name="TC0CL" addr="EC" read-addr="EC" write-addr="EC" value-addr="EC" addr-visiable="true" bank="0"></reg>
			<reg name="TC0CH" addr="ED" read-addr="ED" write-addr="ED" value-addr="ED" addr-visiable="true" bank="0"></reg>
			<reg name="TC0D1" addr="EE" read-addr="EE" write-addr="EE" value-addr="EE" addr-visiable="true" bank="0"></reg>

			<reg name="STKP" addr="EF" read-addr="EF" write-addr="EF" value-addr="EF" addr-visiable="true" bank="0">
				<bit name="STKPB0" offset="0"></bit>
				<bit name="STKPB1" offset="1"></bit>
				<bit name="STKPB2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>

			<reg name="STK7L" addr="F0" read-addr="F0" write-addr="F0" value-addr="F0" addr-visiable="true" bank="0"></reg>
			<reg name="STK7H" addr="F1" read-addr="F1" write-addr="F1" value-addr="F1" addr-visiable="true" bank="0"></reg>
			<reg name="STK6L" addr="F2" read-addr="F2" write-addr="F2" value-addr="F2" addr-visiable="true" bank="0"></reg>
			<reg name="STK6H" addr="F3" read-addr="F3" write-addr="F3" value-addr="F3" addr-visiable="true" bank="0"></reg>
			<reg name="STK5L" addr="F4" read-addr="F4" write-addr="F4" value-addr="F4" addr-visiable="true" bank="0"></reg>
			<reg name="STK5H" addr="F5" read-addr="F5" write-addr="F5" value-addr="F5" addr-visiable="true" bank="0"></reg>
			<reg name="STK4L" addr="F6" read-addr="F6" write-addr="F6" value-addr="F6" addr-visiable="true" bank="0"></reg>
			<reg name="STK4H" addr="F7" read-addr="F7" write-addr="F7" value-addr="F7" addr-visiable="true" bank="0"></reg>
			<reg name="STK3L" addr="F8" read-addr="F8" write-addr="F8" value-addr="F8" addr-visiable="true" bank="0"></reg>
			<reg name="STK3H" addr="F9" read-addr="F9" write-addr="F9" value-addr="F9" addr-visiable="true" bank="0"></reg>
			<reg name="STK2L" addr="FA" read-addr="FA" write-addr="FA" value-addr="FA" addr-visiable="true" bank="0"></reg>
			<reg name="STK2H" addr="FB" read-addr="FB" write-addr="FB" value-addr="FB" addr-visiable="true" bank="0"></reg>
			<reg name="STK1L" addr="FC" read-addr="FC" write-addr="FC" value-addr="FC" addr-visiable="true" bank="0"></reg>
			<reg name="STK1H" addr="FD" read-addr="FD" write-addr="FD" value-addr="FD" addr-visiable="true" bank="0"></reg>
			<reg name="STK0L" addr="FE" read-addr="FE" write-addr="FE" value-addr="FE" addr-visiable="true" bank="0"></reg>
			<reg name="STK0H" addr="FF" read-addr="FF" write-addr="FF" value-addr="FF" addr-visiable="true" bank="0"></reg>

			<reg name="TL0C1" addr="1B0" read-addr="8B0" write-addr="8B0" value-addr="8B0" addr-visiable="true" bank="1"></reg>
			<reg name="TL0C2" addr="1B1" read-addr="8B1" write-addr="8B1" value-addr="8B1" addr-visiable="true" bank="1"></reg>
			<reg name="TL0C3" addr="1B2" read-addr="8B2" write-addr="8B2" value-addr="8B2" addr-visiable="true" bank="1"></reg>
			<reg name="PWM3DL" addr="1B3" read-addr="8B3" write-addr="8B3" value-addr="8B3" addr-visiable="true" bank="1"></reg>
			<reg name="PWM3DH" addr="1B4" read-addr="8B4" write-addr="8B4" value-addr="8B4" addr-visiable="true" bank="1"></reg>
			<reg name="PWM2DL" addr="1B5" read-addr="8B5" write-addr="8B5" value-addr="8B5" addr-visiable="true" bank="1"></reg>
			<reg name="PWM2DH" addr="1B6" read-addr="8B6" write-addr="8B6" value-addr="8B6" addr-visiable="true" bank="1"></reg>
			<reg name="PWM2PL" addr="1B7" read-addr="8B7" write-addr="8B7" value-addr="8B7" addr-visiable="true" bank="1"></reg>
			<reg name="PWM2PH" addr="1B8" read-addr="8B8" write-addr="8B8" value-addr="8B8" addr-visiable="true" bank="1"></reg>

			<reg name="PWM1EN" addr="1B9" read-addr="8B9" write-addr="8B9" value-addr="8B9" addr-visiable="true" bank="1">
				<bit name="PWM2_EN" offset="0"></bit>
				<bit name="PWM2_OEN" offset="1"></bit>
				<bit name="PWM21_OEN" offset="2"></bit>
				<bit name="PWM1M" offset="3"></bit>
				<bit name="PWM3_OEN" offset="4"></bit>
				<bit name="TM2SEL8" offset="5"></bit>
				<bit name="TM2SEL16" offset="6"></bit>
				<bit name="TM2EN" offset="7"></bit>
			</reg>

			<reg name="PWM2C" addr="1BA" read-addr="8BA" write-addr="8BA" value-addr="8BA" addr-visiable="true" bank="1">
				<bit name="CK20" offset="0"></bit>
				<bit name="CK21" offset="1"></bit>
				<bit name="PWM2SL0" offset="2"></bit>
				<bit name="PWM2SEL" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="CK22" offset="6"></bit>
				<bit name="CK23" offset="7"></bit>
			</reg>


			<reg name="PWM2TL" addr="1BB" read-addr="8BB" write-addr="8BB" value-addr="8BB" addr-visiable="true" bank="1"></reg>
			<reg name="PWM2TH" addr="1BC" read-addr="8BC" write-addr="8BC" value-addr="8BC" addr-visiable="true" bank="1"></reg>
			<reg name="PWM2DTL" addr="1BD" read-addr="8BD" write-addr="8BD" value-addr="8BD" addr-visiable="true" bank="1"></reg>
			<reg name="PWM2DTH" addr="1BE" read-addr="8BE" write-addr="8BE" value-addr="8BE" addr-visiable="true" bank="1"></reg>

			<reg name="PWM2PSC" addr="1BF" read-addr="8BF" write-addr="8BF" value-addr="8BF" addr-visiable="true" bank="1">
				<bit name="PWM2S0" offset="0"></bit>
				<bit name="PWM21S0" offset="1"></bit>
				<bit name="PWM3S0" offset="2"></bit>
				<bit name="PWM3S1" offset="3"></bit>
				<bit name="PWM21S1" offset="4"></bit>
				<bit name="PWM3S1" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="P0SC" addr="1C0" read-addr="8C0" write-addr="8C0" value-addr="8C0" addr-visiable="true" bank="1"></reg>
			<reg name="P4SC" addr="1C1" read-addr="8C1" write-addr="8C1" value-addr="8C1" addr-visiable="true" bank="1"></reg>
			<reg name="P0SI" addr="1C2" read-addr="8C2" write-addr="8C2" value-addr="8C2" addr-visiable="true" bank="1"></reg>
			<reg name="P1SI" addr="1C3" read-addr="8C3" write-addr="8C3" value-addr="8C3" addr-visiable="true" bank="1"></reg>
			<reg name="P2SI" addr="1C4" read-addr="8C4" write-addr="8C4" value-addr="8C4" addr-visiable="true" bank="1"></reg>
			<reg name="P4SI" addr="1C5" read-addr="8C5" write-addr="8C5" value-addr="8C5" addr-visiable="true" bank="1"></reg>

			<reg name="TL0M" addr="1C7" read-addr="8C7" write-addr="8C7" value-addr="8C7" addr-visiable="true" bank="1">
				<bit name="PWM2S0" offset="0"></bit>
				<bit name="PWM21S0" offset="1"></bit>
				<bit name="PWM3S0" offset="2"></bit>
				<bit name="PWM3S1" offset="3"></bit>
				<bit name="PWM21S1" offset="4"></bit>
				<bit name="PWM3S1" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="TL0C" addr="1C8" read-addr="8C8" write-addr="8C8" value-addr="8C0" addr-visiable="true" bank="1"></reg>

			<reg name="T0M" addr="1C9" read-addr="8C9" write-addr="8C9" value-addr="8C9" addr-visiable="true" bank="1">
				<bit name="TC0GN" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="T0CK" offset="2"></bit>
				<bit name="TP0SEL" offset="3"></bit>
				<bit name="TP0S0" offset="4"></bit>
				<bit name="TP0S1" offset="5"></bit>
				<bit name="TP0S2" offset="6"></bit>
				<bit name="T0TR" offset="7"></bit>
			</reg>

			<reg name="T0L" addr="1CA" read-addr="8CA" write-addr="8CA" value-addr="8CA" addr-visiable="true" bank="1"></reg>
			<reg name="T0H" addr="1CB" read-addr="8CB" write-addr="8CB" value-addr="8CB" addr-visiable="true" bank="1"></reg>

			<reg name="T0M1" addr="1CC" read-addr="8CC" write-addr="8CC" value-addr="8CC" addr-visiable="true" bank="1">
				<bit name="T0GN" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="T0OVS" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="PWMW1" offset="4"></bit>
				<bit name="PWMW2" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="TIRCF" addr="1CE" read-addr="8CE" write-addr="8CE" value-addr="8CE" addr-visiable="true" bank="1"></reg>
			<reg name="I2CCON" addr="1D0" read-addr="8D0" write-addr="8D0" value-addr="8D0" addr-visiable="true" bank="1">
				<bit name="I2CEN" offset="0"></bit>
				<bit name="I2CPU" offset="1"></bit>
				<bit name="CKP" offset="2"></bit>
				<bit name="TXAK" offset="3"></bit>
				<bit name="SRW" offset="4"></bit>
				<bit name="HBB" offset="5"></bit>
				<bit name="HAAS" offset="6"></bit>
				<bit name="HCF" offset="7"></bit>
			</reg>

			<reg name="I2CADR" addr="1D1" read-addr="8D1" write-addr="8D1" value-addr="8D1" addr-visiable="true" bank="1"></reg>
			<reg name="I2CBUF" addr="1D2" read-addr="8D2" write-addr="8D2" value-addr="8D2" addr-visiable="true" bank="1"></reg>

			<reg name="I2CTOV" addr="1D3" read-addr="8D3" write-addr="8D3" value-addr="8D3" addr-visiable="true" bank="1">
				<bit name="TOS0" offset="0"></bit>
				<bit name="TOS0" offset="1"></bit>
				<bit name="TOS0" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="TOVF" offset="6"></bit>
				<bit name="TOVEN" offset="7"></bit>
			</reg>

			<reg name="RCSTA" addr="1E0" read-addr="8E0" write-addr="8E0" value-addr="8E0" addr-visiable="true" bank="1">
				<bit name="RX9D" offset="0"></bit>
				<bit name="OERR" offset="1"></bit>
				<bit name="FERR" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="CREN" offset="4"></bit>
				<bit name="SREN" offset="5"></bit>
				<bit name="RX9" offset="6"></bit>
				<bit name="SPEN" offset="7"></bit>
			</reg>

			<reg name="TXREG" addr="1E1" read-addr="8E1" write-addr="8E1" value-addr="8E1" addr-visiable="true" bank="1"></reg>
			<reg name="RXREG" addr="1E2" read-addr="8E2" write-addr="8E2" value-addr="8E2" addr-visiable="true" bank="1"></reg>

			<reg name="TXSTA" addr="1E3" read-addr="8E3" write-addr="8E3" value-addr="8E3" addr-visiable="true" bank="1">
				<bit name="TX9D" offset="0"></bit>
				<bit name="TRMT" offset="1"></bit>
				<bit name="BRGH" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="SYNC" offset="4"></bit>
				<bit name="TXEN" offset="5"></bit>
				<bit name="TX9" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="SPBRG" addr="1E4" read-addr="8E4" write-addr="8E4" value-addr="8E4" addr-visiable="true" bank="1"></reg>
			<reg name="SPBRGH" addr="1E5" read-addr="8E5" write-addr="8E5" value-addr="8E5" addr-visiable="true" bank="1"></reg>

			<reg name="BAUDCTL" addr="1E6" read-addr="8E6" write-addr="8E6" value-addr="8E6" addr-visiable="true" bank="1">
				<bit name="IFTX" offset="0"></bit>
				<bit name="IFRX" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="ITXEN" offset="4"></bit>
				<bit name="IRXEN" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="SIMC0" addr="1E7" read-addr="8E7" write-addr="8E7" value-addr="8E7" addr-visiable="true" bank="1">
				<bit name="--" offset="0"></bit>
				<bit name="SPIEN" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="SIMM0" offset="5"></bit>
				<bit name="SIMM1" offset="6"></bit>
				<bit name="SIMM2" offset="7"></bit>
			</reg>

			<reg name="SIMC1" addr="1E8" read-addr="8E8" write-addr="8E8" value-addr="8E8" addr-visiable="true" bank="1">
				<bit name="TRF" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="SSEN" offset="2"></bit>
				<bit name="MLS" offset="3"></bit>
				<bit name="CKP" offset="4"></bit>
				<bit name="CKEG" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="SIMD" addr="1EA" read-addr="8EA" write-addr="8EA" value-addr="8EA" addr-visiable="true" bank="1"></reg>

			<reg name="ITFACES" addr="1ED" read-addr="8ED" write-addr="8ED" value-addr="8ED" addr-visiable="true" bank="1">
				<bit name="RXIN" offset="0"></bit>
				<bit name="TXOUT" offset="1"></bit>
				<bit name="I2CSCL" offset="2"></bit>
				<bit name="I2CSDA" offset="3"></bit>
				<bit name="SPICLK" offset="4"></bit>
				<bit name="SCS" offset="5"></bit>
				<bit name="SPIIN" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="ITFACES1" addr="1EE" read-addr="8EE" write-addr="8EE" value-addr="8EE" addr-visiable="true" bank="1">
				<bit name="UARTPTS0" offset="0"></bit>
				<bit name="UARTPTS1" offset="1"></bit>
				<bit name="UARTPTS2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="SIMD" addr="2B1" read-addr="10B1" write-addr="10B1" value-addr="10B1" addr-visiable="true" bank="2"></reg>
			<reg name="LFSEL" addr="2B2" read-addr="10B2" write-addr="10B2" value-addr="10B2" addr-visiable="true" bank="2"></reg>
			<reg name="PWM4DL" addr="2B5" read-addr="10B5" write-addr="10B5" value-addr="10B5" addr-visiable="true" bank="2"></reg>
			<reg name="PWM4DH" addr="2B6" read-addr="10B6" write-addr="10B6" value-addr="10B6" addr-visiable="true" bank="2"></reg>
			<reg name="PWM4PL" addr="2B7" read-addr="10B7" write-addr="10B7" value-addr="10B7" addr-visiable="true" bank="2"></reg>
			<reg name="PWM4PH" addr="2B8" read-addr="10B8" write-addr="10B8" value-addr="10B8" addr-visiable="true" bank="2"></reg>

			<reg name="PWM2EN" addr="2B9" read-addr="10B9" write-addr="10B9" value-addr="10B9" addr-visiable="true" bank="2">
				<bit name="PWM4_EN" offset="0"></bit>
				<bit name="PWM4_OEN" offset="1"></bit>
				<bit name="PWM41_OEN" offset="2"></bit>
				<bit name="PWM2M" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TM3SEL9" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="TM3EN" offset="7"></bit>		
			</reg>

			<reg name="PWM4C" addr="2BA" read-addr="10BA" write-addr="10BA" value-addr="10BA" addr-visiable="true" bank="2">
				<bit name="CK40" offset="0"></bit>
				<bit name="CK41" offset="1"></bit>
				<bit name="PWM4SL0" offset="2"></bit>
				<bit name="PWM4SL1" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="CK42" offset="6"></bit>
				<bit name="CK43" offset="7"></bit>		
			</reg>

			<reg name="PWM4TL" addr="2BB" read-addr="10BB" write-addr="10BB" value-addr="10BB" addr-visiable="true" bank="2"></reg>
			<reg name="PWM4TH" addr="2BC" read-addr="10BC" write-addr="10BC" value-addr="10BC" addr-visiable="true" bank="2"></reg>
			<reg name="PWM4DTL" addr="2BD" read-addr="10BD" write-addr="10BD" value-addr="10BD" addr-visiable="true" bank="2"></reg>
			<reg name="PWM4DTH" addr="2BE" read-addr="10BE" write-addr="10BE" value-addr="10BE" addr-visiable="true" bank="2"></reg>

			<reg name="LOAD" addr="2CF" read-addr="10CF" write-addr="10CF" value-addr="10CF" addr-visiable="true" bank="2"></reg>
			<reg name="FDATL" addr="2DF" read-addr="10DF" write-addr="10DF" value-addr="10DF" addr-visiable="true" bank="2"></reg>
			<reg name="EADRL" addr="2E0" read-addr="10E0" write-addr="10E0" value-addr="10E0" addr-visiable="true" bank="2"></reg>

			<reg name="EECON1" addr="2E1" read-addr="10E1" write-addr="10E1" value-addr="10E1" addr-visiable="true" bank="2">
				<bit name="READEE" offset="0"></bit>
				<bit name="PROGEE" offset="1"></bit>
				<bit name="ERASEEE" offset="2"></bit>
				<bit name="ERSALLEE" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TIMEE0" offset="5"></bit>
				<bit name="TIMEE1" offset="6"></bit>
				<bit name="--" offset="7"></bit>	
			</reg>

			<reg name="EDATL" addr="2E2" read-addr="10E2" write-addr="10E2" value-addr="10E2" addr-visiable="true" bank="2"></reg>

			<reg name="CMPCON" addr="2E3" read-addr="10E3" write-addr="10E3" value-addr="10E3" addr-visiable="true" bank="2">
				<bit name="--" offset="0"></bit>
				<bit name="COPOL" offset="1"></bit>
				<bit name="CVEN+" offset="2"></bit>
				<bit name="CPEN+" offset="3"></bit>
				<bit name="CODEB" offset="4"></bit>
				<bit name="FTCKS" offset="5"></bit>
				<bit name="CMPIF" offset="6"></bit>
				<bit name="CMPEN" offset="7"></bit>	
			</reg>

			<reg name="CMPM" addr="2E4" read-addr="10E4" write-addr="10E4" value-addr="10E4" addr-visiable="true" bank="2">
				<bit name="VRS0" offset="0"></bit>
				<bit name="VRS1" offset="1"></bit>
				<bit name="VRS2" offset="2"></bit>
				<bit name="VRS3" offset="3"></bit>
				<bit name="XRVSEL" offset="4"></bit>
				<bit name="CPINS0" offset="5"></bit>
				<bit name="CPINS1" offset="6"></bit>
				<bit name="COMSEL" offset="7"></bit>	
			</reg>

			<reg name="OPAM" addr="2E5" read-addr="10E5" write-addr="10E5" value-addr="10E5" addr-visiable="true" bank="2"></reg>
			<reg name="OPAM1" addr="2E6" read-addr="10E6" write-addr="10E6" value-addr="10E6" addr-visiable="true" bank="2"></reg>

			<reg name="OPAMC" addr="2E7" read-addr="10E7" write-addr="10E7" value-addr="10E7" addr-visiable="true" bank="2">
				<bit name="AP1NS" offset="0"></bit>
				<bit name="AP1NS0" offset="1"></bit>
				<bit name="AP1OS" offset="2"></bit>
				<bit name="AP1OSP" offset="3"></bit>
				<bit name="AP1PS0" offset="4"></bit>
				<bit name="AP1PS" offset="5"></bit>
				<bit name="LVHSEN" offset="6"></bit>
				<bit name="OPAMC7" offset="7"></bit>	
			</reg>

			<reg name="OPAMC1" addr="2E8" read-addr="10E8" write-addr="10E8" value-addr="10E8" addr-visiable="true" bank="2">
				<bit name="AP2NS" offset="0"></bit>
				<bit name="AP2NS0" offset="1"></bit>
				<bit name="AP2OS" offset="2"></bit>
				<bit name="AP2OSP" offset="3"></bit>
				<bit name="AP2PS0" offset="4"></bit>
				<bit name="AP2PS" offset="5"></bit>
				<bit name="LVHSEN1" offset="6"></bit>
				<bit name="OPAMC17" offset="7"></bit>	
			</reg>

			<reg name="FLER" addr="2E9" read-addr="10E9" write-addr="10E9" value-addr="10E9" addr-visiable="true" bank="2">
				<bit name="FOV" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>	
			</reg>

			<reg name="FADRH" addr="2EA" read-addr="10EA" write-addr="10EA" value-addr="10EA" addr-visiable="true" bank="2"></reg>
			<reg name="FADRL" addr="2EB" read-addr="10EB" write-addr="10EB" value-addr="10EB" addr-visiable="true" bank="2"></reg>

			<reg name="FCON1" addr="2EC" read-addr="10EC" write-addr="10EC" value-addr="10EC" addr-visiable="true" bank="2">
				<bit name="READL" offset="0"></bit>
				<bit name="PROGL" offset="1"></bit>
				<bit name="ERASEL" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TIMEL0" offset="5"></bit>
				<bit name="TIMEL1" offset="6"></bit>
				<bit name="CEFL" offset="7"></bit>	
			</reg>

			<reg name="FCON2" addr="2ED" read-addr="10ED" write-addr="10ED" value-addr="10ED" addr-visiable="true" bank="2"></reg>
			<reg name="FDATH" addr="2EE" read-addr="10EE" write-addr="10EE" value-addr="10EE" addr-visiable="true" bank="2"></reg>

		</sfr>	
	</sfrs>
	<insts>
		<inst name="call" value="c000" mask-value="c000"/>
		<inst name="return" value="0e00" mask-value="ffff"/>
		<inst name="return" value="0f00" mask-value="ffff"/>
	</insts>
	<eeprom>
		<size>256</size>
		<addr>0</addr>	
		<update-addr>310</update-addr>
	</eeprom>	
	<ccs-config>
		<config-item addr="548" bit="no">1</config-item>
	</ccs-config>		
	<compilers>
		<compiler>	
			<compiler-item type="c" name="cc2" command-path="$(DevEnvDir)\cc2.exe">
				<option>-chip-name $(ChipName) -chip-ver $(ChipVer) -chip-id $(ChipID) -file-ver $(CCSFileVer) -rom-size $(UserRomSize) -debug false -c h1 -clean-ram false -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -config "$(ConfigWord)" -lib "$GetFiles('.lib',';')"  -inc-dir "$GetFolders(';')" -src-files "$GetFiles('.c',';')" -inc-files "$GetFiles('.h;.inc',';')"</option>
				<action-before-compile>
				</action-before-compile> 
				<action-after-compile >
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="asm" name="ac0" command-path="$(DevEnvDir)\ac0.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -ram-start $(RamStartAddr) -ram-size $(RamSize) -reset-addr $(ResetAddr) -inst-set INST_SET_8F22E8 -otp-body-size $(OtpBodySize) -debug false -symbol-file true  -listfile true -workdir "$(ProjectDir)" -include-path "$GetFolders(';')" -file "$(EntryFile)" -output "$(OutDir)" -project-name "$(ProjectName)" -config "$(ConfigWord)"</option>
				<action-before-compile>
				</action-before-compile>
				<action-after-compile>
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="c" name="cc2" out-type="lib" command-path="$(DevEnvDir)\cc2.exe">
				<option>-chip-name $(ChipName) -chip-ver $(ChipVer) -chip-id $(ChipID) -file-ver $(CCSFileVer) -rom-size $(UserRomSize) -debug false  -c h1 -clean-ram false -prj-name "$(ProjectName)"  -out-type $(ProjectType) -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -config "$(ConfigWord)" -lib "$GetFiles('.lib',';')"  -inc-dir "$GetFolders(';')" -src-files "$GetFiles('.c',';')" -inc-files "$GetFiles('.h;.inc',';')"</option>
			</compiler-item>			
		</compiler>	
	</compilers>
	<debugers>
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>snc</debuger-c>
			<device type="4" version="0">
				<simulator type="3" version="0" code-first="false" config-item="false" config-item-id="-1">
					<pc-addr pcl="FF1" pch="FF2" />
					<config-word-addr>1FF8</config-word-addr>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>
		</debuger>		
	</debugers>
	<editor-language>
		<c-lang name="c2-lang"/>
		<asm-lang name="asm3-lang"/>
	</editor-language>	
</chip>