#ifndef __SN8P2267E__H
#define __SN8P2267E__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FSTKOV = 0x86:4;
sbit	FRST = 0x86:5;
sbit	FWDT = 0x86:6;
sbit	FPOR = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sfr	_HL = 0x90;
sfr	_YZ = 0x91;
sfr	PCL = 0x93;
sfr	PCH = 0x94;
sfr	OSCM = 0x95;
sbit	FCPUM1 = 0x95:4;
sbit	FCPUM0 = 0x95:3;
sbit	FCLKMD = 0x95:2;
sbit	FSTPHX = 0x95:1;
sfr	WDTR = 0x96;
sfr	INTRQ = 0x97;
sbit	FNDTIRQ = 0x97:7;
sbit	FUSBIRQ = 0x97:6;
sbit	FTC0IRQ = 0x97:5;
sbit	FAKAIRQ = 0x97:4;
sbit	FWAKEIRQ = 0x97:2;
sbit	FP00IRQ = 0x97:0;
sfr	INTEN = 0x99;
sbit	FNDTIEN = 0x99:7;
sbit	FUSBIEN = 0x99:6;
sbit	FTC0IEN = 0x99:5;
sbit	FAKAIEN = 0x99:4;
sbit	FWAKEIEN = 0x99:2;
sbit	FP00IEN = 0x99:0;
sfr	PEDGE = 0x9f;
sbit	FP00G1 = 0x9f:1;
sbit	FP00G0 = 0x9f:0;
sfr	P0M = 0xa0;
sbit	FP07M = 0xa0:7;
sbit	FP06M = 0xa0:6;
sbit	FP05M = 0xa0:5;
sbit	FP04M = 0xa0:4;
sbit	FP03M = 0xa0:3;
sbit	FP02M = 0xa0:2;
sbit	FP01M = 0xa0:1;
sbit	FP00M = 0xa0:0;
sfr	P1M = 0xa1;
sbit	FP17M = 0xa1:7;
sbit	FP16M = 0xa1:6;
sbit	FP15M = 0xa1:5;
sbit	FP14M = 0xa1:4;
sbit	FP13M = 0xa1:3;
sbit	FP12M = 0xa1:2;
sbit	FP11M = 0xa1:1;
sbit	FP10M = 0xa1:0;
sfr	P2M = 0xa2;
sbit	FP27M = 0xa2:7;
sbit	FP26M = 0xa2:6;
sbit	FP25M = 0xa2:5;
sbit	FP24M = 0xa2:4;
sbit	FP23M = 0xa2:3;
sbit	FP22M = 0xa2:2;
sbit	FP21M = 0xa2:1;
sbit	FP20M = 0xa2:0;
sfr	P3M = 0xa3;
sbit	FP36M = 0xa3:6;
sbit	FP35M = 0xa3:5;
sbit	FP34M = 0xa3:4;
sbit	FP33M = 0xa3:3;
sbit	FP32M = 0xa3:2;
sbit	FP31M = 0xa3:1;
sbit	FP30M = 0xa3:0;
sfr	P5M = 0xa4;
sbit	FP55M = 0xa4:5;
sbit	FP54M = 0xa4:4;
sbit	FP53M = 0xa4:3;
sbit	FP52M = 0xa4:2;
sbit	FP51M = 0xa4:1;
sbit	FP50M = 0xa4:0;
sfr	P0 = 0xa5;
sbit	FP07 = 0xa5:7;
sbit	FP06 = 0xa5:6;
sbit	FP05 = 0xa5:5;
sbit	FP04 = 0xa5:4;
sbit	FP03 = 0xa5:3;
sbit	FP02 = 0xa5:2;
sbit	FP01 = 0xa5:1;
sbit	FP00 = 0xa5:0;
sfr	P1 = 0xa6;
sbit	FP17 = 0xa6:7;
sbit	FP16 = 0xa6:6;
sbit	FP15 = 0xa6:5;
sbit	FP14 = 0xa6:4;
sbit	FP13 = 0xa6:3;
sbit	FP12 = 0xa6:2;
sbit	FP11 = 0xa6:1;
sbit	FP10 = 0xa6:0;
sfr	P2 = 0xa7;
sbit	FP27 = 0xa7:7;
sbit	FP26 = 0xa7:6;
sbit	FP25 = 0xa7:5;
sbit	FP24 = 0xa7:4;
sbit	FP23 = 0xa7:3;
sbit	FP22 = 0xa7:2;
sbit	FP21 = 0xa7:1;
sbit	FP20 = 0xa7:0;
sfr	P3 = 0xa8;
sbit	FP37 = 0xa8:7;
sbit	FP36 = 0xa8:6;
sbit	FP35 = 0xa8:5;
sbit	FP34 = 0xa8:4;
sbit	FP33 = 0xa8:3;
sbit	FP32 = 0xa8:2;
sbit	FP31 = 0xa8:1;
sbit	FP30 = 0xa8:0;
sfr	P5 = 0xa9;
sbit	FP55 = 0xa9:5;
sbit	FP54 = 0xa9:4;
sbit	FP53 = 0xa9:3;
sbit	FP52 = 0xa9:2;
sbit	FP51 = 0xa9:1;
sbit	FP50 = 0xa9:0;
sfr	P0UR = 0xaa;
sbit	FP07R = 0xaa:7;
sbit	FP06R = 0xaa:6;
sbit	FP05R = 0xaa:5;
sbit	FP04R = 0xaa:4;
sbit	FP03R = 0xaa:3;
sbit	FP02R = 0xaa:2;
sbit	FP01R = 0xaa:1;
sbit	FP00R = 0xaa:0;
sfr	P1UR = 0xab;
sbit	FP17R = 0xab:7;
sbit	FP16R = 0xab:6;
sbit	FP15R = 0xab:5;
sbit	FP14R = 0xab:4;
sbit	FP13R = 0xab:3;
sbit	FP12R = 0xab:2;
sbit	FP11R = 0xab:1;
sbit	FP10R = 0xab:0;
sfr	P2UR = 0xac;
sbit	FP27R = 0xac:7;
sbit	FP26R = 0xac:6;
sbit	FP25R = 0xac:5;
sbit	FP24R = 0xac:4;
sbit	FP23R = 0xac:3;
sbit	FP22R = 0xac:2;
sbit	FP21R = 0xac:1;
sbit	FP20R = 0xac:0;
sfr	P3UR = 0xad;
sbit	FP36R = 0xad:6;
sbit	FP35R = 0xad:5;
sbit	FP32R = 0xad:2;
sbit	FP31R = 0xad:1;
sbit	FP30R = 0xad:0;
sfr	P5UR = 0xae;
sbit	FP55R = 0xae:5;
sbit	FP54R = 0xae:4;
sbit	FP53R = 0xae:3;
sbit	FP52R = 0xae:2;
sbit	FP51R = 0xae:1;
sbit	FP50R = 0xae:0;
sfr	P3DR = 0xaf;
sbit	FP37DR = 0xaf:7;
sfr	TC0M = 0xb8;
sbit	FTC0ENB = 0xb8:7;
sbit	FTC0RATE2 = 0xb8:6;
sbit	FTC0RATE1 = 0xb8:5;
sbit	FTC0RATE0 = 0xb8:4;
sbit	FALOAD0 = 0xb8:2;
sfr	TC0C = 0xb9;
sfr	TC0R = 0xba;
sfr	UDA = 0xcc;
sbit	FUDE = 0xcc:7;
sbit	FUDA6 = 0xcc:6;
sbit	FUDA5 = 0xcc:5;
sbit	FUDA4 = 0xcc:4;
sbit	FUDA3 = 0xcc:3;
sbit	FUDA2 = 0xcc:2;
sbit	FUDA1 = 0xcc:1;
sbit	FUDA0 = 0xcc:0;
sfr	USTATUS = 0xcd;
sbit	FEP0_PRESETUP = 0xcd:6;
sbit	FERR_SETUP = 0xcd:5;
sbit	FBUS_RST = 0xcd:4;
sbit	FSUSPEND = 0xcd:3;
sbit	FEP0SETUP = 0xcd:2;
sbit	FEP0IN = 0xcd:1;
sbit	FEP0OUT = 0xcd:0;
sfr	EP0OUT_CNT = 0xce;
sbit	FUEP0OC4 = 0xce:4;
sbit	FUEP0OC3 = 0xce:3;
sbit	FUEP0OC2 = 0xce:2;
sbit	FUEP0OC1 = 0xce:1;
sbit	FUEP0OC0 = 0xce:0;
sfr	USB_INT_EN = 0xcf;
sbit	FREG_EN = 0xcf:7;
sbit	FDN_PU_EN = 0xcf:6;
sbit	FIHRCCTR_EN = 0xcf:5;
sbit	FSMPC_CTL = 0xcf:4;
sbit	FEP2_NAK_EN = 0xcf:3;
sbit	FEP1_NAK_EN = 0xcf:2;
sbit	FUE2D = 0xcf:1;
sbit	FUE1D = 0xcf:0;
sfr	EP_ACK = 0xd0;
sbit	FEP2_NAK = 0xd0:3;
sbit	FEP1_NAK = 0xd0:2;
sbit	FEP2_ACK = 0xd0:1;
sbit	FEP1_ACK = 0xd0:0;
sfr	EP0_STALL = 0xd1;
sbit	FEP0_OUT_STALL = 0xd1:1;
sbit	FEP0_IN_STALL = 0xd1:0;
sfr	UE0R = 0xd5;
sbit	FUE0E = 0xd5:7;
sbit	FUE0M1 = 0xd5:6;
sbit	FUE0M0 = 0xd5:5;
sbit	FUE0C3 = 0xd5:3;
sbit	FUE0C2 = 0xd5:2;
sbit	FUE0C1 = 0xd5:1;
sbit	FUE0C0 = 0xd5:0;
sfr	UE1R = 0xd7;
sbit	FUE1E = 0xd7:7;
sbit	FUE1M1 = 0xd7:6;
sbit	FUE1M0 = 0xd7:5;
sbit	FUE1C3 = 0xd7:3;
sbit	FUE1C2 = 0xd7:2;
sbit	FUE1C1 = 0xd7:1;
sbit	FUE1C0 = 0xd7:0;
sfr	UE2R = 0xd9;
sbit	FUE2E = 0xd9:7;
sbit	FUE2M1 = 0xd9:6;
sbit	FUE2M0 = 0xd9:5;
sbit	FUE2C3 = 0xd9:3;
sbit	FUE2C2 = 0xd9:2;
sbit	FUE2C1 = 0xd9:1;
sbit	FUE2C0 = 0xd9:0;
sfr	UPID = 0xe3;
sbit	FUBDE = 0xe3:2;
sbit	FDDP = 0xe3:1;
sbit	FDDN = 0xe3:0;
sfr	IHRC_CTL = 0xe5;
sbit	FIAA_EN = 0xe5:7;
sbit	FKAD_EN = 0xe5:6;
sfr	UTOGGLE = 0xe8;
sbit	FEP2_DATA01 = 0xe8:1;
sbit	FEP1_DATA01 = 0xe8:0;
sfr	UNDT = 0xe9;
sbit	FNDT_EN = 0xe9:7;
sbit	FNDT = 0xe9:0;
sfr	STKP = 0xef;
sbit	FGIE = 0xef:7;
sbit	FSTKPB2 = 0xef:2;
sbit	FSTKPB1 = 0xef:1;
sbit	FSTKPB0 = 0xef:0;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
