/******************************************************************
;UPDATA DATE:2019/12/17
;USER:Cuiyn
;HS23P6610
******************************************************************/
#ifndef _DEF_H
#define _DEF_H

/////////////////////////////////////////
struct bitRegister{
	unsigned bit0:1;
	unsigned bit1:1;
	unsigned bit2:1;
	unsigned bit3:1;
	unsigned bit4:1;
	unsigned bit5:1;
	unsigned bit6:1;
	unsigned bit7:1;
};
//////////////////////////////////////////
typedef unsigned char 	BYTE;
typedef unsigned long 	WORD;
typedef double 			DWORD;
////////////////////////////////////////////
//sfr define for HS23P6610
////////////////////////////////////////////
//=================================================
//¼Ä´æÆ÷ºê¶¨Òå 
//=================================================
//0X80~0X8F
sfr		L 		= 	0x80;
sfr		H		= 	0x81;
sfr		R		= 	0x82;
sfr		Z 		= 	0x83;

sfr		Y 		= 	0x84;
sfr		PFLAG 	= 	0x86;
	sbit	FZ		=	0x86:0;
	sbit	FDC		=	0x86:1;
	sbit	FC		=	0x86:2;
	
	sbit	FLVD24	=	0x86:4;
	sbit	FLVD36	=	0x86:5;
	sbit	FNPD	=	0x86:6;
	sbit	FNT0	=	0x86:7;
	
sfr		RBANK 	= 	0x87;
	sbit	FRBANKS0=	0x87:0;

//=================================================
//0XA0~0XAF
sfr		ADCCN1	= 	0xA4;
	sbit	FADGN0	=	0xA4:0;
	sbit	FADGN1	=	0xA4:1;
	sbit	FADGN2	=	0xA4:2;	
	sbit	FENACM	=	0xA4:3;
	
	sbit	FENTEMP	=	0xA4:4;
	sbit	FENCHP	=	0xA4:5;
	sbit	FADrst	=	0xA4:6;
	sbit	FENADC	=	0xA4:7;
	
sfr		ADCCN2	= 	0xA5;
	sbit	FDCSET0	=	0xA5:0;
	sbit	FDCSET1	=	0xA5:1;
	sbit	FDCSET2	=	0xA5:2;	
	sbit	FVREGN	=	0xA5:3;
	
	sbit	FOSR0	=	0xA5:4;
	sbit	FOSR1	=	0xA5:5;
	sbit	FOSR2	=	0xA5:6;
	sbit	FOSR3	=	0xA5:7;
	
sfr		ADRESH	= 	0xA6;
sfr		ADRES_H	= 	0xA6;
sfr		AINET1	= 	0xA7;
	sbit	FINIS	=	0xA7:1;
    sbit	FAD_INIS=   0xA7:1; 
	sbit	FINL0	=	0xA7:2;	
	sbit	FINL1	=	0xA7:3;	
	sbit	FINL2	=	0xA7:4;
	sbit	FINH0	=	0xA7:5;
	sbit	FINH1	=	0xA7:6;
	sbit	FINH2	=	0xA7:7;

sfr		AINET2	= 	0xA8;
	sbit	FVRL0	=	0xA8:1;
	sbit	FVRL1	=	0xA8:2;	
	
	sbit	FINX0	=	0xA8:3;	
	sbit	FINX1	=	0xA8:4;
	
	sbit	FVRH0	=	0xA8:5;
	sbit	FVRH1	=	0xA8:6;
	
sfr		ADRESM	= 	0xA9;
sfr		ADRES_M	= 	0xA9;
sfr		ADRESL	= 	0xAA;
sfr		ADRES_L	= 	0xAA;

sfr		ADCPCON= 	0xAB;
sbit	FP40AD = 0xAB:0;  
sbit	FP41AD = 0xAB:1;  
sbit	FP02AD = 0xAB:2;  
sbit	FP03AD = 0xAB:3;  
sbit	FP04AD = 0xAB:4;  
sbit	FP05AD = 0xAB:5;  
sbit	FP06AD = 0xAB:6;  
sbit	FP07AD = 0xAB:7; 

sfr		PWRCN	= 	0xAC;
	sbit	FDri_CON2	=	0xAC:0;
	sbit	FDri_CON3	=	0xAC:1;
	sbit	FDri_CON4	=	0xAC:2;	
	
	sbit	FVDDAX0		=	0xAC:4;
	sbit	FVDDAX1		=	0xAC:5;

sfr		OSCCN1 	= 	0xAE;
sfr		ADCCK 	= 	0xAE;
	sbit	FADCS0	=	0xAE:3;	
	sbit	FADCS1	=	0xAE:4;
	sbit	FADCS2	=	0xAE:5;
	sbit	FDHS0	=	0xAE:6;
	sbit	FDHS1	=	0xAE:7;

//=================================================
//0XB0~0XBF
sfr		P0W		= 	0xB0;
sfr		P4W		= 	0xB1;
sfr		P5W		= 	0xB2;

sfr		LCDEN	= 	0xB3;
	sbit	FDRIVE_S		=	0xB3:0;
	sbit	FBIAS_S		=	0xB3:1;
	
	sbit	FLCDEN		=	0xB3:7;
	
sfr		I2CCON	= 	0xB4;
	sbit	FI2CEN	=	0xB4:0;
	sbit	FI2CPU	=	0xB4:1;
	sbit	FCKP	=	0xB4:2;	
	sbit	FTXAK	=	0xB4:3;
	
	sbit	FSRW	=	0xB4:4;
	sbit	FHBB	=	0xB4:5;
	sbit	FHAAS	=	0xB4:6;
	sbit	FHCF	=	0xB4:7;
	
sfr		I2CADD	= 	0xB5;
sfr		I2CBUF	= 	0xB6;

sfr		LCDP0CON= 	0xB7;
	sbit	LCDP00CON	=0xB7:0;
	sbit	LCDP01CON	=0xB7:1;
	sbit	LCDP02CON	=0xB7:2;
	sbit	LCDP03CON	=0xB7:3;
	sbit	LCDP04CON	=0xB7:4;
	sbit	LCDP05CON	=0xB7:5;
	sbit	LCDP06CON	=0xB7:6;
	sbit	LCDP07CON	=0xB7:7;

sfr		P0M		= 	0xB8;

sfr		LCDP0B0	= 	0xB9;
	sbit	FP0BIAS00	=0xB9:0;
	sbit	FP0BIAS01	=0xB9:1;
	sbit	FP0BIAS02	=0xB9:2;
	sbit	FP0BIAS03	=0xB9:3;
	sbit	FP0BIAS04	=0xB9:4;
	sbit	FP0BIAS05	=0xB9:5;
	sbit	FP0BIAS06	=0xB9:6;
	sbit	FP0BIAS07	=0xB9:7;

sfr		LCDP0B1	= 	0xBA;
	sbit	FP0BIAS10	=0xBA:0;
	sbit	FP0BIAS11	=0xBA:1;
	sbit	FP0BIAS12	=0xBA:2;
	sbit	FP0BIAS13	=0xBA:3;
	sbit	FP0BIAS14	=0xBA:4;
	sbit	FP0BIAS15	=0xBA:5;
	sbit	FP0BIAS16	=0xBA:6;
	sbit	FP0BIAS17	=0xBA:7;	


sfr		LCDP45B0= 	0xBB;
	sbit	FP45BIAS00	=0xBB:0;
	sbit	FP45BIAS01	=0xBB:1;
	sbit	FP45BIAS02	=0xBB:2;
	sbit	FP45BIAS03	=0xBB:3;
	sbit	FP45BIAS04	=0xBB:4;
	sbit	FP45BIAS05	=0xBB:5;

sfr		LCDP45B1= 	0xBC;
	sbit	FP45BIAS10	=0xBC:0;
	sbit	FP45BIAS11	=0xBC:1;
	sbit	FP45BIAS12	=0xBC:2;
	sbit	FP45BIAS13	=0xBC:3;
	sbit	FP45BIAS14	=0xBC:4;
	sbit	FP45BIAS15	=0xBC:5;

sfr		PEDGE	= 	0xBF;
	sbit	FP00G0	=	0xBF:3;
	sbit	FP00G1	=	0xBF:4;

//=================================================
//0XC0~0XCF
sfr		P4M		= 	0xC4;
sfr		P5M		= 	0xC5;
	sbit    FP51M   = 0xC5:1;

sfr		LCDP4CON= 	0xC6;
	sbit	LCDP40CON	=0xC6:0;
	sbit	LCDP41CON	=0xC6:1;
sfr		LCDP5CON= 	0xC7;
	sbit	LCDP51CON	=0xC7:1;
	sbit	LCDP52CON	=0xC7:2;
	sbit	LCDP53CON	=0xC7:3;
	sbit	LCDP54CON	=0xC7:4;

sfr		INTRQ	= 	0xC8;
	sbit	FP00IF	=	0xC8:0;
	sbit	FP01IF	=	0xC8:1;
	sbit	FI2CIF	=	0xC8:2;
	sbit	FTC0IF	=	0xC8:5;
	sbit	FTC1IF	=	0xC8:6;
	sbit	FADCIF	=	0xC8:7;
    	sbit	FADCIRQ	=	0xC8:7;

sfr		INTEN	= 	0xC9;
	sbit	FP00IEN	=	0xC9:0;
	sbit	FP01IEN	=	0xC9:1;
	sbit	FI2CIEN	=	0xC9:2;
	sbit	FTC0IEN	=	0xC9:5;
	sbit	FTC1IEN	=	0xC9:6;
	sbit	FADCIEN	=	0xC9:7;

sfr		OSCM	= 	0xCA;
	sbit	FCPUM1 = 0xca:4;
	sbit	FCPUM0 = 0xca:3;
	sbit	FCLKMD = 0xca:2;
	sbit	FSTPHX = 0xca:1;
	

sfr		WDTC	= 	0xCB;
	sbit	FWDTEN	=	0xCB:7;
	
sfr		WDTR	= 	0xCC;

sfr		TC0R	= 	0xCD;
sfr		TCH		= 	0xCD;
	
sfr		PCL		= 	0xCE;
sfr		PCH		= 	0xCF;

//=================================================
//0XD0~0XDF
sfr		P0		= 	0xD0;
	sbit	FP00 = 0xd0:0;
	sbit	FP01 = 0xd0:1;
	sbit	FP02 = 0xd0:2;
	sbit	FP03 = 0xd0:3;
	
	sbit	FP04 = 0xd0:4;
	sbit	FP05 = 0xd0:5;
	sbit	FP06 = 0xd0:6;
	sbit	FP07 = 0xd0:7;
	
sfr		P4		= 	0xD4;
	sbit	FP40 = 0xd4:0;
	sbit	FP41 = 0xd4:1;
	
sfr		P5		= 	0xD5;
	sbit	FP51 = 0xd5:1;
	sbit	FP52 = 0xd5:2;
	sbit	FP53 = 0xd5:3;
	sbit	FP54 = 0xd5:4;

sfr		T0M		= 	0xD8;
	sbit	FTC0GN = 0xd8:1;
	sbit	FTC0X8 = 0xd8:2;
	sbit	FTC1X8 = 0xd8:3;
	sbit	FTC0S16 = 0xd8:4;
	sbit	FTC1S16 = 0xd8:5;

sfr		PWMCON	= 	0xD9;
	sbit	FPWM1EN 	= 0xd9:0;
	sbit	FPWM2EN 	= 0xd9:1;
	sbit	FPWM1_PSEL 	= 0xd9:2;
	sbit	FPWM2_PSEL 	= 0xd9:3;
	
	sbit	FPWM1_OSEL 	= 0xd9:4;
	sbit	FPWM2_OSEL 	= 0xd9:5;
	sbit	FPWM0_OSEL 	= 0xd9:6;

sfr		TC0M	= 	0xDA;
	sbit	FTC0ENB 	= 0xda:7;
	sbit	FTC0R 		= 0xda:7;
	sbit	FTC0RATE2 	= 0xda:6;
	sbit	FTC0PS2 	= 0xda:6;
	sbit	FTC0RATE1 	= 0xda:5;
	sbit	FTC0PS1 	= 0xda:5;
	sbit	FTC0RATE0 	= 0xda:4;
	sbit	FTC0PS0 	= 0xda:4;
	
	sbit	FTC0CKS 	= 0xda:3;
	sbit	FALOAD0 	= 0xda:2;
	sbit	FTC0OUT 	= 0xda:1;
	sbit	FPWM0OUT 	= 0xda:0;
	
sfr		TC0C	= 	0xDB;

sfr		TC1M	= 	0xDC;
	sbit	FTC1ENB 	= 0xdc:7;
	sbit	FTC1R 		= 0xdc:7;
	sbit	FTC1RATE2 	= 0xdc:6;
	sbit	FTC1PS2 	= 0xdc:6;
	sbit	FTC1RATE1 	= 0xdc:5;
	sbit	FTC1PS1 	= 0xdc:5;
	sbit	FTC1RATE0 	= 0xdc:4;
	sbit	FTC1PS0 	= 0xdc:4;
	
	sbit	FTC1CKS 	= 0xdc:3;
	sbit	FALOAD1 	= 0xdc:2;
	sbit	FTC1OUT 	= 0xdc:1;
	sbit	FPWM1OUT 	= 0xdc:0;
	
sfr		TC1C	= 	0xDD;
sfr		TC1R	= 	0xDE;

sfr		STKP	= 	0xDF;
	sbit	FGIE 	= 0xdf:7;
	sbit	FSTKPB2 = 0xdf:2;
	sbit	FSTKPB1 = 0xdf:1;
	sbit	FSTKPB0 = 0xdf:0;

//=================================================
//0XE0~0XEF
sfr		P0UR	= 	0xE0;
sfr		P4UR	= 	0xE4;
sfr		P5UR	= 	0xE5;
sbit	FP51UR = 0xE5:1; 
sfr		_HL		= 	0xE6;
sfr		_YZ		= 	0xE7;

sfr		TC0R0	= 	0xE9;
sfr		TC0R1	= 	0xEA;
sfr		TC0R2	= 	0xEB;

//=================================================
//0XF0~0XFF
sfr		STK7L	= 	0xF0;
sfr		STK7H	= 	0xF1;
sfr		STK6L	= 	0xF2;
sfr		STK6H	= 	0xF3;
sfr		STK5L	= 	0xF4;
sfr		STK5H	= 	0xF5;
sfr		STK4L	= 	0xF6;
sfr		STK4H	= 	0xF7;

sfr		STK3L	= 	0xF8;
sfr		STK3H	= 	0xF9;
sfr		STK2L	= 	0xFA;
sfr		STK2H	= 	0xFB;
sfr		STK1L	= 	0xFC;
sfr		STK1H	= 	0xFD;
sfr		STK0L	= 	0xFE;
sfr		STK0H	= 	0xFF;

//=================================================
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}


/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
#define HIBYTE(wval)		*(((BYTE*)(&wval))+1)
#define LWBYTE(wval)		*(((BYTE*)(&wval))+0)

#define HIWORD(wval)		*(((WORD*)(&wval))+1)
#define LWWORD(wval)		*(((WORD*)(&wval))+0)


#endif
