<?xml version="1.0" encoding="UTF-8"?>
<chip>
	<configure-file-ver>1.0</configure-file-ver>
	<chip-name>HS23P6631</chip-name>
	<chip-classes>ADC MCU</chip-classes>
	<chip-id>77</chip-id>
	<chip-ver>0</chip-ver>
	<chip-id-debug>f902</chip-id-debug>
	<ccs-file-ver>4</ccs-file-ver>
	<ram-start-addr>0</ram-start-addr>
	<ram-size>256</ram-size>
	<otp-body-size>2048</otp-body-size>
	<user-rom-size>2048</user-rom-size>
	<reset-addr>0</reset-addr>
	<stack-level>8</stack-level>
	<config-word-count>5</config-word-count>	
	<max-breakpoint>16</max-breakpoint>	
	<asm-inc>$(DevEnvDir)\asm_inc\$(ChipName).inc</asm-inc>
	<clang-inc>$(DevEnvDir)\include\$(ChipName).h</clang-inc>				
	<description></description>
	<rams>
		<ram mode="fpga" start-addr="0" length="512">
			<ram-segment start-addr="00" size="128" write-addr="00" read-addr="00" value-addr="00" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="80" size="128" write-addr="80" read-addr="80" value-addr="80" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="100" size="256" write-addr="100" read-addr="100" value-addr="100" visiable="true" bank="1"></ram-segment>		
			<ram-segment start-addr="200" size="1" write-addr="8087" read-addr="8087" value-addr="200" visiable="false" bank="-1"></ram-segment>	
		</ram>	
		<ram mode="ic" start-addr="0" length="512">
			<ram-segment start-addr="00" size="128" write-addr="00" read-addr="00" value-addr="00" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="80" size="128" write-addr="80" read-addr="80" value-addr="80" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="100" size="256" write-addr="100" read-addr="100" value-addr="100" visiable="true" bank="1"></ram-segment>		
			<ram-segment start-addr="200" size="1" write-addr="0ff0" read-addr="0ff0" value-addr="200" visiable="false" bank="-1"></ram-segment>	
		</ram>			
	</rams>
	<configs>
		<config-word index="0" or-value="0000" and-value="ffff" mapto="0"></config-word>
		<config-word index="1" or-value="0400" and-value="C3ff" mapto="1"></config-word>	
		
		
		<config-item name="LVD" width="2" offset="13" default-value="2" enable="true" config-index="0">
			<config-item-value name="LVD_H" value="2"></config-item-value>
			<config-item-value name="LVD_M" value="1"></config-item-value>
			<config-item-value name="LVD_L" value="0"></config-item-value>
			<description>低电压复位选择</description>
		</config-item>	
		<config-item name="看门狗" width="4" offset="8" default-value="0" enable="true" config-index="0">
			<config-item-value name="always on" value="0"></config-item-value>
			<config-item-value name="enable" value="5"></config-item-value>
			<config-item-value name="disable" value="10"></config-item-value>
			<description>看门狗</description>
		</config-item>
		<config-item name="Fcpu" width="3" offset="2" default-value="1" enable="true" config-index="0">
			<config-item-value name="Fosc/2" value="0"></config-item-value>
			<config-item-value name="Fosc/4" value="1"></config-item-value>
			<config-item-value name="Fosc/8" value="2"></config-item-value>
			<config-item-value name="Fosc/16" value="3"></config-item-value>
			<config-item-value name="Fosc/32" value="4"></config-item-value>
			<description>CPU时钟分频</description>
		</config-item>
		<config-item name="加密" width="1" offset="1" default-value="0" enable="true" config-index="0">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>芯片数据保护功能，加密后数据无法读出来</description>
		</config-item>		
		<config-item name="低通滤波" width="1" offset="0" default-value="0" enable="true" config-index="0">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>低通滤波</description>
		</config-item>					
		<config-item name="参考电流源个数" width="4" offset="10" default-value="1" enable="true" config-index="1">
			<config-item-value name="1/8" value="0"></config-item-value>
			<config-item-value name="1" value="1"></config-item-value>
			<config-item-value name="2" value="2"></config-item-value>
			<config-item-value name="3" value="3"></config-item-value>
			<config-item-value name="4" value="4"></config-item-value>
			<config-item-value name="5" value="5"></config-item-value>
			<config-item-value name="6" value="6"></config-item-value>
			<config-item-value name="7" value="7"></config-item-value>
			<config-item-value name="8" value="8"></config-item-value>
			<config-item-value name="9" value="9"></config-item-value>
			<config-item-value name="10" value="10"></config-item-value>
			<config-item-value name="1/4" value="11"></config-item-value>
			<config-item-value name="12" value="12"></config-item-value>
			<config-item-value name="1/2" value="13"></config-item-value>
			<config-item-value name="14" value="14"></config-item-value>
			<config-item-value name="16" value="15"></config-item-value>
			<description>
			</description>
		</config-item>	
		<config-item name="读指令周期" width="2" offset="1" default-value="0" enable="true" config-index="1">
			<config-item-value name="全指令周期" value="0"></config-item-value>
			<config-item-value name="半指令周期" value="2"></config-item-value>
			<config-item-value name="1/4指令周期" value="3"></config-item-value>
			<description>
			1/4指令周期:在单指令芯片中不适用，如果选中，则还是半指令周期
			</description>
		</config-item>	
		<config-item name="低功耗" width="1" offset="0" default-value="0" enable="true" config-index="1">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>
			在低频时使用，有效时可以大幅降低功耗
			</description>
		</config-item>					
	</configs>
	
	
	<sfrs>
		<sfr mode="fpga">
			<reg name="A" addr="200" read-addr="8087" write-addr="8087" value-addr="200" addr-visiable="false" bank="-1"></reg>

			<reg name="L" addr="80" read-addr="80" write-addr="80" value-addr="80" addr-visiable="false" bank="0"></reg>
			<reg name="H" addr="81" read-addr="81" write-addr="81" value-addr="81" addr-visiable="false" bank="0"></reg>
			<reg name="R" addr="82" read-addr="82" write-addr="82" value-addr="82" addr-visiable="false" bank="0"></reg>
			<reg name="Z" addr="83" read-addr="83" write-addr="83" value-addr="83" addr-visiable="false" bank="0"></reg>
			<reg name="Y" addr="84" read-addr="84" write-addr="84" value-addr="84" addr-visiable="false" bank="0"></reg>
		
			<reg name="PFLAG" addr="86"  read-addr="86" write-addr="86" value-addr="86" addr-visiable="false" bank="0">
				<bit name="Z" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="C" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="LVDF24" offset="4"></bit>
				<bit name="LVDF36" offset="5"></bit>
				<bit name="PD" offset="6"></bit>
				<bit name="TO" offset="7"></bit>
			</reg>
			
			<reg name="RBANK" addr="87" read-addr="87" write-addr="87" value-addr="87" addr-visiable="true" bank="0"></reg>
			<reg name="PTADCON" addr="A4" read-addr="A4" write-addr="A4" value-addr="A4" addr-visiable="true" bank="0"></reg>
			
			<reg name="ADCSEL" addr="A5" read-addr="A5" write-addr="A5" value-addr="A5" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="AD7_VREF_SEL" offset="3"></bit>
				<bit name="CHS0" offset="4"></bit>
				<bit name="CHS1" offset="5"></bit>
				<bit name="CHS2" offset="6"></bit>
				<bit name="CHS3" offset="7"></bit>
			</reg>			
			
			<reg name="ADRESH" addr="A6" read-addr="A6" write-addr="A6" value-addr="A6" addr-visiable="true" bank="0"></reg>			
			
			<reg name="ADCON" addr="A7" read-addr="A7" write-addr="A7" value-addr="A7" addr-visiable="true" bank="0">
				<bit name="LDOEN" offset="0"></bit>
				<bit name="AD7EN" offset="1"></bit>
				<bit name="LIGHT_R_EN" offset="2"></bit>
				<bit name="ADC_CLK_SEL" offset="3"></bit>
				<bit name="SAD7ONTM" offset="4"></bit>
				<bit name="SAD7SENS" offset="5"></bit>
				<bit name="SBPLP" offset="6"></bit>
				<bit name="SAD14D" offset="7"></bit>
			</reg>				
			
			<reg name="OPTION" addr="A8" read-addr="A8" write-addr="A8" value-addr="A8" addr-visiable="true" bank="0">
				<bit name="WDT0" offset="0"></bit>
				<bit name="WDT1" offset="1"></bit>
				<bit name="WDT2" offset="2"></bit>
				<bit name="P4CON0" offset="3"></bit>
				<bit name="P4CON1" offset="4"></bit>
				<bit name="ADC_CLK_D0" offset="5"></bit>
				<bit name="ADC_CLK_D1" offset="6"></bit>
				<bit name="84KOSC_EN" offset="7"></bit>
			</reg>				
			
			<reg name="ADRESM" addr="A9" read-addr="A9" write-addr="A9" value-addr="A9" addr-visiable="true" bank="0"></reg>			
			<reg name="ADRESL" addr="AA" read-addr="AA" write-addr="AA" value-addr="AA" addr-visiable="true" bank="0"></reg>			
			<reg name="P0M" addr="B8" read-addr="B8" write-addr="B8" value-addr="B8" addr-visiable="true" bank="0"></reg>			
			<reg name="PEDGE" addr="BF" read-addr="BF" write-addr="BF" value-addr="BF" addr-visiable="true" bank="0"></reg>		
			
			<reg name="P2M" addr="C2" read-addr="C2" write-addr="C2" value-addr="C2" addr-visiable="true" bank="0"></reg>			
			<reg name="P4M" addr="C4" read-addr="C4" write-addr="C4" value-addr="C4" addr-visiable="true" bank="0"></reg>			
			<reg name="P5M" addr="C5" read-addr="C5" write-addr="C5" value-addr="C5" addr-visiable="true" bank="0"></reg>			
			
			<reg name="INTRQ" addr="C8" read-addr="C8" write-addr="C8" value-addr="C8" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TC0IRQ" offset="5"></bit>
				<bit name="TC1IRQ" offset="6"></bit>
				<bit name="ADCIRQ" offset="7"></bit>
			</reg>			
			
			<reg name="INTEN" addr="C9" read-addr="C9" write-addr="C9" value-addr="C9" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TC0IEN" offset="5"></bit>
				<bit name="TC1IEN" offset="6"></bit>
				<bit name="ADCIEN" offset="7"></bit>
			</reg>			
			
			<reg name="OSCM" addr="CA" read-addr="CA" write-addr="CA" value-addr="CA" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="CLKMD" offset="2"></bit>
				<bit name="CPUM0" offset="3"></bit>
				<bit name="CPUM1" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>				
			
			
			<reg name="WDTR" addr="CC" read-addr="CC" write-addr="CC" value-addr="CC" addr-visiable="true" bank="0"></reg>			
			<reg name="TC0R" addr="CD" read-addr="CD" write-addr="CD" value-addr="CD" addr-visiable="true" bank="0"></reg>			
			<reg name="PCL" addr="CE" read-addr="CE" write-addr="CE" value-addr="CE" addr-visiable="true" bank="0"></reg>			
			<reg name="PCH" addr="CF" read-addr="CF" write-addr="CF" value-addr="CF" addr-visiable="true" bank="0"></reg>				
			
			<reg name="P0" addr="D0" read-addr="D0" write-addr="D0" value-addr="D0" addr-visiable="true" bank="0"></reg>			
			<reg name="P2" addr="D2" read-addr="D2" write-addr="D2" value-addr="D2" addr-visiable="true" bank="0"></reg>			
			<reg name="P4" addr="D4" read-addr="D4" write-addr="D4" value-addr="D4" addr-visiable="true" bank="0"></reg>			
			<reg name="P5" addr="D5" read-addr="D5" write-addr="D5" value-addr="D5" addr-visiable="true" bank="0"></reg>				
			
			<reg name="T0M" addr="D8" read-addr="D8" write-addr="D8" value-addr="D8" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="TC0GN" offset="1"></bit>
				<bit name="TC0X8" offset="2"></bit>
				<bit name="TC1X8" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>			
			
			<reg name="TC0M" addr="DA" read-addr="DA" write-addr="DA" value-addr="DA" addr-visiable="true" bank="0">
				<bit name="PWM0OUT" offset="0"></bit>
				<bit name="TC0OUT" offset="1"></bit>
				<bit name="ALOAD0" offset="2"></bit>
				<bit name="TC0CKS" offset="3"></bit>
				<bit name="TC0PS0" offset="4"></bit>
				<bit name="TC0PS1" offset="5"></bit>
				<bit name="TC0PS2" offset="6"></bit>
				<bit name="TC0R" offset="7"></bit>
			</reg>				
			
			<reg name="TC0C" addr="DB" read-addr="DB" write-addr="DB" value-addr="DB" addr-visiable="true" bank="0"></reg>			
			
			<reg name="TC1M" addr="DC" read-addr="DC" write-addr="DC" value-addr="DC" addr-visiable="true" bank="0">
				<bit name="PWM1OUT" offset="0"></bit>
				<bit name="TC1OUT" offset="1"></bit>
				<bit name="ALOAD1" offset="2"></bit>
				<bit name="TC1CKS" offset="3"></bit>
				<bit name="TC1PS0" offset="4"></bit>
				<bit name="TC1PS1" offset="5"></bit>
				<bit name="TC1PS2" offset="6"></bit>
				<bit name="TC1R" offset="7"></bit>
			</reg>	

			<reg name="TC1C" addr="DD" read-addr="DD" write-addr="DD" value-addr="DD" addr-visiable="true" bank="0"></reg>	
			<reg name="TC1R" addr="DE" read-addr="DE" write-addr="DE" value-addr="DE" addr-visiable="true" bank="0"></reg>				
			
			<reg name="STKP" addr="DF" read-addr="DF" write-addr="DF" value-addr="DF" addr-visiable="true" bank="0">
				<bit name="STKPB0" offset="0"></bit>
				<bit name="STKPB1" offset="1"></bit>
				<bit name="STKPB2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>	

			<reg name="P0UP" addr="E0" read-addr="E0" write-addr="E0" value-addr="E0" addr-visiable="true" bank="0"></reg>
			<reg name="P2UP" addr="E2" read-addr="E2" write-addr="E2" value-addr="E2" addr-visiable="true" bank="0"></reg>
			<reg name="P4UP" addr="E4" read-addr="E4" write-addr="E4" value-addr="E4" addr-visiable="true" bank="0"></reg>
			<reg name="P5UP" addr="E5" read-addr="E5" write-addr="E5" value-addr="E5" addr-visiable="true" bank="0"></reg>
			<reg name="@YZ" addr="E7" read-addr="E7" write-addr="E7" value-addr="E7" addr-visiable="true" bank="0"></reg>

			<reg name="STK7L" addr="F0" read-addr="F0" write-addr="F0" value-addr="F0" addr-visiable="true" bank="0"></reg>
			<reg name="STK7H" addr="F1" read-addr="F1" write-addr="F1" value-addr="F1" addr-visiable="true" bank="0"></reg>
			<reg name="STK6L" addr="F2" read-addr="F2" write-addr="F2" value-addr="F2" addr-visiable="true" bank="0"></reg>
			<reg name="STK6H" addr="F3" read-addr="F3" write-addr="F3" value-addr="F3" addr-visiable="true" bank="0"></reg>
			<reg name="STK5L" addr="F4" read-addr="F4" write-addr="F4" value-addr="F4" addr-visiable="true" bank="0"></reg>
			<reg name="STK5H" addr="F5" read-addr="F5" write-addr="F5" value-addr="F5" addr-visiable="true" bank="0"></reg>
			<reg name="STK4L" addr="F6" read-addr="F6" write-addr="F6" value-addr="F6" addr-visiable="true" bank="0"></reg>
			<reg name="STK4H" addr="F7" read-addr="F7" write-addr="F7" value-addr="F7" addr-visiable="true" bank="0"></reg>
			<reg name="STK3L" addr="F8" read-addr="F8" write-addr="F8" value-addr="F8" addr-visiable="true" bank="0"></reg>
			<reg name="STK3H" addr="F9" read-addr="F9" write-addr="F9" value-addr="F9" addr-visiable="true" bank="0"></reg>
			<reg name="STK2L" addr="FA" read-addr="FA" write-addr="FA" value-addr="FA" addr-visiable="true" bank="0"></reg>
			<reg name="STK2H" addr="FB" read-addr="FB" write-addr="FB" value-addr="FB" addr-visiable="true" bank="0"></reg>
			<reg name="STK1L" addr="FC" read-addr="FC" write-addr="FC" value-addr="FC" addr-visiable="true" bank="0"></reg>
			<reg name="STK1H" addr="FD" read-addr="FD" write-addr="FD" value-addr="FD" addr-visiable="true" bank="0"></reg>
			<reg name="STK0L" addr="FE" read-addr="FE" write-addr="FE" value-addr="FE" addr-visiable="true" bank="0"></reg>
			<reg name="STK0H" addr="FF" read-addr="FF" write-addr="FF" value-addr="FF" addr-visiable="true" bank="0"></reg>

		</sfr>	
		<sfr mode="ic">
			<reg name="A" addr="200" read-addr="0ff0" write-addr="0ff0" value-addr="200" addr-visiable="false" bank="-1"></reg>

			<reg name="L" addr="80" read-addr="80" write-addr="80" value-addr="80" addr-visiable="false" bank="0"></reg>
			<reg name="H" addr="81" read-addr="81" write-addr="81" value-addr="81" addr-visiable="false" bank="0"></reg>
			<reg name="R" addr="82" read-addr="82" write-addr="82" value-addr="82" addr-visiable="false" bank="0"></reg>
			<reg name="Z" addr="83" read-addr="83" write-addr="83" value-addr="83" addr-visiable="false" bank="0"></reg>
			<reg name="Y" addr="84" read-addr="84" write-addr="84" value-addr="84" addr-visiable="false" bank="0"></reg>
		
			<reg name="PFLAG" addr="86"  read-addr="86" write-addr="86" value-addr="86" addr-visiable="false" bank="0">
				<bit name="Z" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="C" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="LVDF24" offset="4"></bit>
				<bit name="LVDF36" offset="5"></bit>
				<bit name="PD" offset="6"></bit>
				<bit name="TO" offset="7"></bit>
			</reg>
			
			<reg name="RBANK" addr="87" read-addr="87" write-addr="87" value-addr="87" addr-visiable="true" bank="0"></reg>
			<reg name="PTADCON" addr="A4" read-addr="A4" write-addr="A4" value-addr="A4" addr-visiable="true" bank="0"></reg>
			
			<reg name="ADCSEL" addr="A5" read-addr="A5" write-addr="A5" value-addr="A5" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="AD7_VREF_SEL" offset="3"></bit>
				<bit name="CHS0" offset="4"></bit>
				<bit name="CHS1" offset="5"></bit>
				<bit name="CHS2" offset="6"></bit>
				<bit name="CHS3" offset="7"></bit>
			</reg>			
			
			<reg name="ADRESH" addr="A6" read-addr="A6" write-addr="A6" value-addr="A6" addr-visiable="true" bank="0"></reg>			
			
			<reg name="ADCON" addr="A7" read-addr="A7" write-addr="A7" value-addr="A7" addr-visiable="true" bank="0">
				<bit name="LDOEN" offset="0"></bit>
				<bit name="AD7EN" offset="1"></bit>
				<bit name="LIGHT_R_EN" offset="2"></bit>
				<bit name="ADC_CLK_SEL" offset="3"></bit>
				<bit name="SAD7ONTM" offset="4"></bit>
				<bit name="SAD7SENS" offset="5"></bit>
				<bit name="SBPLP" offset="6"></bit>
				<bit name="SAD14D" offset="7"></bit>
			</reg>				
			
			<reg name="OPTION" addr="A8" read-addr="A8" write-addr="A8" value-addr="A8" addr-visiable="true" bank="0">
				<bit name="WDT0" offset="0"></bit>
				<bit name="WDT1" offset="1"></bit>
				<bit name="WDT2" offset="2"></bit>
				<bit name="P4CON0" offset="3"></bit>
				<bit name="P4CON1" offset="4"></bit>
				<bit name="ADC_CLK_D0" offset="5"></bit>
				<bit name="ADC_CLK_D1" offset="6"></bit>
				<bit name="84KOSC_EN" offset="7"></bit>
			</reg>				
			
			<reg name="ADRESM" addr="A9" read-addr="A9" write-addr="A9" value-addr="A9" addr-visiable="true" bank="0"></reg>			
			<reg name="ADRESL" addr="AA" read-addr="AA" write-addr="AA" value-addr="AA" addr-visiable="true" bank="0"></reg>			
			<reg name="P0M" addr="B8" read-addr="B8" write-addr="B8" value-addr="B8" addr-visiable="true" bank="0"></reg>			
			<reg name="PEDGE" addr="BF" read-addr="BF" write-addr="BF" value-addr="BF" addr-visiable="true" bank="0"></reg>		
			
			<reg name="P2M" addr="C2" read-addr="C2" write-addr="C2" value-addr="C2" addr-visiable="true" bank="0"></reg>			
			<reg name="P4M" addr="C4" read-addr="C4" write-addr="C4" value-addr="C4" addr-visiable="true" bank="0"></reg>			
			<reg name="P5M" addr="C5" read-addr="C5" write-addr="C5" value-addr="C5" addr-visiable="true" bank="0"></reg>			
			
			<reg name="INTRQ" addr="C8" read-addr="C8" write-addr="C8" value-addr="C8" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TC0IRQ" offset="5"></bit>
				<bit name="TC1IRQ" offset="6"></bit>
				<bit name="ADCIRQ" offset="7"></bit>
			</reg>			
			
			<reg name="INTEN" addr="C9" read-addr="C9" write-addr="C9" value-addr="C9" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TC0IEN" offset="5"></bit>
				<bit name="TC1IEN" offset="6"></bit>
				<bit name="ADCIEN" offset="7"></bit>
			</reg>			
			
			<reg name="OSCM" addr="CA" read-addr="CA" write-addr="CA" value-addr="CA" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="CLKMD" offset="2"></bit>
				<bit name="CPUM0" offset="3"></bit>
				<bit name="CPUM1" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>				
			
			
			<reg name="WDTR" addr="CC" read-addr="CC" write-addr="CC" value-addr="CC" addr-visiable="true" bank="0"></reg>			
			<reg name="TC0R" addr="CD" read-addr="CD" write-addr="CD" value-addr="CD" addr-visiable="true" bank="0"></reg>			
			<reg name="PCL" addr="CE" read-addr="CE" write-addr="CE" value-addr="CE" addr-visiable="true" bank="0"></reg>			
			<reg name="PCH" addr="CF" read-addr="CF" write-addr="CF" value-addr="CF" addr-visiable="true" bank="0"></reg>				
			
			<reg name="P0" addr="D0" read-addr="D0" write-addr="D0" value-addr="D0" addr-visiable="true" bank="0"></reg>			
			<reg name="P2" addr="D2" read-addr="D2" write-addr="D2" value-addr="D2" addr-visiable="true" bank="0"></reg>			
			<reg name="P4" addr="D4" read-addr="D4" write-addr="D4" value-addr="D4" addr-visiable="true" bank="0"></reg>			
			<reg name="P5" addr="D5" read-addr="D5" write-addr="D5" value-addr="D5" addr-visiable="true" bank="0"></reg>				
			
			<reg name="T0M" addr="D8" read-addr="D8" write-addr="D8" value-addr="D8" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="TC0GN" offset="1"></bit>
				<bit name="TC0X8" offset="2"></bit>
				<bit name="TC1X8" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>			
			
			<reg name="TC0M" addr="DA" read-addr="DA" write-addr="DA" value-addr="DA" addr-visiable="true" bank="0">
				<bit name="PWM0OUT" offset="0"></bit>
				<bit name="TC0OUT" offset="1"></bit>
				<bit name="ALOAD0" offset="2"></bit>
				<bit name="TC0CKS" offset="3"></bit>
				<bit name="TC0PS0" offset="4"></bit>
				<bit name="TC0PS1" offset="5"></bit>
				<bit name="TC0PS2" offset="6"></bit>
				<bit name="TC0R" offset="7"></bit>
			</reg>				
			
			<reg name="TC0C" addr="DB" read-addr="DB" write-addr="DB" value-addr="DB" addr-visiable="true" bank="0"></reg>			
			
			<reg name="TC1M" addr="DC" read-addr="DC" write-addr="DC" value-addr="DC" addr-visiable="true" bank="0">
				<bit name="PWM1OUT" offset="0"></bit>
				<bit name="TC1OUT" offset="1"></bit>
				<bit name="ALOAD1" offset="2"></bit>
				<bit name="TC1CKS" offset="3"></bit>
				<bit name="TC1PS0" offset="4"></bit>
				<bit name="TC1PS1" offset="5"></bit>
				<bit name="TC1PS2" offset="6"></bit>
				<bit name="TC1R" offset="7"></bit>
			</reg>	

			<reg name="TC1C" addr="DD" read-addr="DD" write-addr="DD" value-addr="DD" addr-visiable="true" bank="0"></reg>	
			<reg name="TC1R" addr="DE" read-addr="DE" write-addr="DE" value-addr="DE" addr-visiable="true" bank="0"></reg>				
			
			<reg name="STKP" addr="DF" read-addr="DF" write-addr="DF" value-addr="DF" addr-visiable="true" bank="0">
				<bit name="STKPB0" offset="0"></bit>
				<bit name="STKPB1" offset="1"></bit>
				<bit name="STKPB2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>	

			<reg name="P0UP" addr="E0" read-addr="E0" write-addr="E0" value-addr="E0" addr-visiable="true" bank="0"></reg>
			<reg name="P2UP" addr="E2" read-addr="E2" write-addr="E2" value-addr="E2" addr-visiable="true" bank="0"></reg>
			<reg name="P4UP" addr="E4" read-addr="E4" write-addr="E4" value-addr="E4" addr-visiable="true" bank="0"></reg>
			<reg name="P5UP" addr="E5" read-addr="E5" write-addr="E5" value-addr="E5" addr-visiable="true" bank="0"></reg>
			<reg name="@YZ" addr="E7" read-addr="E7" write-addr="E7" value-addr="E7" addr-visiable="true" bank="0"></reg>

			<reg name="STK7L" addr="F0" read-addr="F0" write-addr="F0" value-addr="F0" addr-visiable="true" bank="0"></reg>
			<reg name="STK7H" addr="F1" read-addr="F1" write-addr="F1" value-addr="F1" addr-visiable="true" bank="0"></reg>
			<reg name="STK6L" addr="F2" read-addr="F2" write-addr="F2" value-addr="F2" addr-visiable="true" bank="0"></reg>
			<reg name="STK6H" addr="F3" read-addr="F3" write-addr="F3" value-addr="F3" addr-visiable="true" bank="0"></reg>
			<reg name="STK5L" addr="F4" read-addr="F4" write-addr="F4" value-addr="F4" addr-visiable="true" bank="0"></reg>
			<reg name="STK5H" addr="F5" read-addr="F5" write-addr="F5" value-addr="F5" addr-visiable="true" bank="0"></reg>
			<reg name="STK4L" addr="F6" read-addr="F6" write-addr="F6" value-addr="F6" addr-visiable="true" bank="0"></reg>
			<reg name="STK4H" addr="F7" read-addr="F7" write-addr="F7" value-addr="F7" addr-visiable="true" bank="0"></reg>
			<reg name="STK3L" addr="F8" read-addr="F8" write-addr="F8" value-addr="F8" addr-visiable="true" bank="0"></reg>
			<reg name="STK3H" addr="F9" read-addr="F9" write-addr="F9" value-addr="F9" addr-visiable="true" bank="0"></reg>
			<reg name="STK2L" addr="FA" read-addr="FA" write-addr="FA" value-addr="FA" addr-visiable="true" bank="0"></reg>
			<reg name="STK2H" addr="FB" read-addr="FB" write-addr="FB" value-addr="FB" addr-visiable="true" bank="0"></reg>
			<reg name="STK1L" addr="FC" read-addr="FC" write-addr="FC" value-addr="FC" addr-visiable="true" bank="0"></reg>
			<reg name="STK1H" addr="FD" read-addr="FD" write-addr="FD" value-addr="FD" addr-visiable="true" bank="0"></reg>
			<reg name="STK0L" addr="FE" read-addr="FE" write-addr="FE" value-addr="FE" addr-visiable="true" bank="0"></reg>
			<reg name="STK0H" addr="FF" read-addr="FF" write-addr="FF" value-addr="FF" addr-visiable="true" bank="0"></reg>

		</sfr>			
	</sfrs>
	<insts>
		<inst name="call" value="c000" mask-value="c000"/>
		<inst name="return" value="0e00" mask-value="ffff"/>
		<inst name="return" value="0f00" mask-value="ffff"/>
	</insts>
	<compilers>
		<compiler>	
			<compiler-item type="c" name="cc2" command-path="$(DevEnvDir)\cc2.exe">
				<option>-chip-name $(ChipName) -chip-ver $(ChipVer) -chip-id $(ChipID) -file-ver $(CCSFileVer) -rom-size $(UserRomSize) -debug false -c h1 -clean-ram false -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -config "$(ConfigWord)" -lib "$GetFiles('.lib',';')"  -inc-dir "$GetFolders(';')" -src-files "$GetFiles('.c',';')" -inc-files "$GetFiles('.h;.inc',';')"</option>
				<action-before-compile>
				</action-before-compile> 
				<action-after-compile >
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="asm" name="ac0" command-path="$(DevEnvDir)\ac0.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -ram-start $(RamStartAddr) -ram-size $(RamSize) -reset-addr $(ResetAddr) -inst-set INST_SET_2711 -otp-body-size $(OtpBodySize) -debug false -symbol-file true  -listfile true -workdir "$(ProjectDir)" -include-path "$GetFolders(';')" -file "$(EntryFile)" -output "$(OutDir)" -project-name "$(ProjectName)" -config "$(ConfigWord)"</option>
				<action-before-compile>
				</action-before-compile>
				<action-after-compile>
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="c" name="cc2" out-type="lib" command-path="$(DevEnvDir)\cc2.exe">
				<option>-chip-name $(ChipName) -chip-ver $(ChipVer) -chip-id $(ChipID) -file-ver $(CCSFileVer) -rom-size $(UserRomSize) -debug false  -c h1 -clean-ram false -prj-name "$(ProjectName)"  -out-type $(ProjectType) -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -config "$(ConfigWord)" -lib "$GetFiles('.lib',';')"  -inc-dir "$GetFolders(';')" -src-files "$GetFiles('.c',';')" -inc-files "$GetFiles('.h;.inc',';')"</option>
			</compiler-item>			
		</compiler>	
	</compilers>
	<debugers>
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>snc</debuger-c>
			<device type="1" version="0">
				<simulator type="1" version="0" code-first="true" config-item="true" config-item-id="10">
					<pc-addr pcl="ce" pch="cf" />
					<ram-mode>fpga</ram-mode>
					<sfr-mode>fpga</sfr-mode>
					<config-word-addr>800</config-word-addr>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>
		</debuger>	
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>snc</debuger-c>
			<device type="9" version="0">
				<simulator type="9" version="0" code-first="true" config-item="false" config-item-id="-1">
					<pc-addr pcl="ce" pch="cf" />
					<ram-mode>ic</ram-mode>
					<sfr-mode>ic</sfr-mode>
					<config-word-addr>800</config-word-addr>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>
		</debuger>			
	</debugers>
	<editor-language>
		<c-lang name="c2-lang"/>
		<asm-lang name="asm3-lang"/>
	</editor-language>	
</chip>