<?xml version="1.0" encoding="UTF-8"?>
<chip>
	<configure-file-ver>1.0</configure-file-ver>
	<chip-name>HS23P6625L</chip-name>
	<chip-classes>ADC MCU</chip-classes>
	<chip-id>AE</chip-id>
	<chip-ver>0</chip-ver>
	<chip-id-debug>f903</chip-id-debug>
	<ccs-file-ver>4</ccs-file-ver>
	<ram-start-addr>0</ram-start-addr>
	<ram-size>256</ram-size>
	<otp-body-size>2048</otp-body-size>
	<user-rom-size>2044</user-rom-size>
	<reset-addr>0</reset-addr>
	<stack-level>8</stack-level>
	<config-word-count>5</config-word-count>	
	<max-breakpoint>16</max-breakpoint>	
	<asm-inc>$(DevEnvDir)\asm_inc\$(ChipName).inc</asm-inc>
	<clang-inc>$(DevEnvDir)\include\$(ChipName).h</clang-inc>			
	<description></description>
	<rams>
		<ram mode="fpga" start-addr="0" length="384">
			<ram-segment start-addr="00" size="128" write-addr="00" read-addr="00" value-addr="00" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="80" size="128" write-addr="80" read-addr="80" value-addr="80" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="100" size="128" write-addr="100" read-addr="100" value-addr="100" visiable="true" bank="0"></ram-segment>		
			<ram-segment start-addr="200" size="1" write-addr="8087" read-addr="8087" value-addr="200" visiable="false" bank="0"></ram-segment>
		</ram>	
		<ram mode="ic" start-addr="0" length="384">
			<ram-segment start-addr="00" size="128" write-addr="00" read-addr="00" value-addr="00" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="80" size="128" write-addr="80" read-addr="80" value-addr="80" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="100" size="128" write-addr="100" read-addr="100" value-addr="100" visiable="true" bank="0"></ram-segment>		
			<ram-segment start-addr="200" size="1" write-addr="0ff0" read-addr="0ff0" value-addr="200" visiable="false" bank="0"></ram-segment>
		</ram>			
	</rams>
	<configs>
		<config-word index="0" or-value="0000" and-value="ffff" mapto="0"></config-word>
		<config-word index="1" or-value="0000" and-value="ffff" mapto="1"></config-word>	
		<config-word index="2" or-value="0000" and-value="ffff" mapto="3"></config-word>
		
		
		<config-item name="LVD" width="2" offset="11" default-value="0" enable="true" config-index="0">
			<config-item-value name="LVD_H" value="2"></config-item-value>
			<config-item-value name="LVD_M" value="1"></config-item-value>
			<config-item-value name="LVD_L" value="0"></config-item-value>
			<description>
			LVD_H:等价于LVD36_EN使能
			LVD_M:等价于LVD24_EN使能
			LVD_L:等价于LVD36 LVD24关闭
			</description>
		</config-item>
		<config-item name="RST TIME" width="2" offset="9" default-value="0" enable="true" config-index="0">
			<config-item-value name="18ms" value="0"></config-item-value>
			<config-item-value name="36ms" value="1"></config-item-value>
			<config-item-value name="72ms" value="2"></config-item-value>
			<config-item-value name="144ms" value="3"></config-item-value>
			<description>
			复位时间选择：为Enable时，WDT在睡眠模式和绿色模式时无效
			</description>
		</config-item>
		<config-item name="RST PIN" width="1" offset="8" default-value="0" enable="true" config-index="0">
			<config-item-value name="IO" value="0"></config-item-value>
			<config-item-value name="Reset Pin" value="1"></config-item-value>
			<description>P51是否作为复位脚</description>
		</config-item>	
		<config-item name="WDT" width="2" offset="5" default-value="2" enable="true" config-index="0">
			<config-item-value name="Always on" value="0"></config-item-value>
			<config-item-value name="Disable when sleep" value="1"></config-item-value>
			<config-item-value name="Disable" value="2"></config-item-value>
			<description>看门狗使能</description>
		</config-item>	
		<config-item name="Fcpu" width="3" offset="2" default-value="0" enable="true" config-index="0">
			<config-item-value name="Fcpu = Fosc/2" value="0"></config-item-value>
			<config-item-value name="Fcpu = Fosc/4" value="1"></config-item-value>
			<config-item-value name="Fcpu = Fosc/8" value="2"></config-item-value>
			<config-item-value name="Fcpu = Fosc/16" value="3"></config-item-value>
			<config-item-value name="Fcpu = Fosc/32" value="4"></config-item-value>
			<config-item-value name="Fcpu = Fosc/64" value="5"></config-item-value>
			<description>系统时钟分频</description>
		</config-item>
		<config-item name="PROTECT" width="1" offset="1" default-value="0" enable="true" config-index="0">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>芯片数据保护功能，加密后数据无法读出来</description>
		</config-item>	
		<config-item name="P4PD" width="1" offset="0" default-value="1" enable="true" config-index="0">
			<config-item-value name="Disable" value="1"></config-item-value>
			<config-item-value name="Enable" value="0"></config-item-value>
			<description>噪声抑制</description>
		</config-item>			
		<config-item name="OTP读占空比" width="2" offset="1" default-value="0" enable="true" config-index="1">
			<config-item-value name="全指令周期" value="0"></config-item-value>
			<config-item-value name="半指令周期" value="2"></config-item-value>
			<config-item-value name="1/4指令周期" value="3"></config-item-value>
			<description>
			1/4指令周期:在单指令芯片中不适用，如果选中，则还是半指令周期
			</description>
		</config-item>		
		<config-item name="低功耗" width="1" offset="0" default-value="0" enable="true" config-index="1">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>
			在低频时使用，有效时可以大幅降低功耗
			</description>
		</config-item>		
		<config-item name="内置RC选择" width="1" offset="8" default-value="0" enable="true" config-index="2">
			<config-item-value name="8M" value="0"></config-item-value>
			<config-item-value name="16M" value="1"></config-item-value>
			<description>
			</description>
		</config-item>	
		<config-item name="P00驱动" width="1" offset="6" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P00驱动选择</description>
		</config-item>	
		<config-item name="P01驱动" width="1" offset="7" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P01驱动选择</description>
		</config-item>	
		<config-item name="P02驱动" width="1" offset="8" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P02驱动选择</description>
		</config-item>	
		<config-item name="P03驱动" width="1" offset="9" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P03驱动选择</description>
		</config-item>	
		<config-item name="P04驱动" width="1" offset="10" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P04驱动选择</description>
		</config-item>	
		<config-item name="P05驱动" width="1" offset="11" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P05驱动选择</description>
		</config-item>	
		<config-item name="P06驱动" width="1" offset="12" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P06驱动选择</description>
		</config-item>	
		<config-item name="P07驱动" width="1" offset="13" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P07驱动选择</description>
		</config-item>	
		<config-item name="P40驱动" width="1" offset="4" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P40驱动选择</description>
		</config-item>		
		<config-item name="P41驱动" width="1" offset="5" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P41驱动选择</description>
		</config-item>				
		<config-item name="P51,P52驱动" width="1" offset="3" default-value="0" enable="true" config-index="1">
			<config-item-value name="10mA" value="0"></config-item-value>
			<config-item-value name="20mA" value="1"></config-item-value>
			<description>P51,P52驱动选择</description>
		</config-item>			
	</configs>
	
	
	<sfrs>
		<sfr mode="fpga">
			<reg name="A" addr="200" read-addr="8087" write-addr="8087" value-addr="200" addr-visiable="false" bank="-1"></reg>

			<reg name="L" addr="80" read-addr="80" write-addr="80" value-addr="80" addr-visiable="false" bank="0"></reg>
			<reg name="H" addr="81" read-addr="81" write-addr="81" value-addr="81" addr-visiable="false" bank="0"></reg>
			<reg name="R" addr="82" read-addr="82" write-addr="82" value-addr="82" addr-visiable="false" bank="0"></reg>
			<reg name="Z" addr="83" read-addr="83" write-addr="83" value-addr="83" addr-visiable="false" bank="0"></reg>
			<reg name="Y" addr="84" read-addr="84" write-addr="84" value-addr="84" addr-visiable="false" bank="0"></reg>
		
			<reg name="PFLAG" addr="86"  read-addr="86" write-addr="86" value-addr="86" addr-visiable="false" bank="0">
				<bit name="Z" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="C" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="LVDF24" offset="4"></bit>
				<bit name="LVDF36" offset="5"></bit>
				<bit name="PD" offset="6"></bit>
				<bit name="TO" offset="7"></bit>
			</reg>

			<reg name="RBANK" addr="87"  read-addr="87" write-addr="87" value-addr="87" addr-visiable="true" bank="0">
				<bit name="RBANKS0" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="LDOOUT" addr="A0"  read-addr="A0" write-addr="A0" value-addr="A0" addr-visiable="true" bank="0">
				<bit name="P53ANA" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="AINET3" addr="A1"  read-addr="A1" write-addr="A1" value-addr="A1" addr-visiable="true" bank="0">
				<bit name="AINET30" offset="0"></bit>
				<bit name="AINET31" offset="1"></bit>
				<bit name="AINET32" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="ADCLP" addr="A2"  read-addr="A2" write-addr="A2" value-addr="A2" addr-visiable="true" bank="0">
				<bit name="ADCLP0" offset="0"></bit>
				<bit name="ADCLP1" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="ADCCN3" addr="A3"  read-addr="A3" write-addr="A3" value-addr="A3" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="RDBH" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="ADCCN1" addr="A4"  read-addr="A4" write-addr="A4" value-addr="A4" addr-visiable="true" bank="0">
				<bit name="ADGN0" offset="0"></bit>
				<bit name="ADGN1" offset="1"></bit>
				<bit name="ADGN2" offset="2"></bit>
				<bit name="ENACM" offset="3"></bit>
				<bit name="ENTEMP" offset="4"></bit>
				<bit name="ENCHP" offset="5"></bit>
				<bit name="ADRST" offset="6"></bit>
				<bit name="ENADC" offset="7"></bit>
			</reg>

			<reg name="ADCCN2" addr="A5"  read-addr="A5" write-addr="A5" value-addr="A5" addr-visiable="true" bank="0">
				<bit name="DCSET0" offset="0"></bit>
				<bit name="DCSET1" offset="1"></bit>
				<bit name="DCSET2" offset="2"></bit>
				<bit name="VREGN" offset="3"></bit>
				<bit name="OSR0" offset="4"></bit>
				<bit name="OSR1" offset="5"></bit>
				<bit name="OSR2" offset="6"></bit>
				<bit name="OSR3" offset="7"></bit>
			</reg>

			<reg name="ADRESH" addr="A6" read-addr="A6" write-addr="A6" value-addr="A6" addr-visiable="true" bank="0"></reg>

			<reg name="AINET1" addr="A7"  read-addr="A7" write-addr="A7" value-addr="A7" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="INIS" offset="1"></bit>
				<bit name="INL0" offset="2"></bit>
				<bit name="INL1" offset="3"></bit>
				<bit name="INL2" offset="4"></bit>
				<bit name="INH0" offset="5"></bit>
				<bit name="INH1" offset="6"></bit>
				<bit name="INH2" offset="7"></bit>
			</reg>

			<reg name="AINET2" addr="A8"  read-addr="A8" write-addr="A8" value-addr="A8" addr-visiable="true" bank="0">
				<bit name="LVHSEN" offset="0"></bit>
				<bit name="VRL0" offset="1"></bit>
				<bit name="VRL1" offset="2"></bit>
				<bit name="INX0" offset="3"></bit>
				<bit name="INX1" offset="4"></bit>
				<bit name="VRH0" offset="5"></bit>
				<bit name="VRH1" offset="6"></bit>
				<bit name="ADPCONS1" offset="7"></bit>
			</reg>

			<reg name="ADRESM" addr="A9" read-addr="A9" write-addr="A9" value-addr="A9" addr-visiable="true" bank="0"></reg>
			<reg name="ADRESL" addr="AA" read-addr="AA" write-addr="AA" value-addr="AA" addr-visiable="true" bank="0"></reg>
			<reg name="ADCPCON" addr="AB" read-addr="AB" write-addr="AB" value-addr="AB" addr-visiable="true" bank="0"></reg>

			<reg name="PWRCN" addr="AC"  read-addr="AC" write-addr="AC" value-addr="AC" addr-visiable="true" bank="0">
				<bit name="DRCON530" offset="0"></bit>
				<bit name="DRCON531" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="VDDVX0" offset="4"></bit>
				<bit name="VDDVX1" offset="5"></bit>
				<bit name="VDDVX2" offset="6"></bit>
				<bit name="LDOEN" offset="7"></bit>
			</reg>

			<reg name="ADRBUF" addr="AD" read-addr="AD" write-addr="AD" value-addr="AD" addr-visiable="true" bank="0"></reg>

			<reg name="ADCCK" addr="AE"  read-addr="AE" write-addr="AE" value-addr="AE" addr-visiable="true" bank="0">
				<bit name="ADCCKS" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="ADCS0" offset="3"></bit>
				<bit name="ADCS1" offset="4"></bit>
				<bit name="ADCS2" offset="5"></bit>
				<bit name="DHS0" offset="6"></bit>
				<bit name="DHS1" offset="7"></bit>
			</reg>


			<reg name="P0W" addr="B0" read-addr="B0" write-addr="B0" value-addr="B0" addr-visiable="true" bank="0"></reg>
			<reg name="P4W" addr="B1" read-addr="B1" write-addr="B1" value-addr="B1" addr-visiable="true" bank="0"></reg>
			<reg name="P5W" addr="B2" read-addr="B2" write-addr="B2" value-addr="B2" addr-visiable="true" bank="0"></reg>
			
			<reg name="I2CCON1" addr="B3"  read-addr="B3" write-addr="B3" value-addr="B3" addr-visiable="true" bank="0">
				<bit name="RXAK" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="I2CCON" addr="B4"  read-addr="B4" write-addr="B4" value-addr="B4" addr-visiable="true" bank="0">
				<bit name="I2CEN" offset="0"></bit>
				<bit name="I2CPU" offset="1"></bit>
				<bit name="CKP" offset="2"></bit>
				<bit name="TXAK" offset="3"></bit>
				<bit name="SRW" offset="4"></bit>
				<bit name="HBB" offset="5"></bit>
				<bit name="HAAS" offset="6"></bit>
				<bit name="HCF" offset="7"></bit>
			</reg>

			<reg name="I2CADD" addr="B5" read-addr="B5" write-addr="B5" value-addr="B5" addr-visiable="true" bank="0"></reg>
			<reg name="I2CBUF" addr="B6" read-addr="B6" write-addr="B6" value-addr="B6" addr-visiable="true" bank="0"></reg>

			<reg name="I2CT0V" addr="B7"  read-addr="B7" write-addr="B7" value-addr="B7" addr-visiable="true" bank="0">
				<bit name="T0S0" offset="0"></bit>
				<bit name="T0S1" offset="1"></bit>
				<bit name="T0S2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="T0VF" offset="6"></bit>
				<bit name="T0VEN" offset="7"></bit>
			</reg>

			<reg name="P0M" addr="B8" read-addr="B8" write-addr="B8" value-addr="B8" addr-visiable="true" bank="0"></reg>
			<reg name="P4PD" addr="BC" read-addr="BC" write-addr="BC" value-addr="BC" addr-visiable="true" bank="0"></reg>

			<reg name="PEDGE" addr="BF"  read-addr="BF" write-addr="BF" value-addr="BF" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="PG0" offset="3"></bit>
				<bit name="PG1" offset="4"></bit>
				<bit name="INTSEL0" offset="5"></bit>
				<bit name="INTSEL1" offset="6"></bit>
				<bit name="INTSEL2" offset="7"></bit>
			</reg>

			<reg name="P4M" addr="C4" read-addr="C4" write-addr="C4" value-addr="C4" addr-visiable="true" bank="0"></reg>
			<reg name="P5M" addr="C5" read-addr="C5" write-addr="C5" value-addr="C5" addr-visiable="true" bank="0"></reg>

			<reg name="INTRQ" addr="C8"  read-addr="C8" write-addr="C8" value-addr="C8" addr-visiable="true" bank="0">
				<bit name="INT0IF" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="I2CIF" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TC0IF" offset="5"></bit>
				<bit name="TC1IF" offset="6"></bit>
				<bit name="ADCIF" offset="7"></bit>
			</reg>

			<reg name="INTEN" addr="C9"  read-addr="C9" write-addr="C9" value-addr="C9" addr-visiable="true" bank="0">
				<bit name="INT0IE" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="I2CIE" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TC0IE" offset="5"></bit>
				<bit name="TC1IE" offset="6"></bit>
				<bit name="ADCIE" offset="7"></bit>
			</reg>

			<reg name="OSCM" addr="CA" read-addr="CA" write-addr="CA" value-addr="CA" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="CLKMD" offset="2"></bit>
				<bit name="CPUM0" offset="3"></bit>
				<bit name="CPUM1" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="LECS32K" offset="7"></bit>
			</reg>

			<reg name="WDTC" addr="CB" read-addr="CB" write-addr="CB" value-addr="CB" addr-visiable="true" bank="0">
				<bit name="WDTS0" offset="0"></bit>
				<bit name="WDTS1" offset="1"></bit>
				<bit name="WDTS2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="LFS0" offset="4"></bit>
				<bit name="LFS1" offset="5"></bit>
				<bit name="LFS2" offset="6"></bit>
				<bit name="WDTEN" offset="7"></bit>
			</reg>

			<reg name="WDTR" addr="CC" read-addr="CC" write-addr="CC" value-addr="CC" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R" addr="CD" read-addr="CD" write-addr="CD" value-addr="CD" addr-visiable="true" bank="0"></reg>
			<reg name="PCL" addr="CE" read-addr="CE" write-addr="CE" value-addr="CE" addr-visiable="true" bank="0"></reg>
			<reg name="PCH" addr="CF" read-addr="CF" write-addr="CF" value-addr="CF" addr-visiable="true" bank="0"></reg>

			<reg name="P0" addr="D0" read-addr="D0" write-addr="D0" value-addr="D0" addr-visiable="true" bank="0"></reg>
			<reg name="P4" addr="D4" read-addr="D4" write-addr="D4" value-addr="D4" addr-visiable="true" bank="0"></reg>
			<reg name="P5" addr="D5" read-addr="D5" write-addr="D5" value-addr="D5" addr-visiable="true" bank="0"></reg>

			<reg name="T0M" addr="D8" read-addr="D8" write-addr="D8" value-addr="D8" addr-visiable="true" bank="0">
				<bit name="TC1GN" offset="0"></bit>
				<bit name="TC0GN" offset="1"></bit>
				<bit name="TC0X8" offset="2"></bit>
				<bit name="TC1X8" offset="3"></bit>
				<bit name="TC0S16" offset="4"></bit>
				<bit name="TC1S16" offset="5"></bit>
				<bit name="LRCEN" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="PWMCON" addr="D9" read-addr="D9" write-addr="D9" value-addr="D9" addr-visiable="true" bank="0">
				<bit name="PWM1EN" offset="0"></bit>
				<bit name="PWM2EN" offset="1"></bit>
				<bit name="PWM1PSEL" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="PWM1OSEL" offset="4"></bit>
				<bit name="PWM2OSEL" offset="5"></bit>
				<bit name="PWM0OSEL" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="TC0M" addr="DA" read-addr="DA" write-addr="DA" value-addr="DA" addr-visiable="true" bank="0">
				<bit name="PWM0EN" offset="0"></bit>
				<bit name="TCOUT" offset="1"></bit>
				<bit name="ALOAD0" offset="2"></bit>
				<bit name="T0CKS" offset="3"></bit>
				<bit name="TPS0" offset="4"></bit>
				<bit name="TPS1" offset="5"></bit>
				<bit name="TPS2" offset="6"></bit>
				<bit name="TR0" offset="7"></bit>
			</reg>

			<reg name="TC0C" addr="DB" read-addr="DB" write-addr="DB" value-addr="DB" addr-visiable="true" bank="0"></reg>

			<reg name="TC1M" addr="DC" read-addr="DC" write-addr="DC" value-addr="DC" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="ALOAD1" offset="2"></bit>
				<bit name="T1CKS" offset="3"></bit>
				<bit name="TP1S0" offset="4"></bit>
				<bit name="TP1S1" offset="5"></bit>
				<bit name="TP1S2" offset="6"></bit>
				<bit name="TR1" offset="7"></bit>
			</reg>

			<reg name="TC1C" addr="DD" read-addr="DD" write-addr="DD" value-addr="DD" addr-visiable="true" bank="0"></reg>
			<reg name="TC1R" addr="DE" read-addr="DE" write-addr="DE" value-addr="DE" addr-visiable="true" bank="0"></reg>

			<reg name="STKP" addr="DF" read-addr="DF" write-addr="DF" value-addr="DF" addr-visiable="true" bank="0">
				<bit name="STKPB0" offset="0"></bit>
				<bit name="STKPB1" offset="1"></bit>
				<bit name="STKPB2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>

			<reg name="P0UR" addr="E0" read-addr="E0" write-addr="E0" value-addr="E0" addr-visiable="true" bank="0"></reg>
			<reg name="P4UR" addr="E4" read-addr="E4" write-addr="E4" value-addr="E4" addr-visiable="true" bank="0"></reg>
			<reg name="P5UR" addr="E5" read-addr="E5" write-addr="E5" value-addr="E5" addr-visiable="true" bank="0"></reg>

			<reg name="@YZ" addr="E7" read-addr="E7" write-addr="E7" value-addr="E7" addr-visiable="true" bank="0"></reg>
			<reg name="PWM2CON" addr="E8" read-addr="E8" write-addr="E8" value-addr="E8" addr-visiable="true" bank="0"></reg>

			<reg name="TC0R0" addr="E9" read-addr="E9" write-addr="E9" value-addr="E9" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R1" addr="EA" read-addr="EA" write-addr="EA" value-addr="EA" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R2" addr="EB" read-addr="EB" write-addr="EB" value-addr="EB" addr-visiable="true" bank="0"></reg>


			<reg name="STK7L" addr="F0" read-addr="F0" write-addr="F0" value-addr="F0" addr-visiable="true" bank="0"></reg>
			<reg name="STK7H" addr="F1" read-addr="F1" write-addr="F1" value-addr="F1" addr-visiable="true" bank="0"></reg>
			<reg name="STK6L" addr="F2" read-addr="F2" write-addr="F2" value-addr="F2" addr-visiable="true" bank="0"></reg>
			<reg name="STK6H" addr="F3" read-addr="F3" write-addr="F3" value-addr="F3" addr-visiable="true" bank="0"></reg>
			<reg name="STK5L" addr="F4" read-addr="F4" write-addr="F4" value-addr="F4" addr-visiable="true" bank="0"></reg>
			<reg name="STK5H" addr="F5" read-addr="F5" write-addr="F5" value-addr="F5" addr-visiable="true" bank="0"></reg>
			<reg name="STK4L" addr="F6" read-addr="F6" write-addr="F6" value-addr="F6" addr-visiable="true" bank="0"></reg>
			<reg name="STK4H" addr="F7" read-addr="F7" write-addr="F7" value-addr="F7" addr-visiable="true" bank="0"></reg>
			<reg name="STK3L" addr="F8" read-addr="F8" write-addr="F8" value-addr="F8" addr-visiable="true" bank="0"></reg>
			<reg name="STK3H" addr="F9" read-addr="F9" write-addr="F9" value-addr="F9" addr-visiable="true" bank="0"></reg>
			<reg name="STK2L" addr="FA" read-addr="FA" write-addr="FA" value-addr="FA" addr-visiable="true" bank="0"></reg>
			<reg name="STK2H" addr="FB" read-addr="FB" write-addr="FB" value-addr="FB" addr-visiable="true" bank="0"></reg>
			<reg name="STK1L" addr="FC" read-addr="FC" write-addr="FC" value-addr="FC" addr-visiable="true" bank="0"></reg>
			<reg name="STK1H" addr="FD" read-addr="FD" write-addr="FD" value-addr="FD" addr-visiable="true" bank="0"></reg>
			<reg name="STK0L" addr="FE" read-addr="FE" write-addr="FE" value-addr="FE" addr-visiable="true" bank="0"></reg>
			<reg name="STK0H" addr="FF" read-addr="FF" write-addr="FF" value-addr="FF" addr-visiable="true" bank="0"></reg>
		</sfr>	
		<sfr mode="ic">
			<reg name="A" addr="200" read-addr="0ff0" write-addr="0ff0" value-addr="200" addr-visiable="false" bank="-1"></reg>

			<reg name="L" addr="80" read-addr="80" write-addr="80" value-addr="80" addr-visiable="false" bank="0"></reg>
			<reg name="H" addr="81" read-addr="81" write-addr="81" value-addr="81" addr-visiable="false" bank="0"></reg>
			<reg name="R" addr="82" read-addr="82" write-addr="82" value-addr="82" addr-visiable="false" bank="0"></reg>
			<reg name="Z" addr="83" read-addr="83" write-addr="83" value-addr="83" addr-visiable="false" bank="0"></reg>
			<reg name="Y" addr="84" read-addr="84" write-addr="84" value-addr="84" addr-visiable="false" bank="0"></reg>
		
			<reg name="PFLAG" addr="86"  read-addr="86" write-addr="86" value-addr="86" addr-visiable="false" bank="0">
				<bit name="Z" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="C" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="LVDF24" offset="4"></bit>
				<bit name="LVDF36" offset="5"></bit>
				<bit name="PD" offset="6"></bit>
				<bit name="TO" offset="7"></bit>
			</reg>

			<reg name="RBANK" addr="87"  read-addr="87" write-addr="87" value-addr="87" addr-visiable="true" bank="0">
				<bit name="RBANKS0" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="LDOOUT" addr="A0"  read-addr="A0" write-addr="A0" value-addr="A0" addr-visiable="true" bank="0">
				<bit name="P53ANA" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="AINET3" addr="A1"  read-addr="A1" write-addr="A1" value-addr="A1" addr-visiable="true" bank="0">
				<bit name="AINET30" offset="0"></bit>
				<bit name="AINET31" offset="1"></bit>
				<bit name="AINET32" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="ADCLP" addr="A2"  read-addr="A2" write-addr="A2" value-addr="A2" addr-visiable="true" bank="0">
				<bit name="ADCLP0" offset="0"></bit>
				<bit name="ADCLP1" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="ADCCN3" addr="A3"  read-addr="A3" write-addr="A3" value-addr="A3" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="RDBH" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="ADCCN1" addr="A4"  read-addr="A4" write-addr="A4" value-addr="A4" addr-visiable="true" bank="0">
				<bit name="ADGN0" offset="0"></bit>
				<bit name="ADGN1" offset="1"></bit>
				<bit name="ADGN2" offset="2"></bit>
				<bit name="ENACM" offset="3"></bit>
				<bit name="ENTEMP" offset="4"></bit>
				<bit name="ENCHP" offset="5"></bit>
				<bit name="ADRST" offset="6"></bit>
				<bit name="ENADC" offset="7"></bit>
			</reg>

			<reg name="ADCCN2" addr="A5"  read-addr="A5" write-addr="A5" value-addr="A5" addr-visiable="true" bank="0">
				<bit name="DCSET0" offset="0"></bit>
				<bit name="DCSET1" offset="1"></bit>
				<bit name="DCSET2" offset="2"></bit>
				<bit name="VREGN" offset="3"></bit>
				<bit name="OSR0" offset="4"></bit>
				<bit name="OSR1" offset="5"></bit>
				<bit name="OSR2" offset="6"></bit>
				<bit name="OSR3" offset="7"></bit>
			</reg>

			<reg name="ADRESH" addr="A6" read-addr="A6" write-addr="A6" value-addr="A6" addr-visiable="true" bank="0"></reg>

			<reg name="AINET1" addr="A7"  read-addr="A7" write-addr="A7" value-addr="A7" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="INIS" offset="1"></bit>
				<bit name="INL0" offset="2"></bit>
				<bit name="INL1" offset="3"></bit>
				<bit name="INL2" offset="4"></bit>
				<bit name="INH0" offset="5"></bit>
				<bit name="INH1" offset="6"></bit>
				<bit name="INH2" offset="7"></bit>
			</reg>

			<reg name="AINET2" addr="A8"  read-addr="A8" write-addr="A8" value-addr="A8" addr-visiable="true" bank="0">
				<bit name="LVHSEN" offset="0"></bit>
				<bit name="VRL0" offset="1"></bit>
				<bit name="VRL1" offset="2"></bit>
				<bit name="INX0" offset="3"></bit>
				<bit name="INX1" offset="4"></bit>
				<bit name="VRH0" offset="5"></bit>
				<bit name="VRH1" offset="6"></bit>
				<bit name="ADPCONS1" offset="7"></bit>
			</reg>

			<reg name="ADRESM" addr="A9" read-addr="A9" write-addr="A9" value-addr="A9" addr-visiable="true" bank="0"></reg>
			<reg name="ADRESL" addr="AA" read-addr="AA" write-addr="AA" value-addr="AA" addr-visiable="true" bank="0"></reg>
			<reg name="ADCPCON" addr="AB" read-addr="AB" write-addr="AB" value-addr="AB" addr-visiable="true" bank="0"></reg>

			<reg name="PWRCN" addr="AC"  read-addr="AC" write-addr="AC" value-addr="AC" addr-visiable="true" bank="0">
				<bit name="DRCON530" offset="0"></bit>
				<bit name="DRCON531" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="VDDVX0" offset="4"></bit>
				<bit name="VDDVX1" offset="5"></bit>
				<bit name="VDDVX2" offset="6"></bit>
				<bit name="LDOEN" offset="7"></bit>
			</reg>

			<reg name="ADRBUF" addr="AD" read-addr="AD" write-addr="AD" value-addr="AD" addr-visiable="true" bank="0"></reg>

			<reg name="ADCCK" addr="AE"  read-addr="AE" write-addr="AE" value-addr="AE" addr-visiable="true" bank="0">
				<bit name="ADCCKS" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="ADCS0" offset="3"></bit>
				<bit name="ADCS1" offset="4"></bit>
				<bit name="ADCS2" offset="5"></bit>
				<bit name="DHS0" offset="6"></bit>
				<bit name="DHS1" offset="7"></bit>
			</reg>


			<reg name="P0W" addr="B0" read-addr="B0" write-addr="B0" value-addr="B0" addr-visiable="true" bank="0"></reg>
			<reg name="P4W" addr="B1" read-addr="B1" write-addr="B1" value-addr="B1" addr-visiable="true" bank="0"></reg>
			<reg name="P5W" addr="B2" read-addr="B2" write-addr="B2" value-addr="B2" addr-visiable="true" bank="0"></reg>
			
			<reg name="I2CCON1" addr="B3"  read-addr="B3" write-addr="B3" value-addr="B3" addr-visiable="true" bank="0">
				<bit name="RXAK" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="I2CCON" addr="B4"  read-addr="B4" write-addr="B4" value-addr="B4" addr-visiable="true" bank="0">
				<bit name="I2CEN" offset="0"></bit>
				<bit name="I2CPU" offset="1"></bit>
				<bit name="CKP" offset="2"></bit>
				<bit name="TXAK" offset="3"></bit>
				<bit name="SRW" offset="4"></bit>
				<bit name="HBB" offset="5"></bit>
				<bit name="HAAS" offset="6"></bit>
				<bit name="HCF" offset="7"></bit>
			</reg>

			<reg name="I2CADD" addr="B5" read-addr="B5" write-addr="B5" value-addr="B5" addr-visiable="true" bank="0"></reg>
			<reg name="I2CBUF" addr="B6" read-addr="B6" write-addr="B6" value-addr="B6" addr-visiable="true" bank="0"></reg>

			<reg name="I2CT0V" addr="B7"  read-addr="B7" write-addr="B7" value-addr="B7" addr-visiable="true" bank="0">
				<bit name="T0S0" offset="0"></bit>
				<bit name="T0S1" offset="1"></bit>
				<bit name="T0S2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="T0VF" offset="6"></bit>
				<bit name="T0VEN" offset="7"></bit>
			</reg>

			<reg name="P0M" addr="B8" read-addr="B8" write-addr="B8" value-addr="B8" addr-visiable="true" bank="0"></reg>
			<reg name="P4PD" addr="BC" read-addr="BC" write-addr="BC" value-addr="BC" addr-visiable="true" bank="0"></reg>

			<reg name="PEDGE" addr="BF"  read-addr="BF" write-addr="BF" value-addr="BF" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="PG0" offset="3"></bit>
				<bit name="PG1" offset="4"></bit>
				<bit name="INTSEL0" offset="5"></bit>
				<bit name="INTSEL1" offset="6"></bit>
				<bit name="INTSEL2" offset="7"></bit>
			</reg>

			<reg name="P4M" addr="C4" read-addr="C4" write-addr="C4" value-addr="C4" addr-visiable="true" bank="0"></reg>
			<reg name="P5M" addr="C5" read-addr="C5" write-addr="C5" value-addr="C5" addr-visiable="true" bank="0"></reg>

			<reg name="INTRQ" addr="C8"  read-addr="C8" write-addr="C8" value-addr="C8" addr-visiable="true" bank="0">
				<bit name="INT0IF" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="I2CIF" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TC0IF" offset="5"></bit>
				<bit name="TC1IF" offset="6"></bit>
				<bit name="ADCIF" offset="7"></bit>
			</reg>

			<reg name="INTEN" addr="C9"  read-addr="C9" write-addr="C9" value-addr="C9" addr-visiable="true" bank="0">
				<bit name="INT0IE" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="I2CIE" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="TC0IE" offset="5"></bit>
				<bit name="TC1IE" offset="6"></bit>
				<bit name="ADCIE" offset="7"></bit>
			</reg>

			<reg name="OSCM" addr="CA" read-addr="CA" write-addr="CA" value-addr="CA" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="CLKMD" offset="2"></bit>
				<bit name="CPUM0" offset="3"></bit>
				<bit name="CPUM1" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="LECS32K" offset="7"></bit>
			</reg>

			<reg name="WDTC" addr="CB" read-addr="CB" write-addr="CB" value-addr="CB" addr-visiable="true" bank="0">
				<bit name="WDTS0" offset="0"></bit>
				<bit name="WDTS1" offset="1"></bit>
				<bit name="WDTS2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="LFS0" offset="4"></bit>
				<bit name="LFS1" offset="5"></bit>
				<bit name="LFS2" offset="6"></bit>
				<bit name="WDTEN" offset="7"></bit>
			</reg>

			<reg name="WDTR" addr="CC" read-addr="CC" write-addr="CC" value-addr="CC" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R" addr="CD" read-addr="CD" write-addr="CD" value-addr="CD" addr-visiable="true" bank="0"></reg>
			<reg name="PCL" addr="CE" read-addr="CE" write-addr="CE" value-addr="CE" addr-visiable="true" bank="0"></reg>
			<reg name="PCH" addr="CF" read-addr="CF" write-addr="CF" value-addr="CF" addr-visiable="true" bank="0"></reg>

			<reg name="P0" addr="D0" read-addr="D0" write-addr="D0" value-addr="D0" addr-visiable="true" bank="0"></reg>
			<reg name="P4" addr="D4" read-addr="D4" write-addr="D4" value-addr="D4" addr-visiable="true" bank="0"></reg>
			<reg name="P5" addr="D5" read-addr="D5" write-addr="D5" value-addr="D5" addr-visiable="true" bank="0"></reg>

			<reg name="T0M" addr="D8" read-addr="D8" write-addr="D8" value-addr="D8" addr-visiable="true" bank="0">
				<bit name="TC1GN" offset="0"></bit>
				<bit name="TC0GN" offset="1"></bit>
				<bit name="TC0X8" offset="2"></bit>
				<bit name="TC1X8" offset="3"></bit>
				<bit name="TC0S16" offset="4"></bit>
				<bit name="TC1S16" offset="5"></bit>
				<bit name="LRCEN" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="PWMCON" addr="D9" read-addr="D9" write-addr="D9" value-addr="D9" addr-visiable="true" bank="0">
				<bit name="PWM1EN" offset="0"></bit>
				<bit name="PWM2EN" offset="1"></bit>
				<bit name="PWM1PSEL" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="PWM1OSEL" offset="4"></bit>
				<bit name="PWM2OSEL" offset="5"></bit>
				<bit name="PWM0OSEL" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>

			<reg name="TC0M" addr="DA" read-addr="DA" write-addr="DA" value-addr="DA" addr-visiable="true" bank="0">
				<bit name="PWM0EN" offset="0"></bit>
				<bit name="TCOUT" offset="1"></bit>
				<bit name="ALOAD0" offset="2"></bit>
				<bit name="T0CKS" offset="3"></bit>
				<bit name="TPS0" offset="4"></bit>
				<bit name="TPS1" offset="5"></bit>
				<bit name="TPS2" offset="6"></bit>
				<bit name="TR0" offset="7"></bit>
			</reg>

			<reg name="TC0C" addr="DB" read-addr="DB" write-addr="DB" value-addr="DB" addr-visiable="true" bank="0"></reg>

			<reg name="TC1M" addr="DC" read-addr="DC" write-addr="DC" value-addr="DC" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="ALOAD1" offset="2"></bit>
				<bit name="T1CKS" offset="3"></bit>
				<bit name="TP1S0" offset="4"></bit>
				<bit name="TP1S1" offset="5"></bit>
				<bit name="TP1S2" offset="6"></bit>
				<bit name="TR1" offset="7"></bit>
			</reg>

			<reg name="TC1C" addr="DD" read-addr="DD" write-addr="DD" value-addr="DD" addr-visiable="true" bank="0"></reg>
			<reg name="TC1R" addr="DE" read-addr="DE" write-addr="DE" value-addr="DE" addr-visiable="true" bank="0"></reg>

			<reg name="STKP" addr="DF" read-addr="DF" write-addr="DF" value-addr="DF" addr-visiable="true" bank="0">
				<bit name="STKPB0" offset="0"></bit>
				<bit name="STKPB1" offset="1"></bit>
				<bit name="STKPB2" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>

			<reg name="P0UR" addr="E0" read-addr="E0" write-addr="E0" value-addr="E0" addr-visiable="true" bank="0"></reg>
			<reg name="P4UR" addr="E4" read-addr="E4" write-addr="E4" value-addr="E4" addr-visiable="true" bank="0"></reg>
			<reg name="P5UR" addr="E5" read-addr="E5" write-addr="E5" value-addr="E5" addr-visiable="true" bank="0"></reg>

			<reg name="@YZ" addr="E7" read-addr="E7" write-addr="E7" value-addr="E7" addr-visiable="true" bank="0"></reg>
			<reg name="PWM2CON" addr="E8" read-addr="E8" write-addr="E8" value-addr="E8" addr-visiable="true" bank="0"></reg>

			<reg name="TC0R0" addr="E9" read-addr="E9" write-addr="E9" value-addr="E9" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R1" addr="EA" read-addr="EA" write-addr="EA" value-addr="EA" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R2" addr="EB" read-addr="EB" write-addr="EB" value-addr="EB" addr-visiable="true" bank="0"></reg>


			<reg name="STK7L" addr="F0" read-addr="F0" write-addr="F0" value-addr="F0" addr-visiable="true" bank="0"></reg>
			<reg name="STK7H" addr="F1" read-addr="F1" write-addr="F1" value-addr="F1" addr-visiable="true" bank="0"></reg>
			<reg name="STK6L" addr="F2" read-addr="F2" write-addr="F2" value-addr="F2" addr-visiable="true" bank="0"></reg>
			<reg name="STK6H" addr="F3" read-addr="F3" write-addr="F3" value-addr="F3" addr-visiable="true" bank="0"></reg>
			<reg name="STK5L" addr="F4" read-addr="F4" write-addr="F4" value-addr="F4" addr-visiable="true" bank="0"></reg>
			<reg name="STK5H" addr="F5" read-addr="F5" write-addr="F5" value-addr="F5" addr-visiable="true" bank="0"></reg>
			<reg name="STK4L" addr="F6" read-addr="F6" write-addr="F6" value-addr="F6" addr-visiable="true" bank="0"></reg>
			<reg name="STK4H" addr="F7" read-addr="F7" write-addr="F7" value-addr="F7" addr-visiable="true" bank="0"></reg>
			<reg name="STK3L" addr="F8" read-addr="F8" write-addr="F8" value-addr="F8" addr-visiable="true" bank="0"></reg>
			<reg name="STK3H" addr="F9" read-addr="F9" write-addr="F9" value-addr="F9" addr-visiable="true" bank="0"></reg>
			<reg name="STK2L" addr="FA" read-addr="FA" write-addr="FA" value-addr="FA" addr-visiable="true" bank="0"></reg>
			<reg name="STK2H" addr="FB" read-addr="FB" write-addr="FB" value-addr="FB" addr-visiable="true" bank="0"></reg>
			<reg name="STK1L" addr="FC" read-addr="FC" write-addr="FC" value-addr="FC" addr-visiable="true" bank="0"></reg>
			<reg name="STK1H" addr="FD" read-addr="FD" write-addr="FD" value-addr="FD" addr-visiable="true" bank="0"></reg>
			<reg name="STK0L" addr="FE" read-addr="FE" write-addr="FE" value-addr="FE" addr-visiable="true" bank="0"></reg>
			<reg name="STK0H" addr="FF" read-addr="FF" write-addr="FF" value-addr="FF" addr-visiable="true" bank="0"></reg>
		</sfr>			
	</sfrs>
	<insts>
		<inst name="call" value="c000" mask-value="c000"/>
		<inst name="return" value="0e00" mask-value="ffff"/>
		<inst name="return" value="0f00" mask-value="ffff"/>
	</insts>
	<compilers>
		<compiler>	
			<compiler-item type="c" name="cc2" command-path="$(DevEnvDir)\cc2.exe">
				<option>-chip-name $(ChipName) -chip-ver $(ChipVer) -chip-id $(ChipID) -file-ver $(CCSFileVer) -rom-size $(UserRomSize) -debug false -c h1 -clean-ram false -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -config "$(ConfigWord)" -lib "$GetFiles('.lib',';')"  -inc-dir "$GetFolders(';')" -src-files "$GetFiles('.c',';')" -inc-files "$GetFiles('.h;.inc',';')"</option>
				<action-before-compile>
				</action-before-compile> 
				<action-after-compile >
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="asm" name="ac0" command-path="$(DevEnvDir)\ac0.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -ram-start $(RamStartAddr) -ram-size $(RamSize) -reset-addr $(ResetAddr) -inst-set INST_SET_2711 -otp-body-size $(OtpBodySize) -debug false -symbol-file true  -listfile true -workdir "$(ProjectDir)" -include-path "$GetFolders(';')" -file "$(EntryFile)" -output "$(OutDir)" -project-name "$(ProjectName)" -config "$(ConfigWord)"</option>
				<action-before-compile>
				</action-before-compile>
				<action-after-compile>
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="c" name="cc2" out-type="lib" command-path="$(DevEnvDir)\cc2.exe">
				<option>-chip-name $(ChipName) -chip-ver $(ChipVer) -chip-id $(ChipID) -file-ver $(CCSFileVer) -rom-size $(UserRomSize) -debug false  -c h1 -clean-ram false -prj-name "$(ProjectName)"  -out-type $(ProjectType) -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -config "$(ConfigWord)" -lib "$GetFiles('.lib',';')"  -inc-dir "$GetFolders(';')" -src-files "$GetFiles('.c',';')" -inc-files "$GetFiles('.h;.inc',';')"</option>
			</compiler-item>			
		</compiler>	
	</compilers>
	<debugers>
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>snc</debuger-c>
			<device type="1" version="0">
				<simulator type="1" version="0" code-first="true" config-item="true" config-item-id="11">
					<ram-mode>fpga</ram-mode>
					<sfr-mode>fpga</sfr-mode>
					<pc-addr pcl="CE" pch="CF" />
					<config-word-addr>800</config-word-addr>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>
		</debuger>
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>snc</debuger-c>
			<device type="10" version="0">
				<simulator type="10" version="0" code-first="true" config-item="false" config-item-id="-1">
					<pc-addr pcl="CE" pch="CF" />
					<ram-mode>ic</ram-mode>
					<sfr-mode>ic</sfr-mode>	
					<config-word-addr>800</config-word-addr>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>
		</debuger>		
	</debugers>
	<editor-language>
		<c-lang name="c2-lang"/>
		<asm-lang name="asm3-lang"/>
	</editor-language>	
</chip>