//****************************************************
//Copyright(c) 2021   苏州华芯微电子股份有限公司  	 *
//文件名称:HS26F2728S                                *
//文件标志:HS26F2728S.h		                         *
//摘    要:TkLib	   			                     *
//				                                     *
//当前版本: Lowpower_V1                              *
//作    者:	LvbuWei	                                 *
//完成日期:	20211021                                 *
//****************************************************
        
/****************************************************************'*/
#ifndef __HS26F2728S__H
#define __HS26F2728S__H


/* bank0 function <<==================================================*/
sfr	L       = 0x80;
sfr	H       = 0x81;
sfr	R       = 0x82;
sfr	Z       = 0x83;

sfr	Y       = 0x84;
sfr	X       = 0x85;

sfr	PFLAG   = 0x86;
    sbit	FZ          = 0x86:0;	
    sbit	FDC         = 0x86:1;	
    sbit	FC          = 0x86:2;	
	
    sbit	FNPD        = 0x86:6;
    sbit	FNTO        = 0x86:7;
    
sfr	RBANK   = 0x87;
    sbit	FRBANKS     = 0x87:0;
	
    sbit	FSBANKS1    = 0x87:6;
    sbit	FSBANKS2    = 0x87:7;
    
/* bank0 function <<==================================================*/
sfr	W0      = 0x88;
sfr	W1      = 0x89;
sfr	W2      = 0x8a;
sfr	W3      = 0x8b;

sfr	W4      = 0x8c;
sfr	W5      = 0x8d;
sfr	W6      = 0x8e;
sfr	W7      = 0x8f;

/* bank0 function <<==================================================*/
sfr	_HL     = 0x90;
sfr	_YZ     = 0x91;

sfr	PCL     = 0x93;
sfr	PCH     = 0x94;

sfr	OSCM    = 0x95;
    sbit	F8M32KSEL   = 0x95:0;
    sbit	FSTPHX      = 0x95:1;
    sbit	FCLKMD      = 0x95:2;
    sbit	FCPUM0      = 0x95:3;
	
    sbit	FCPUM1      = 0x95:4;
    sbit	FLRCSXT     = 0x95:6;
    sbit	FLRCS32K    = 0x95:7;
    
sfr	WDTR    = 0x96;

sfr	INTRQ0  = 0x97;
    sbit	FINT0IF     = 0x97:0;
    sbit	FINT1IF     = 0x97:1;
    sbit	FINT2IF     = 0x97:2;
    sbit	FADCIF      = 0x97:3;
	
    sbit	FT0IF       = 0x97:4;
    sbit	FTC0IF      = 0x97:5;
    sbit	FT2IF       = 0x97:6;
    sbit	FPBIF       = 0x97:7;
    
/* bank0 function <<==================================================*/
sfr	INTRQ1  = 0x98;
    sbit	FTM1IF      = 0x98:0;
    sbit	FTM2IF      = 0x98:1;
    //sbit	ADC24IF     = 0x98:2;	
    sbit	FTM3IF    = 0x98:3;	
	
    sbit	FCMPIF      = 0x98:4;
    sbit	FI2CIF      = 0x98:6;
    sbit	FSPIIF      = 0x98:7;
    
sfr	INTEN0  = 0x99;
    sbit	FINT0IE     = 0x99:0;
    sbit	FINT1IE     = 0x99:1;
    sbit	FINT2IE     = 0x99:2;
    sbit	FADCIE      = 0x99:3;
	
    sbit	FT0IE       = 0x99:4;
    sbit	FTC0IE      = 0x99:5;
    sbit	FT2IE       = 0x99:6;
    sbit	FPBIE       = 0x99:7;
    
sfr	INTEN1  = 0x9A;
    sbit	FTM1IE      = 0x9A:0;
    sbit	FTM2IE      = 0x9A:1;
    //sbit	ADC24IE     = 0x9A:2;	
    sbit	FTM3IE    = 0x9A:3;	
	
    sbit	FCMPIE      = 0x9A:4;
    sbit	FI2CIE      = 0x9A:6;
    sbit	FSPIIE      = 0x9A:7;
    
sfr	P0W     = 0x9B;
    sbit	FP07W       = 0x9b:7;	
    sbit	FP06W       = 0x9b:6;
    sbit	FP05W       = 0x9b:5;
    sbit	FP04W       = 0x9b:4;
	
    sbit	FP03W       = 0x9b:3;
    sbit	FP02W       = 0x9b:2;
    sbit	FP01W       = 0x9b:1;
    sbit	FP00W       = 0x9b:0;
    
sfr	P1W     = 0x9C;
    sbit	FP17W       = 0x9c:7;	
    sbit	FP16W       = 0x9c:6;	
    sbit	FP15W       = 0x9c:5;	
    sbit	FP14W       = 0x9c:4;	
	
    sbit	FP13W       = 0x9c:3;	
    sbit	FP12W       = 0x9c:2;
    sbit	FP11W       = 0x9c:1;
    sbit	FP10W       = 0x9c:0;
    
sfr	P2W     = 0x9D;
    sbit	FP27W       = 0x9d:7;	
    sbit	FP26W       = 0x9d:6;	
    sbit	FP25W       = 0x9d:5;	
    sbit	FP24W       = 0x9d:4;	
	
    sbit	FP23W       = 0x9d:3;	
    sbit	FP22W       = 0x9d:2;	
    sbit	FP21W       = 0x9d:1;	
    sbit	FP20W       = 0x9d:0;	

sfr	P4W     = 0x9E;
    sbit	FP47W       = 0x9e:7;
    sbit	FP46W       = 0x9e:6;
    sbit	FP45W       = 0x9e:5;
    sbit	FP44W       = 0x9e:4;
	
    sbit	FP43W       = 0x9e:3;
    sbit	FP42W       = 0x9e:2;
    sbit	FP41W       = 0x9e:1;
    sbit	FP40W       = 0x9e:0;
    
sfr	PEDGE   = 0x9F;
    sbit	FPG0        = 0x9f:0;
    sbit	FPG1        = 0x9f:1;
    
/* bank0 function <<==================================================*/
sfr	P0M     = 0xA0;
    sbit	FP00M       = 0xa0:0;
    sbit	FP01M       = 0xa0:1;
    sbit	FP02M       = 0xa0:2;
    sbit	FP03M       = 0xa0:3;
	
    sbit	FP04M       = 0xa0:4;
    sbit	FP05M       = 0xa0:5;
    sbit	FP06M       = 0xa0:6;
    sbit	FP07M       = 0xa0:7;	
    
sfr	P1M     = 0xA1;
    sbit	FP10M       = 0xa1:0;
    sbit	FP11M       = 0xa1:1;
    sbit	FP12M       = 0xa1:2;
    sbit	FP13M       = 0xa1:3;
    
    sbit	FP14M       = 0xa1:4;
    sbit	FP15M       = 0xa1:5;
    sbit	FP16M       = 0xa1:6;
    sbit	FP17M       = 0xa1:7;
    
sfr	P2M     = 0xA2;
    sbit	FP20M       = 0xa2:0;	
    sbit	FP21M       = 0xa2:1;	
    sbit	FP22M       = 0xa2:2;	
    sbit	FP23M       = 0xa2:3;	
    
    sbit	FP24M       = 0xA2:4;	
    sbit	FP25M       = 0xA2:5;	
    sbit	FP26M       = 0xA2:6;	
    sbit	FP27M       = 0xA2:7;	

sfr	P4M     = 0xA3;
    sbit	FP40M       = 0xa3:0;
    sbit	FP41M       = 0xa3:1;
    sbit	FP42M       = 0xa3:2;
    sbit	FP43M       = 0xa3:3;
	
    sbit	FP44M       = 0xa3:4;
    sbit	FP45M       = 0xa3:5;
    sbit	FP46M       = 0xa3:6;
    sbit	FP47M       = 0xa3:7;

sfr	P5M     = 0xa4;	//1348
    sbit	FP50M       = 0xa4:0;	//1348
    sbit	FP51M       = 0xa4:1;	//1348
    sbit	FP52M       = 0xa4:2;	//1348
    sbit	FP53M       = 0xa4:3;	//1348
    
    sbit	FP54M       = 0xa4:4;	//1348
    sbit	FP55M       = 0xa4:5;	//1348
    sbit	FP56M       = 0xa4:6;	//1348
    sbit	FP57M       = 0xa4:7;	//1348

sfr	P0      = 0xA5;
    sbit	FP00        = 0xa5:0;
    sbit	FP01        = 0xa5:1;
    sbit	FP02        = 0xa5:2;
    sbit	FP03        = 0xa5:3;
	
    sbit	FP04        = 0xa5:4;
    sbit	FP05        = 0xa5:5;
    sbit	FP06        = 0xa5:6;
    sbit	FP07        = 0xa5:7;
    
sfr	P1      = 0xA6;
    sbit	FP10        = 0xa6:0;
    sbit	FP11        = 0xa6:1;
    sbit	FP12        = 0xa6:2;
    sbit	FP13        = 0xa6:3;	
    
    sbit	FP14        = 0xa6:4;	
    sbit	FP15        = 0xa6:5;	
    sbit	FP16        = 0xa6:6;	
    sbit	FP17        = 0xa6:7;	

sfr	P2     	= 0xA7;
    sbit	FP20        = 0xa7:0;	
    sbit	FP21        = 0xa7:1;	
    sbit	FP22        = 0xa7:2;	
    sbit	FP23        = 0xa7:3;	
    
    sbit	FP24        = 0xa7:4;	
    sbit	FP25        = 0xa7:5;	
    sbit	FP26        = 0xa7:6;	
    sbit	FP27        = 0xa7:7;	

/* bank0 function <<==================================================*/
sfr	P4      = 0xA8;
    sbit	FP40        = 0xa8:0;
    sbit	FP41        = 0xa8:1;
    sbit	FP42        = 0xa8:2;
    sbit	FP43        = 0xa8:3;
	
    sbit	FP44        = 0xa8:4;
    sbit	FP45        = 0xa8:5;
    sbit	FP46        = 0xa8:6;
    sbit	FP47        = 0xa8:7;
    
sfr	P5     	= 0xa9;	//1348
    sbit	FP50        = 0xa9:0;	//1348
    sbit	FP51        = 0xa9:1;	//1348
    sbit	FP52        = 0xa9:2;	//1348
    sbit	FP53        = 0xa9:3;	//1348
    
    sbit	FP54        = 0xa9:4;	//1348
    sbit	FP55        = 0xa9:5;	//1348
    sbit	FP56        = 0xa9:6;	//1348
    sbit	FP57        = 0xa9:7;	//1348

sfr	P0UR    = 0xAA;
    sbit	FP00UR      = 0xaa:0;
    sbit	FP01UR      = 0xaa:1;
    sbit	FP02UR      = 0xaa:2;
    sbit	FP03UR      = 0xaa:3;
	
    sbit	FP04UR      = 0xaa:4;
    sbit	FP05UR      = 0xaa:5;
    sbit	FP06UR      = 0xaa:6;
    sbit	FP07UR      = 0xaa:7;	
    
sfr	P1UR    = 0xAB;
    sbit	FP10UR      = 0xab:0;
    sbit	FP11UR      = 0xab:1;
    sbit	FP12UR      = 0xab:2;
    sbit	FP13UR      = 0xab:3;
    
    sbit	FP14UR      = 0xab:4;
    sbit	FP15UR      = 0xab:5;
    sbit	FP16UR      = 0xab:6;
    sbit	FP17UR      = 0xab:7;
    
sfr	P2UR    = 0xAC;
    sbit	FP20UR      = 0xac:0;	
    sbit	FP21UR      = 0xac:1;	
    sbit	FP22UR      = 0xac:2;	
    sbit	FP23UR      = 0xac:3;	
    
    sbit	FP24UR      = 0xac:4;	
    sbit	FP25UR      = 0xac:5;	
    sbit	FP26UR      = 0xac:6;	
    sbit	FP27UR      = 0xac:7;	

sfr	P4UR    = 0xAD;
    sbit	FP40UR      = 0xad:0;
    sbit	FP41UR      = 0xad:1;
    sbit	FP42UR      = 0xad:2;
    sbit	FP43UR      = 0xad:3;
	
    sbit	FP44UR      = 0xad:4;
    sbit	FP45UR      = 0xad:5;
    sbit	FP46UR      = 0xad:6;
    sbit	FP47UR      = 0xad:7;
    
sfr	P5UR     	= 0xae;//1348
    sbit	FP50UR      = 0xae:0;	//1348
    sbit	FP51UR      = 0xae:1;	//1348
    sbit	FP52UR      = 0xae:2;	//1348
    sbit	FP53UR      = 0xae:3;	//1348
    
    sbit	FP54UR      = 0xae:4;	//1348
    sbit	FP55UR      = 0xae:5;	//1348
    sbit	FP56UR      = 0xae:6;	//1348
    sbit	FP57UR      = 0xae:7;	//1348

sfr	REMC   = 0xAF;
    sbit	FRem_sel0      = 0xaf:0;
    sbit	FRem_sel1      = 0xaf:1;
    sbit	FRem_sel2      = 0xaf:2;
    sbit	FRem_sel3      = 0xaf:3;
    
    sbit	FRem_sel4      = 0xaf:4;
    sbit	FELE_en        = 0xaf:5;
    sbit	FD_sel         = 0xaf:6;
    sbit	FIE_sel        = 0xaf:7;


/* bank0 function <<==================================================*/
sfr	LCDCT0     	= 0xB0;
    sbit	FSCANSEL    = 0xB0:0;	
    sbit	FDUTY0      = 0xB0:4;	
    sbit	FDUTY1      = 0xB0:5;	
    sbit	FLCDEN      = 0xB0:7;	
    
sfr	LCDDB     	= 0xB1;	
    sbit	FLCDDB0    = 0xB1:0;	
    sbit	FLCDDB1    = 0xB1:1;	
    sbit	FLCDDB2    = 0xB1:2;	
    sbit	FLCDDB3    = 0xB1:3;	
    
    sbit	FLCDDB4    = 0xB1:4;	
    sbit	FLCDDB5    = 0xB1:5;	
    sbit	FLCDDB6    = 0xB1:6;	
    sbit	FLCDDB7    = 0xB1:7;	
    
sfr	LCDADR     	= 0xB2;
    sbit	FLCDA0    = 0xB2:0;	
    sbit	FLCDA1    = 0xB2:1;	
    sbit	FLCDA2    = 0xB2:2;	
    sbit	FLCDA3    = 0xB2:3;	
    sbit	FLCDA4    = 0xB2:4;	
    
sfr	LCDCT1     	= 0xB3;
    sbit	FLCDCLKS0 = 0xB3:0;	
    sbit	FLCDCLKS1 = 0xB3:1;	
    sbit	FVLO0    = 0xB3:3;	
    sbit	FVLO1    = 0xB3:4;	
    sbit	FLEDEN    = 0xB3:7;	
    
sfr	LCDCT2     	= 0xB4;
    sbit	FCOMS4    = 0xB4:4;	
    sbit	FCOMS5    = 0xB4:5;	
    sbit	FCOMS6    = 0xB4:6;	

sfr	PWM0DL  = 0xb5;
sfr	PWM0DH  = 0xb6;

sfr	PWM0PL  = 0xb7;
/* bank0 function <<==================================================*/
sfr	PWM0PH  = 0xb8;

sfr	PWM0EN  = 0xb9;
    sbit	FPWM0_EN    = 0xb9:0;
    sbit	FPWM0_OEN   = 0xb9:1;
    sbit	FPWM01_OEN  = 0xb9:2;
    sbit	FPWM0M      = 0xb9:3;
	
    sbit	FPWM1_OEN   = 0xb9:4;
    sbit	FTM1SEL8    = 0xb9:5;
    sbit	FTM1EN      = 0xb9:7;
    
sfr	PWM0C   = 0xba;
    sbit	FCK0_0      = 0xba:0;
    sbit	FCK0_1      = 0xba:1;
    sbit	FPWM0S_0    = 0xba:2;
    sbit	FPWM0S_1    = 0xba:3;
	
    sbit	FCK0_2      = 0xba:6;
    sbit	FCK0_3      = 0xba:7;
    
sfr	PWM0TL  = 0xbb;
sfr	PWM0TH  = 0xbc;

sfr	PWM0DTL = 0xbd;
sfr	PWM0DTH = 0xbe;

sfr	PWMPSC  = 0xbf;
    sbit	FPWM0_S0     = 0xbf:0;
    sbit	FPWM01_S0    = 0xbf:1;
    sbit	FPWM1_S0     = 0xbf:2;
    sbit	FPWM0_S1     = 0xbf:3;
    sbit	FPWM01_S1    = 0xbf:4;
    sbit	FPWM1_S1     = 0xbf:5;
    
/* bank0 function <<==================================================*/
sfr	P0SS     	= 0xC0;//1348
    sbit	P0SS0     = 0xC0:0;	//1348
    sbit	P0SS1     = 0xC0:1;	//1348
    sbit	P0SS2     = 0xC0:2;	//1348
    sbit	P0SS3     = 0xC0:3;	//1348
    
    sbit	P0SS4     = 0xC0:4;	//1348
    sbit	P0SS5     = 0xC0:5;	//1348
    sbit	P0SS6     = 0xC0:6;	//1348
    sbit	P0SS7     = 0xC0:7;	//1348
	
sfr	P1SS     	= 0xC1;//1348
    sbit	P1SS0     = 0xC1:0;	//1348
    sbit	P1SS1     = 0xC1:1;	//1348
    sbit	P1SS2     = 0xC1:2;	//1348
    sbit	P1SS3     = 0xC1:3;	//1348
    
    sbit	P1SS4     = 0xC1:4;	//1348
    sbit	P1SS5     = 0xC1:5;	//1348
    sbit	P1SS6     = 0xC1:6;	//1348
    sbit	P1SS7     = 0xC1:7;	//1348
    
sfr	P2SS     	= 0xC2;//1348
    sbit	P2SS0     = 0xC2:0;	//1348
    sbit	P2SS1     = 0xC2:1;	//1348
    sbit	P2SS2     = 0xC2:2;	//1348
    sbit	P2SS3     = 0xC2:3;	//1348
    
sfr	P4SS     	= 0xC3;//1348
    sbit	P4SS0     = 0xC3:0;	//1348
    sbit	P4SS1     = 0xC3:1;	//1348
    sbit	P4SS2     = 0xC3:2;	//1348
    sbit	P4SS3     = 0xC3:3;	//1348
    
    sbit	P4SS4     = 0xC3:4;	//1348
    sbit	P4SS5     = 0xC3:5;	//1348
    sbit	P4SS6     = 0xC3:6;	//1348
    sbit	P4SS7     = 0xC3:7;	//1348
    
sfr	P5SS     	= 0xC4;//1348
    sbit	P5SS0     = 0xC4:0;	//1348
    sbit	P5SS1     = 0xC4:1;	//1348
    sbit	P5SS2     = 0xC4:2;	//1348
    sbit	P5SS3     = 0xC4:3;	//1348
    
    sbit	P5SS4     = 0xC4:4;	//1348
    sbit	P5SS5     = 0xC4:5;	//1348
    sbit	P5SS6     = 0xC4:6;	//1348
    sbit	P5SS7     = 0xC4:7;	//1348
    
sfr	ADPCON1 = 0xc5;
    sbit	FADPC10     = 0xc5:0;
    sbit	FADPC11     = 0xc5:1;
    sbit	FADPC12     = 0xc5:2;
    sbit	FADPC13     = 0xc5:3;
    
sfr	ADPCON  = 0xc7;
    sbit	FADPC7       = 0xc7:7;
    sbit	FADPC6       = 0xc7:6;
    sbit	FADPC5       = 0xc7:5;
    sbit	FADPC4       = 0xc7:4;
	
    sbit	FADPC3       = 0xc7:3;
    sbit	FADPC2       = 0xc7:2;
    sbit	FADPC1       = 0xc7:1;
    sbit	FADPC0       = 0xc7:0;
    
/* bank0 function <<==================================================*/
sfr	ADM     = 0xc8;
    sbit	FADENB      = 0xc8:7;
    sbit	FADS        = 0xc8:6;
    sbit	FEOC        = 0xc8:5;
    sbit	FGCHS       = 0xc8:4;
	
    sbit	FCHS2       = 0xc8:2;
    sbit	FCHS1       = 0xc8:1;
    sbit	FCHS0       = 0xc8:0;
    
sfr	ADB     = 0xc9;
    sbit	FADB11      = 0xc9:7;
    sbit	FADB10      = 0xc9:6;
    sbit	FADB9       = 0xc9:5;
    sbit	FADB8       = 0xc9:4;
	
    sbit	FADB7       = 0xc9:3;
    sbit	FADB6       = 0xc9:2;
    sbit	FADB5       = 0xc9:1;
    sbit	FADB4       = 0xc9:0;
    
sfr	ADR     = 0xca;
    sbit	FADCKS1     = 0xca:6;
    sbit	FADCKS0     = 0xca:4;
	
    sbit	FADB3       = 0xca:3;
    sbit	FADB2       = 0xca:2;
    sbit	FADB1       = 0xca:1;
    sbit	FADB0       = 0xca:0;
    
sfr	ADT     = 0xcb;
    sbit	FADTS0      = 0xcb:4;
    sbit	FADT3       = 0xcb:3;
    sbit	FADT2       = 0xcb:2;
    sbit	FADT1       = 0xcb:1;
    sbit	FADT0       = 0xcb:0;
    
sfr	WDTC    = 0xcc;
    sbit	FWDT_EN     = 0xcc:7;
    sbit	FWDT_PRE2   = 0xcc:6;
    sbit	FWDT_PRE1   = 0xcc:5;
    sbit	FWDT_PRE0   = 0xcc:4;
    sbit	FWDTC3   = 0xcc:3;
    sbit	FWDTC2   = 0xcc:2;
    
sfr	SBANK    = 0xCD;
    sbit	FSBANK7       = 0xCD:7;
    sbit	FSBANK1       = 0xCD:1;
    sbit	FSBANK0       = 0xCD:0;

sfr	VREFH   = 0xce;
    sbit	FEVHENB     = 0xce:7;
    sbit	FVHS1       = 0xce:1;
    sbit	FVHS0       = 0xce:0;
    
sfr	LVDC    = 0xcf;
    sbit	FLVDTE      = 0xcf:7;
    
/* bank0 function <<==================================================*/
sfr	P0PD    = 0xd0;
    sbit	FP00PD      = 0xd0:0;
    sbit	FP01PD      = 0xd0:1;
    sbit	FP02PD      = 0xd0:2;
    sbit	FP03PD      = 0xd0:3;
	
    sbit	FP04PD      = 0xd0:4;
    sbit	FP05PD      = 0xd0:5;
    sbit	FP06PD      = 0xd0:6;
    sbit	FP07PD      = 0xd0:7;	//1348
    
sfr	P1PD    = 0xd1;
    sbit	FP10PD      = 0xd1:0;
    sbit	FP11PD      = 0xd1:1;
    sbit	FP12PD      = 0xd1:2;
    sbit	FP13PD      = 0xd1:3;	//1348
    
    sbit	FP14PD      = 0xd1:4;	//1348
    sbit	FP15PD      = 0xd1:5;	//1348
    sbit	FP16PD      = 0xd1:6;	//1348
    sbit	FP17PD      = 0xd1:7;	//1348

sfr	P2PD     	= 0xD2;//1348
    sbit	FP20PD      = 0xd2:0;	//1348
    sbit	FP21PD      = 0xd2:1;	//1348
    sbit	FP22PD      = 0xd2:2;	//1348
    sbit	FP23PD      = 0xd2:3;	//1348
    
    sbit	FP24PD      = 0xd2:4;	//1348
    sbit	FP25PD      = 0xd2:5;	//1348
    sbit	FP26PD      = 0xd2:6;	//1348
    sbit	FP27PD      = 0xd2:7;	//1348
    
sfr	P4PD    = 0xd3;
    sbit	FP40PD      = 0xd3:0;
    sbit	FP41PD      = 0xd3:1;
    sbit	FP42PD      = 0xd3:2;
    sbit	FP43PD      = 0xd3:3;
	
    sbit	FP44PD      = 0xd3:4;
    sbit	FP45PD      = 0xd3:5;
    sbit	FP46PD      = 0xd3:6;
    sbit	FP47PD      = 0xd3:7;
    
sfr	P5PD     	= 0xD4;//1348
    sbit	FP50PD      = 0xd4:0;	//1348
    sbit	FP51PD      = 0xd4:1;	//1348
    sbit	FP52PD      = 0xd4:2;	//1348
    sbit	FP53PD      = 0xd4:3;	//1348
    
    sbit	FP54PD      = 0xd4:4;	//1348
    sbit	FP55PD      = 0xd4:5;	//1348
    sbit	FP56PD      = 0xd4:6;	//1348
    sbit	FP57PD      = 0xd4:7;	//1348

sfr	TKC0    = 0xd5;
    sbit	FTKEN       = 0xd5:7;
    sbit	FTKST       = 0xd5:6;
    sbit	FTKGCHS     = 0xd5:5;
    sbit	FCHRVS      = 0xd5:4;
	
    sbit	FTKPS_3     = 0xd5:3;
    sbit	FTKPS_2     = 0xd5:2;
    sbit	FTKPS_1     = 0xd5:1;
    sbit	FTKPS_0     = 0xd5:0;
    
sfr	TK16DH  = 0xd6;
sfr	TK16DL  = 0xd7;

/* bank0 function <<==================================================*/
sfr	TKC1    = 0xd8;
    sbit	FCCFLT_2    = 0xd8:6;
    sbit	FCCFLT_1    = 0xd8:5;
    sbit	FCCFLT_0    = 0xd8:4;
	
    sbit	FDCTS_1     = 0xd8:1;
    sbit	FDCTS_0     = 0xd8:0;
    
sfr	TKC2    = 0xd9;
    sbit	FCTS_0      = 0xd9:0;
    sbit	FCTS_1      = 0xd9:1;
    sbit	FCTS_2      = 0xd9:2;
    sbit	FCTS_3      = 0xd9:3;
    
sfr	TKC3    = 0xda;
    sbit	TKCMOD0     = 0xda:7;
    sbit	FCPSV_1     = 0xda:4;
    sbit	FCPSV_0     = 0xda:3;
    sbit	FCVREFS_1   = 0xda:1;
    sbit	FCVREFS_0   = 0xda:0;
    
sfr	TKSTA   = 0xdb;
    sbit	FTMOUT      = 0xdb:7;
    sbit	FTKINTIF    = 0xdb:6;
    sbit	FTKINTIE    = 0xdb:5;
    sbit	FDCMPO      = 0xdb:3;
    sbit	FACMPO      = 0xdb:2;
    sbit	FSACMPO     = 0xdb:1;
    
sfr	TKPDH   = 0xdc;
sfr	TKPDL   = 0xdd;

sfr	ADF1    = 0xde;
    sbit	FADF17     = 0xde:7;//1348
sfr	ADF0    = 0xdf;

/* bank0 function <<==================================================*/
sfr	P0OD    = 0xe0;
    sbit	FP00OD      = 0xe0:0;
    sbit	FP01OD      = 0xe0:1;
    sbit	FP02OD      = 0xe0:2;
    sbit	FP03OD      = 0xe0:3;
	
    sbit	FP04OD      = 0xe0:4;
    sbit	FP05OD      = 0xe0:5;
    sbit	FP06OD      = 0xe0:6;
    sbit	FP07OD      = 0xe0:7;  	//1348
    
sfr	P1OD    = 0xe1;
    sbit	FP10OD      = 0xe1:0;
    sbit	FP11OD      = 0xe1:1;
    sbit	FP12OD      = 0xe1:2;
    sbit	FP13OD      = 0xe1:3;  	//1348
	
    sbit	FP14OD      = 0xe1:4;  	//1348
    sbit	FP15OD      = 0xe1:5;  	//1348
    sbit	FP16OD      = 0xe1:6;  	//1348
    sbit	FP17OD      = 0xe1:7;  	//1348
	
sfr	P2OD    = 0xe2;	//1348
    sbit	FP20OD      = 0xe2:0;  	//1348
    sbit	FP21OD      = 0xe2:1;  	//1348
    sbit	FP22OD      = 0xe2:2;  	//1348
    sbit	FP23OD      = 0xe2:3;  	//1348
	
    sbit	FP24OD      = 0xe2:4;  	//1348
    sbit	FP25OD      = 0xe2:5;  	//1348
    sbit	FP26OD      = 0xe2:6;  	//1348
    sbit	FP27OD      = 0xe2:7;  	//1348
    
sfr	P4OD    = 0xe3;
    sbit	FP40OD      = 0xe3:0;
    sbit	FP41OD      = 0xe3:1;
    sbit	FP42OD      = 0xe3:2;
    sbit	FP43OD      = 0xe3:3;
	
    sbit	FP44OD      = 0xe3:4;
    sbit	FP45OD      = 0xe3:5;
    sbit	FP46OD      = 0xe3:6;
    sbit	FP47OD      = 0xe3:7;
    
sfr	P5OD    = 0xe4;	//1348
    sbit	FP50OD      = 0xe4:0;  	//1348
    sbit	FP51OD      = 0xe4:1;  	//1348
    sbit	FP52OD      = 0xe4:2;  	//1348
    sbit	FP53OD      = 0xe4:3;  	//1348
	
    sbit	FP54OD      = 0xe4:4;  	//1348
    sbit	FP55OD      = 0xe4:5;  	//1348
    sbit	FP56OD      = 0xe4:6;  	//1348
    sbit	FP57OD      = 0xe4:7;  	//1348

sfr	SMTS    = 0xe5;
    sbit	FSMTS0      = 0xe5:0;
    sbit	FSMTS1      = 0xe5:1;
    sbit	FSMTS2      = 0xe5:2;  	//1348
    sbit	FSMTS4      = 0xe5:3;
    sbit	FSMTS5      = 0xe5:4;  	//1348
    
sfr	TC0D2   = 0xe6;
sfr	TC0M1   = 0xe7;
    sbit	FPWM1EN      = 0xe7:0;
    sbit	FPWM2EN      = 0xe7:1;
    sbit	FPWM0S0      = 0xe7:2;  	//1348
    sbit	FPWM1S0      = 0xe7:3;  	//1348
	
    sbit	FPWM2S0      = 0xe7:4;  	//1348
    sbit	FPWM0S1      = 0xe7:5;
    sbit	FPWM1S1      = 0xe7:6;
    sbit	FPWM2S1      = 0xe7:7;
    
/* bank0 function <<==================================================*/
sfr	PWM1DL  = 0xe8;
sfr	PWM1DH  = 0xe9;//2021.0513

sfr	TC0M    = 0xea;
    sbit	FTC0TR      = 0xea:7;
    sbit	FTC0S2      = 0xea:6;
    sbit	FTC0S1      = 0xea:5;
    sbit	FTC0S0      = 0xea:4;
	
    sbit	FTCCKS      = 0xea:3;
    sbit	FINT0CK     = 0xea:2;
    sbit	FPWM0       = 0xea:0;
    
sfr	TC0R    = 0xeb;

sfr	TC0CL   = 0xec;
sfr	TC0CH   = 0xed;

sfr	TC0D1   = 0xee;

sfr	STKP = 0xef;
    sbit	FGIE        = 0xef:7;
    sbit	FSTKPB2     = 0xef:2;
    sbit	FSTKPB1     = 0xef:1;
    sbit	FSTKPB0     = 0xef:0;
    
/* bank0 function <<==================================================*/
sfr	STK7L   = 0xf0;
sfr	STK7H   = 0xf1;
sfr	STK6L   = 0xf2;
sfr	STK6H   = 0xf3;

sfr	STK5L   = 0xf4;
sfr	STK5H   = 0xf5;
sfr	STK4L   = 0xf6;
sfr	STK4H   = 0xf7;

sfr	STK3L   = 0xf8;
sfr	STK3H   = 0xf9;
sfr	STK2L   = 0xfa;
sfr	STK2H   = 0xfb;

sfr	STK1L   = 0xfc;
sfr	STK1H   = 0xfd;
sfr	STK0L   = 0xfe;
sfr	STK0H   = 0xff;


/* bank1 function <<==================================================*/
sfr	TL0C1  = 0xb0;	//20210513
sfr	TL0C2  = 0xb1;//20210513
sfr	TL0C3  = 0xb2;//20210513
sfr	PWM3DL  = 0xb3;//20210513

sfr	PWM3DH  = 0xb4;//20210513
sfr	PWM2DL  = 0xb5;//20210513
sfr	PWM2DH  = 0xb6;//20210513
sfr	PWM2PL  = 0xb7;//20210513
/* bank1 function <<==================================================*/
sfr	PWM2PH  = 0xb8;
sfr	PWM1EN  = 0xb9;//
    sbit	FPWM2_EN    = 0xb9:0;
    sbit	FPWM2_OEN   = 0xb9:1;
    sbit	FPWM21_OEN  = 0xb9:2;
    sbit	FPWM1M      = 0xb9:3;
	
    sbit	FPWM3_OEN   = 0xb9:4;
    sbit	FTM2SEL8    = 0xb9:5;
    sbit	FTM2SEL16   = 0xb9:6;
    sbit	FTM2EN      = 0xb9:7;
    
sfr	PWM2C   = 0xba;
    sbit	FCK2_0      = 0xba:0;
    sbit	FCK2_1      = 0xba:1;
    sbit	FPWM2SL_0    = 0xba:2;
    sbit	FPWM2SL_1    = 0xba:3;
    sbit	FCK2_2      = 0xba:6;
    sbit	FCK2_3      = 0xba:7;
    
sfr	PWM2TL  = 0xbb;
sfr	PWM2TH  = 0xbc;
sfr	PWM2DTL = 0xbd;
sfr	PWM2DTH = 0xbe;
sfr	PWM2PSC = 0xbf;
    sbit	FPWM2_S0      = 0xbf:0;
    sbit	FPWM21_S0     = 0xbf:1;
    sbit	FPWM3_S0      = 0xbf:2;
    sbit	FPWM2_S1      = 0xbf:3;
    sbit	FPWM21_S1      = 0xbf:4;
    sbit	FPWM3_S1      = 0xbf:5;

/* bank1 function <<==================================================*/
sfr	P0SC    = 0xc0;
    sbit	FP07SC      = P0SC:6;	//1348
    sbit	FP06SC      = P0SC:6;
    sbit	FP05SC      = P0SC:5;
    sbit	FP04SC      = P0SC:4;
    sbit	FP03SC      = P0SC:3;
    sbit	FP02SC      = P0SC:2;
    sbit	FP01SC      = P0SC:1;
    sbit	FP00SC      = P0SC:0;

sfr	P4SC    = 0xc1;
    sbit	FP47SC      = P4SC:7;
    sbit	FP46SC      = P4SC:6;
    sbit	FP45SC      = P4SC:5;
    sbit	FP44SC      = P4SC:4;
	
    sbit	FP43SC      = P4SC:3;
    sbit	FP42SC      = P4SC:2;
    sbit	FP41SC      = P4SC:1;
    sbit	FP40SC      = P4SC:0;

sfr	P0IS    = 0xc2;
    sbit	FP03IS      = 0xc2:3;
    sbit	FP02IS      = 0xc2:2;
    sbit	FP01IS      = 0xc2:1;
    sbit	FP00IS      = 0xc2:0;
    
sfr	P1IS    = 0xc3;
    sbit	FP13IS      = 0xc3:3;
    sbit	FP12IS      = 0xc3:2;
    sbit	FP11IS      = 0xc3:1;
    sbit	FP10IS      = 0xc3:0;
    
sfr	P2IS    = 0xc4;	//1348
    sbit	FP23IS      = 0xc4:3;	//1348
    sbit	FP22IS      = 0xc4:2;	//1348
    sbit	FP21IS      = 0xc4:1;	//1348
    sbit	FP20IS      = 0xc4:0;	//1348

sfr	P4IS    = 0xc5;
    sbit	FP43IS      = 0xc5:3;
    sbit	FP42IS      = 0xc5:2;
    sbit	FP41IS      = 0xc5:1;
    sbit	FP40IS      = 0xc5:0;
    
sfr	P5IS    = 0xc6;	//1348
    sbit	FP53IS      = 0xc6:3;	//1348
    sbit	FP52IS      = 0xc6:2;	//1348
    sbit	FP51IS      = 0xc6:1;	//1348
    sbit	FP50IS      = 0xc6:0;	//1348

sfr	TL0M    = 0xc7;
    sbit	FT2TR       = 0xc7:7;
    sbit	FT2WC       = 0xc7:6;
    sbit	FTP2S2      = 0xc7:5;
    sbit	FTP2S1      = 0xc7:4;
    sbit	FTP2S0      = 0xc7:3;
    sbit	FT2BSEL      = 0xc7:2;

/* bank1 function <<==================================================*/
sfr	TL0C    = 0xc8;

sfr	T0M     = 0xc9;
    sbit	FT0TR       = 0xc9:7;
    sbit	FTP0S2      = 0xc9:6;
    sbit	FTP0S1      = 0xc9:5;
    sbit	FTP0S0      = 0xc9:4;
    sbit	FTP0SEL     = 0xc9:3;
    sbit	FT0CK       = 0xc9:2;
    sbit	FTC0GN      = 0xc9:0;
    
sfr	T0L     = 0xca;
sfr	T0H     = 0xcb;

sfr	T0M1    = 0xcc;
    sbit	FPWMW2      = 0xcc:4;
    sbit	FPWMW1      = 0xcc:3;
    //sbit	FINT0W      = 0xcc:2;
    sbit	FT0OVS      = 0xcc:1;
    sbit	FT0GN       = 0xcc:0;

sfr	TIRCF   = 0xce;
    
/* BANK1 function <<==================================================*/
sfr	I2CCON  = 0xd0;
    sbit	FI2CEN      = 0xd0:0;
    sbit	FI2CPU      = 0xd0:1;
    sbit	FI2CCKP     = 0xd0:2;
    sbit	FTXAK       = 0xd0:3;
	
    sbit	FSRW        = 0xd0:4;
    sbit	FHBB        = 0xd0:5;
    sbit	FHAAS       = 0xd0:6;
    sbit	FHCF        = 0xd0:7;
    
sfr	I2CADR  = 0xd1;
sfr	I2CBUF  = 0xd2;
sfr	I2CTOV  = 0xd3;
    sbit	FTOS0       = 0xd3:0;
    sbit	FTOS1       = 0xd3:1;
    sbit	FTOS2       = 0xd3:2;
    sbit	FTOVF       = 0xd3:6;
    sbit	FTOVEN      = 0xd3:7;
   

/* BANK1 function <<==================================================*/
sfr	RCSTA   = 0xe0; //
    sbit	FRX9D     = 0xE0:0;	
    sbit	FOERR     = 0xE0:1;
    sbit	FFERR     = 0xE0:2;
    sbit	FADDEN    = 0xE0:3;
	
    sbit	FCREN     = 0xE0:4;
    sbit	FSREN     = 0xE0:5;
    sbit	FRX9      = 0xE0:6;
    sbit	FSPEN     = 0xE0:7;
	
sfr	TXREG   = 0xe1; //
sfr	RCREG   = 0xe2; //

sfr	TXSTA   = 0xe3; //
    sbit	FTX9D     = 0xE3:0;	
    sbit	FTRMT     = 0xE3:1;
    sbit	FBRGH     = 0xE3:2;
	
    sbit	FSYNC     = 0xE3:4;
    sbit	FTXEN     = 0xE3:5;
    sbit	FTX9      = 0xE3:6;

sfr	SPBRG   = 0xe4; //
sfr	SPBRGH	  = 0xe5; //

sfr	BAUDCTL = 0xe6; //
      sbit  FRXIF   = BAUDCTL:1;
      sbit  FTXIF   = BAUDCTL:0;
    sbit	FIFTX      = 0xE6:0;	
    sbit	FIFRX      = 0xE6:1;
    sbit	FITXEN     = 0xE6:4;
    sbit	FIRXEN     = 0xE6:5;			
    
sfr	SIMC0   = 0xe7;
    sbit	FSPIM2      = 0xe7:7;
    sbit	FSPIM1      = 0xe7:6;
    sbit	FSPIM0      = 0xe7:5;
    sbit	FSPIEN      = 0xe7:1;

/* bank1 function <<==================================================*/
sfr	SIMC1   = 0xe8;
    sbit	FTRF       = 0xe8:0;
    sbit	FSSEN      = 0xe8:2;
    sbit	FMLS       = 0xe8:3;
    sbit	FCKP       = 0xe8:4;
    sbit	FCKEG      = 0xe8:5;

sfr	SIMD    = 0xea;

sfr	ITFACES = 0xed; //
    sbit	FRXIN      = 0xED:0;
    sbit	FTXOUT     = 0xED:1;
    sbit	FI2CSCL    = 0xED:2;
    sbit	FI2CSDA    = 0xED:3;
	
    sbit	FSPICLK    = 0xED:4;
    sbit	FSCS_      = 0xED:5;
    sbit	FSPIIN     = 0xED:6;

    sbit ITFACES_RX  = ITFACES:0;
    sbit ITFACES_TX  = ITFACES:1;
	
sfr	ITFACES1 = 0xee; //
    sbit	UARTPTS0      = 0xEE:0;
    sbit	UARTPTS1      = 0xEE:1;
    sbit	UARTPTS2      = 0xEE:2;

/* BANK2 function <<==================================================*/
sfr	CMPC1   = 0xb0; 
sfr	LFSEL   = 0xb2; 
    sbit	FLFSEL0     = 0xb2:0;
    sbit	FLFSEL1     = 0xb2:1;
    sbit	FLFSEL2     = 0xb2:2;
    sbit	FLFSEL4     = 0xb2:4;
    sbit	FLFSEL5     = 0xb2:5;

//sfr	ADCCN3   = 0xb3;
//sfr	ADCCN1   = 0xb4;	
    
sfr	PWM4DL   = 0xb5; 	
sfr	PWM4DH   = 0xb6; 
    
sfr	PWM4PL   = 0xb7; 	

/* BANK2 function <<==================================================*/
sfr	PWM4PH   = 0xb8; 	
    
sfr	PWM2EN   = 0xb9; 
    sbit	FPWM4_EN     = 0xb9:0;	
    sbit	FPWM4_OEN    = 0xb9:1;
    sbit	FPWM41_OEN   = 0xb9:2;
    sbit	FPWM2M       = 0xb9:3;
    sbit	FTM3SEL8     = 0xb9:5;
    sbit	FTM3EN       = 0xb9:7;					
    
sfr	PWM4C   = 0xba; 
    
sfr	PWM4TL   = 0xbb; 
sfr	PWM4TH   = 0xbc; 	
    
sfr	PWM4DTL   = 0xbd; 	    
sfr	PWM4DTH   = 0xbe; 	

/* BANK2 function <<==================================================*/
sfr	LOAD   = 0xCF; 

/* BANK2 function <<==================================================*/
sfr	FDATL   = 0xDF; 

/* BANK2 function <<==================================================*/
//sfr	EADRL   = 0xe0; //
//    
//sfr	EECON1  = 0xe1; //
//    sbit	FREADEE     = 0xe1:0;
//    sbit	FPROGEE     = 0xe1:1;
//    sbit	FERASEEE    = 0xe1:2;
//    sbit	FERSALLEE   = 0xe1:3;
//	
//    sbit	FTIMEE0     = 0xe1:5;
//    sbit	FTIMEE1     = 0xe1:6;
//    
//sfr	EDATL   = 0xe2; 

sfr	CMPCON  = 0xe3; 
sfr	CMPC	= 0xe3;
    sbit	FCOPOL      = 0xe3:1;
    sbit	FCVENH      = 0xe3:2;
    sbit	FCPENH      = 0xe3:3;//1328修改2020.07.02
	
    sbit	FCODEB      = 0xe3:4;
    sbit	FFTCKS      = 0xe3:5;
    //sbit	FCMPIF      = 0xe3:6;
    sbit	FCMPEN      = 0xe3:7;

sfr	CMPM    = 0xe4; 
    sbit	FVRS0       = 0xe4:0;
    sbit	FVRS1       = 0xe4:1;
    sbit	FVRS2       = 0xe4:2;
    sbit	FVRS3       = 0xe4:3;
	
    sbit	FXRVSEL     = 0xe4:4;
    sbit	FCPINS0     = 0xe4:5;
    sbit	FCPINS1     = 0xe4:6;
    sbit	FCMPSEL     = 0xe4:7;

sfr	OPAM    = 0xe5; //
    sbit	FOPAM0       = 0xe5:0;
    sbit	FOPAM1       = 0xe5:1;
    sbit	FOPAM2       = 0xe5:2;
    sbit	FOPAM3       = 0xe5:3;
	
    sbit	FOPAM4       = 0xe5:4;
    sbit	FOPAM5       = 0xe5:5;
    sbit	FOPAM6       = 0xe5:6;
    sbit	FOPAM7       = 0xe5:7;
	
sfr	OPAM1   = 0xe6; 
    sbit	FOPAM10       = 0xe6:0;
    sbit	FOPAM11       = 0xe6:1;
    sbit	FOPAM12       = 0xe6:2;
    sbit	FOPAM13       = 0xe6:3;
    sbit	FOPAM17       = 0xe6:7;

sfr	OPAMC   = 0xe7; 
    sbit	FAP1NS        = 0xe7:0;
    sbit	FAP1NS0       = 0xe7:1;
    sbit	FAP1OS        = 0xe7:2;
    sbit	FAP1OSP       = 0xe7:3;
	
    sbit	FAP1PS0       = 0xe7:4;
    sbit	FAP1PS        = 0xe7:5;
    sbit	FLVHSEN       = 0xe7:6;
    sbit	FOPAMC7       = 0xe7:7;
	
/* BANK2 function <<==================================================*/
sfr	OPAMC1  = 0xe8; 
    sbit	FAP2NS        = 0xe8:0;
    sbit	FAP2NS0       = 0xe8:1;
    sbit	FAP2OS        = 0xe8:2;
    sbit	FAP2OSP       = 0xe8:3;
	
    sbit	FAP2PS0       = 0xe8:4;
    sbit	FAP2PS        = 0xe8:5;
    sbit	FLVHSEN1      = 0xe8:6;
    sbit	FOPAMC17      = 0xe8:7;

sfr	FLER    = 0xe9; 
    sbit	FFOV        = 0xe9:0;

sfr	FADRH   = 0xea; 
sfr	FADRL   = 0xeb; 

sfr	FCON1   = 0xec; 
    sbit	FREADL        = 0xec:0;
    sbit	FPROGL        = 0xec:1;
    sbit	FERASEL       = 0xec:2;
	
    sbit	FTIMEL0        = 0xec:5;
    sbit	FTIMEL1        = 0xec:6;
    sbit	FCEFL         = 0xec:7;
	
sfr	FCON2   = 0xed; 

sfr	FDATH   = 0xee; 


/* BANK2 function <<==================================================*/


#endif

