#ifndef __SN8P2522__H
#define __SN8P2522__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FLVD24 = 0x86:4;
sbit	FLVD36 = 0x86:5;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	CMP0M = 0x9c;
sbit	FCMCH0 = 0x9c:0;
sbit	FCMCH1 = 0x9c:1;
sbit	FCMCH2 = 0x9c:2;
sbit	FCM0S0 = 0x9c:3;
sbit	FCM0S1 = 0x9c:4;
sbit	FCM0OUT = 0x9c:6;
sbit	FCM0EN = 0x9c:7;
sfr	CMP0M1 = 0x9d;
sbit	FCM0G0 = 0x9d:0;
sbit	FCM0G1 = 0x9d:1;
sbit	FCMDB0 = 0x9d:2;
sbit	FCMDB1 = 0x9d:3;
sbit	FCMP0M17 = 0x9d:7;
sbit	FCMP0M16 = 0x9d:6;
sbit	FCMP0M15 = 0x9d:5;
sbit	FCMP0M14 = 0x9d:4;
sfr	T1M = 0xa0;
sbit	FCPTG0 = 0xa0:0;
sbit	FCPTG1 = 0xa0:1;
sbit	FCPTStart = 0xa0:2;
sbit	FCPTCKS = 0xa0:3;
sbit	FT1rate0 = 0xa0:4;
sbit	FT1rate1 = 0xa0:5;
sbit	FT1rate2 = 0xa0:6;
sbit	FT1ENB = 0xa0:7;
sfr	T1CL = 0xa1;
sfr	T1CH = 0xa2;
sfr	T1VCL = 0xa3;
sfr	T1VCH = 0xa4;
sfr	T1CKM = 0xa5;
sbit	FCPTVC = 0xa5:7;
sbit	FT1CKM2 = 0xa5:2;
sbit	FT1CKM1 = 0xa5:1;
sbit	FT1CKM0 = 0xa5:0;
sfr	SIOM = 0xb4;
sbit	FSENB = 0xb4:7;
sbit	FSTART = 0xb4:6;
sbit	FSRATE1 = 0xb4:5;
sbit	FSRATE0 = 0xb4:4;
sbit	FMLSB = 0xb4:3;
sbit	FSCKMD = 0xb4:2;
sbit	FCPOL = 0xb4:1;
sbit	FCPHA = 0xb4:0;
sfr	SIOR = 0xb5;
sfr	SIOB = 0xb6;
sfr	P0M = 0xb8;
sbit	FP00M = 0xb8:0;
sfr	PEDGE = 0xbf;
sbit	FP00G1 = 0xbf:4;
sbit	FP00G0 = 0xbf:3;
sfr	P1W = 0xc0;
sfr	P1M = 0xc1;
sbit	FP10M = 0xc1:0;
sbit	FP11M = 0xc1:1;
sbit	FP12M = 0xc1:2;
sbit	FP13M = 0xc1:3;
sbit	FP14M = 0xc1:4;
sbit	FP15M = 0xc1:5;
sbit	FP16M = 0xc1:6;
sbit	FP17M = 0xc1:7;
sfr	P5M = 0xc5;
sbit	FP50M = 0xc5:0;
sbit	FP51M = 0xc5:1;
sbit	FP52M = 0xc5:2;
sbit	FP53M = 0xc5:3;
sbit	FP54M = 0xc5:4;
sbit	FP55M = 0xc5:5;
sfr	INTRQ = 0xc8;
sbit	FP00IRQ = 0xc8:0;
sbit	FT1IRQ = 0xc8:2;
sbit	FSIOIRQ = 0xc8:3;
sbit	FT0IRQ = 0xc8:4;
sbit	FTC0IRQ = 0xc8:5;
sbit	FTC1IRQ = 0xc8:6;
sbit	FCM0IRQ = 0xc8:7;
sfr	INTEN = 0xc9;
sbit	FP00IEN = 0xc9:0;
sbit	FT1IEN = 0xc9:2;
sbit	FSIOIEN = 0xc9:3;
sbit	FT0IEN = 0xc9:4;
sbit	FTC0IEN = 0xc9:5;
sbit	FTC1IEN = 0xc9:6;
sbit	FCM0IEN = 0xc9:7;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	TC0R = 0xcd;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP10 = 0xd1:0;
sbit	FP11 = 0xd1:1;
sbit	FP12 = 0xd1:2;
sbit	FP13 = 0xd1:3;
sbit	FP14 = 0xd1:4;
sbit	FP15 = 0xd1:5;
sbit	FP16 = 0xd1:6;
sbit	FP17 = 0xd1:7;
sfr	P5 = 0xd5;
sbit	FP50 = 0xd5:0;
sbit	FP51 = 0xd5:1;
sbit	FP52 = 0xd5:2;
sbit	FP53 = 0xd5:3;
sbit	FP54 = 0xd5:4;
sbit	FP55 = 0xd5:5;
sbit	FP56 = 0xd5:6;
sfr	T0M = 0xd8;
sbit	FT0RATE0 = 0xd8:4;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0ENB = 0xd8:7;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FPWM0OUT = 0xda:0;
sbit	FTC0CKS0 = 0xda:2;
sbit	FTC0CKS1 = 0xda:3;
sbit	FTC0rate0 = 0xda:4;
sbit	FTC0rate1 = 0xda:5;
sbit	FTC0rate2 = 0xda:6;
sbit	FTC0ENB = 0xda:7;
sfr	TC0C = 0xdb;
sfr	TC1M = 0xdc;
sbit	FPWM1OUT = 0xdc:0;
sbit	FTC1CKS0 = 0xdc:2;
sbit	FTC1rate0 = 0xdc:4;
sbit	FTC1rate1 = 0xdc:5;
sbit	FTC1rate2 = 0xdc:6;
sbit	FTC1ENB = 0xdc:7;
sfr	TC1C = 0xdd;
sfr	TC1R = 0xde;
sfr	STKP = 0xdf;
sbit	FSTKPB0 = 0xdf:0;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB2 = 0xdf:2;
sbit	FGIE = 0xdf:7;
sfr	P0UR = 0xe0;
sbit	FP00R = 0xe0:0;
sfr	P1UR = 0xe1;
sbit	FP10R = 0xe1:0;
sbit	FP11R = 0xe1:1;
sbit	FP12R = 0xe1:2;
sbit	FP13R = 0xe1:3;
sbit	FP14R = 0xe1:4;
sbit	FP15R = 0xe1:5;
sbit	FP16R = 0xe1:6;
sbit	FP17R = 0xe1:7;
sfr	P5UR = 0xe5;
sbit	FP50R = 0xe5:0;
sbit	FP51R = 0xe5:1;
sbit	FP52R = 0xe5:2;
sbit	FP53R = 0xe5:3;
sbit	FP54R = 0xe5:4;
sbit	FP55R = 0xe5:5;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	TC0D = 0xe8;
sfr	P1OC = 0xe9;
sbit	FP50OC = 0xe9:2;
sbit	FP51OC = 0xe9:3;
sbit	FP52OC = 0xe9:4;
sbit	FP53OC = 0xe9:5;
sbit	FP54OC = 0xe9:6;
sfr	TC1D = 0xea;
sfr	TOUCH0 = 0xed;
sfr	TOUCH1 = 0xee;
sfr	TOUCH2 = 0xef;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
