;****************************************************   
;Copyright (asm) 2022   苏州华芯微电子股份有限公司   
;					       							   
;文件名称:    HS16F1200.inc               			   
;文件标识:					    					   
;摘要:					    					   
;**************************************************** 
;当前版本:		V1.00		 						   
;作   者:			                    			   
;完成日期:		2022-10-21              			   
;****************************************************   
;【features】
;42-RISC-instruct
;ROM:		1K*14-ROM
;EEPROM:	128*BYTE-EEPROM
;RAM:		64*BYTE-RAM
;TP0
;TC0
;stack:	8-level
;*****************************************************   
;BANK0~3-define
;*****************************************************   
INDF	EQU		000H    
PCL		EQU		002H 
  
STATUS	EQU		003H   
	#define		CARRY           STATUS,0
	#define		ZERO            STATUS,2
	#define		RST             STATUS,7
	
	#define		C	                STATUS,0
	#define		DC                  STATUS,1
	#define		Z                   STATUS,2
	#define		NPD                 STATUS,3	
	#define		NTO                 STATUS,4
	#define		RP0                 STATUS,5
	#define		RP1                 STATUS,6
	#define		IRP                 STATUS,7
	
	#define		FC	            STATUS,0
	#define		FDC             STATUS,1
	#define		FZ              STATUS,2	
	#define		FNPD            STATUS,3
	#define		FNTO            STATUS,4
	#define		FRP0            STATUS,5
	#define		FRP1            STATUS,6
	#define		FRST            STATUS,7
	#define		FIRP            STATUS,7	
	
FSR		EQU		004H   
	#define		FSR7               FSR,7
	#define		FFSR7              FSR,7
	
PCHBUF	EQU		0AH   
#define 	PCLATH 	PCHBUF
	#define		PCH0              PCLATH,0
	#define		PCH1              PCLATH,1
	
	#define		FPCH0              PCLATH,0
	#define		FPCH1              PCLATH,1
	
INTEN	EQU		0BH    
	#define		PBIE		INTEN,1   
	#define		INTIE		INTEN,2   
	#define		TC0IE		INTEN,3  	   
	#define		TP0IE		INTEN,4   
	#define		INT1IE		INTEN,5     
	#define		GIE			INTEN,7
	
	#define		FPBIE			INTEN,1   
	#define		FINTIE			INTEN,2   
	#define		FTC0IE			INTEN,3 	   
	#define		FTP0IE			INTEN,4   
	#define		FINT1IE			INTEN,5     
	#define		FGIE			INTEN,7   
	   
INTFLAG	EQU		0CH 
	#define		PBIF		INTFLAG,1   
	#define		INTIF		INTFLAG,2   
	#define		TC0IF		INTFLAG,3 
	#define		TP0IF		INTFLAG,4   
	#define		INT1IF		INTFLAG,5
	 
	#define		FPBIF			INTFLAG,1   
	#define		FINTIF			INTFLAG,2   
	#define		FTC0IF			INTFLAG,3 
	#define		FTP0IF			INTFLAG,4   
	#define		FINT1IF			INTFLAG,5 

;*****************************************************   
;BANK0-define
;*****************************************************   
PORTB	EQU		006H   
PB		EQU		006H     
RB		EQU		006H 
	#define		PB0             PORTB,0
	#define		PB1             PORTB,1
	#define		PB2             PORTB,2
	#define		PB3             PORTB,3
	#define		PB4             PORTB,4
	#define		PB5             PORTB,5	
	
	#define		FPB0                PORTB,0
	#define		FPB1                PORTB,1
	#define		FPB2                PORTB,2
	#define		FPB3                PORTB,3
	#define		FPB4                PORTB,4
	#define		FPB5                PORTB,5	  

PDCON	EQU		0EH
	#define		PDB0              PDCON,4
	#define		PDB1              PDCON,5
	#define		PDB2              PDCON,6
	#define		PDB3              PDCON,7	

	#define		FPDB0                PDCON,4
	#define		FPDB1                PDCON,5
	#define		FPDB2                PDCON,6
	#define		FPDB3                PDCON,7	

ODCON	EQU		0FH
	#define		ODB0              ODCON,0
	#define		ODB1              ODCON,1
	#define		ODB2              ODCON,2
	#define		ODB3              ODCON,3
	#define		ODB4              ODCON,4
	#define		ODB5              ODCON,5
	
	#define		FODB0                ODCON,0
	#define		FODB1                ODCON,1
	#define		FODB2                ODCON,2
	#define		FODB3                ODCON,3
	#define		FODB4                ODCON,4
	#define		FODB5                ODCON,5

;***************************************************** 
PHCON	EQU		010H  
	#define		PHB0            PHCON,0
	#define		PHB1            PHCON,1
	#define		PHB2            PHCON,2
	#define		PHB3            PHCON,3
	#define		PHB4            PHCON,4
	#define		PHB5            PHCON,5
	
	#define		FPHB0              PHCON,0
	#define		FPHB1              PHCON,1
	#define		FPHB2              PHCON,2
	#define		FPHB3              PHCON,3
	#define		FPHB4              PHCON,4
	#define		FPHB5              PHCON,5
    
TC0L	EQU		011H

TC0M	EQU		012H;   
	#define		TCCKS		TC0M,3  
	#define		TC0S0		TC0M,4   
	#define		TC0S1		TC0M,5   
	#define		TC0S2		TC0M,6   
	#define		TC0TR		TC0M,7 
	    
	#define		FTCCKS			TC0M,3  
	#define		FTC0S0			TC0M,4   
	#define		FTC0S1			TC0M,5   
	#define		FTC0S2			TC0M,6   
	#define		FTC0TR			TC0M,7 


;*****************************************************  
;BANK1-define
;*****************************************************  
OPTION_REG	EQU		081H	
;#define 	OPTION 	OPTION_REG
	#define 	PS0             OPTION_REG,0
	#define 	PS1             OPTION_REG,1
	#define 	PS2             OPTION_REG,2
	#define 	INTEDG          OPTION_REG,6
	#define 	INTEDG1         OPTION_REG,7
	
	#define 	FPS0               OPTION_REG,0
	#define 	FPS1               OPTION_REG,1
	#define 	FPS2               OPTION_REG,2
	#define 	FINTEDG            OPTION_REG,6
	#define 	FINTEDG1           OPTION_REG,7

TRISB	EQU		086H  
#define 	IOSTB	TRISB
	#define 	TRISB0        TRISB,0
	#define 	TRISB1        TRISB,1
	#define 	TRISB2        TRISB,2
	#define 	TRISB3        TRISB,3
	#define 	TRISB4        TRISB,4
	#define 	TRISB5        TRISB,5
	
	#define 	FTRISB0          TRISB,0
	#define 	FTRISB1          TRISB,1
	#define 	FTRISB2          TRISB,2
	#define 	FTRISB3          TRISB,3
	#define 	FTRISB4          TRISB,4
	#define 	FTRISB5          TRISB,5

PCON	EQU		08EH   
	#define 	LVDTE	PCON,5
	#define 	LVREN	PCON,5
	#define 	EIS		PCON,6
	#define 	WDTE	PCON,7
	
	#define 	FLVDTE		PCON,5
	#define 	FLVREN		PCON,5
	#define 	FEIS		PCON,6
	#define 	FWDTE		PCON,7

WUCON	EQU		08FH  
	#define 	WUB0        WUCON,0
	#define 	WUB1        WUCON,1
	#define 	WUB2        WUCON,2
	#define 	WUB3        WUCON,3
	#define 	WUB4        WUCON,4
	#define 	WUB5        WUCON,5
	
	#define 	FWUB0          WUCON,0
	#define 	FWUB1          WUCON,1
	#define 	FWUB2          WUCON,2
	#define 	FWUB3          WUCON,3
	#define 	FWUB4          WUCON,4
	#define 	FWUB5          WUCON,5

;***************************************************** 
PBIC0		EQU		091H
	
OSCM		EQU		094H
	#define		CLKMD		OSCM,0   
	#define		STPHX		OSCM,1   
	#define		XTSEL		OSCM,2   
	#define		SLCON		OSCM,3 
	#define		SLT0CON		OSCM,4 
	#define		SLT0C		OSCM,4    
	#define		GREENEN		OSCM,5   
	#define		WAKEMODE	OSCM,6   

	#define		FCLKMD			OSCM,0   
	#define		FSTPHX			OSCM,1   
	#define		FXTSEL			OSCM,2   
	#define		FSLCON			OSCM,3 
	#define		FSLT0CON		OSCM,4  
	#define		FSLT0C			OSCM,4  
	#define		FGREENEN		OSCM,5   
	#define		FWAKEMODE		OSCM,6 


;*****************************************************  
;BANK2-define
;*****************************************************
EEADRL		EQU		00DH;010DH
#define		EEADR	EEADRL

EEDATL		EQU		0EH;010EH

;EEADRH		EQU		0FH;010FH;

EECON1		EQU		010H;0110H;
#define		EECON	EECON1
	#define		READEE		EECON1,0
	#define		PROGEE		EECON1,1
	#define		ERASEEE		EECON1,2
	#define		ERSALLEE	EECON1,3
	#define		ERSX16		EECON1,4
	#define		TIMEE0		EECON1,5
	#define		TIMEE1		EECON1,6
	#define		TIMEEE		EECON1,6
	
	#define		FREADEE		EECON1,0
	#define		FPROGEE		EECON1,1
	#define		FERASEEE	EECON1,2
	#define		FERSALLEE	EECON1,3
	#define		FERSX16		EECON1,4
	#define		FTIMEE0		EECON1,5
	#define		FTIMEE1		EECON1,6
	#define		FTIMEEE		EECON1,6

PWM0EN		EQU		011H;0111H  		
	#define		LOADEN		PWM0EN,0 
	#define		PWM0XEN		PWM0EN,1  
	#define		PWM01XEN	PWM0EN,2   
	;#define		PWM0M		PWM0EN,3 
	#define		PWM1XEN		PWM0EN,4  
	#define		TP0SEL8		PWM0EN,5   	   
	#define		TP0EN		PWM0EN,7 
	
	#define		FLOADEN			PWM0EN,0 
	#define		FPWM0XEN		PWM0EN,1  
	#define		FPWM01XEN		PWM0EN,2   
	;#define		FPWM0M			PWM0EN,3 
	#define		FPWM1XEN		PWM0EN,4  
	#define		FTP0SEL8		PWM0EN,5   	   
	#define		FTP0EN			PWM0EN,7   

PWM0C		EQU		012H;0112H  
	#define		CK0_0			PWM0C,0 
	#define		CK0_1			PWM0C,1  
	#define		PWM0SV0			PWM0C,2  
	#define		PWM0SV1			PWM0C,3  
	#define		PWM0SV2			PWM0C,4  
	#define		CK0_2			PWM0C,6  	   
	#define		CK0_3			PWM0C,7 
	
	#define		FCK0_0				PWM0C,0 
	#define		FCK0_1				PWM0C,1  
	#define		FPWM0SV0			PWM0C,2
	#define		FPWM0SV1			PWM0C,3
	#define		FPWM0SV2			PWM0C,4
	#define		FCK0_2				PWM0C,6  	   
	#define		FCK0_3				PWM0C,7 
  
PWM0TL		EQU		013H;0113H   
PWM0TH		EQU		014H;0114H   

PWM0PL		EQU		015H;0115H   
PWM0PH		EQU		016H;0116H

PWM0DL		EQU		017H;0117H   
PWM0DH		EQU		018H;0118H  

PWM0DTL		EQU		019H;0119H   
PWM0DTH		EQU		01AH;011AH  
 
PWMPSCON	EQU		01BH;011BH   
	#define		PWM0S0			PWMPSCON,0  
	#define		PWM0S1			PWMPSCON,1  
	#define		PWM01S0			PWMPSCON,2   
	#define		PWM01S1			PWMPSCON,3
	#define		PWM1S0			PWMPSCON,4
	#define		PWM1S1			PWMPSCON,5 
	
	#define		FPWM0S0				PWMPSCON,0  
	#define		FPWM0S1				PWMPSCON,1   
	#define		FPWM01S0			PWMPSCON,2   
	#define		FPWM01S1			PWMPSCON,3
	#define		FPWM1S0				PWMPSCON,4
	#define		FPWM1S1				PWMPSCON,5 

PWM1DL		EQU		01CH;011CH   
PWM1DH		EQU		01DH;011DH

;*****************************************************  
;BANK3-define
;*****************************************************
      
     
;*****************************************************   
;PIN-DEFINE   
;****************************************************   
;	    PA0	-1		14- PA1	                   *   
;	    PB7	-2		13- PA2	                   *   
;	    PB6	-3		12- PA3	                   *   
;	    VDD -4		11- VSS	                   *   
;	    PB5	-5		10- PB0	                   *   
;	    PB4	-6		9 - PB1	                   *   
;	    PB3	-7		8 - PB2	                   *   
;****************************************************      

