#ifndef __SN8P25231__H
#define __SN8P25231__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FLVD24 = 0x86:4;
sbit	FLVD36 = 0x86:5;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sfr	MSPSTAT = 0x90;
sbit	FCKE = 0x90:6;
sbit	FD_A = 0x90:5;
sbit	FP = 0x90:4;
sbit	FS = 0x90:3;
sbit	FRED_WRT = 0x90:2;
sbit	FBF = 0x90:0;
sfr	MSPM1 = 0x91;
sbit	FWCOL = 0x91:7;
sbit	FMSPOV = 0x91:6;
sbit	FMSPENB = 0x91:5;
sbit	FCKP = 0x91:4;
sbit	FSLRXCKP = 0x91:3;
sbit	FMSPWK = 0x91:2;
sbit	FGCEN = 0x91:1;
sfr	MSPBUF = 0x92;
sbit	FMSPBUF7 = 0x92:7;
sbit	FMSPBUF6 = 0x92:6;
sbit	FMSPBUF5 = 0x92:5;
sbit	FMSPBUF4 = 0x92:4;
sbit	FMSPBUF3 = 0x92:3;
sbit	FMSPBUF2 = 0x92:2;
sbit	FMSPBUF1 = 0x92:1;
sbit	FMSPBUF0 = 0x92:0;
sfr	MSPADR = 0x93;
sbit	FMSPADR7 = 0x93:7;
sbit	FMSPADR6 = 0x93:6;
sbit	FMSPADR5 = 0x93:5;
sbit	FMSPADR4 = 0x93:4;
sbit	FMSPADR3 = 0x93:3;
sbit	FMSPADR2 = 0x93:2;
sbit	FMSPADR1 = 0x93:1;
sbit	FMSPADR0 = 0x93:0;
sfr	CM0M = 0x9c;
sbit	FCMCH0 = 0x9c:0;
sbit	FCMCH1 = 0x9c:1;
sbit	FCMCH2 = 0x9c:2;
sbit	FCMCH3 = 0x9c:3;
sbit	FCM0S0 = 0x9c:4;
sbit	FCM0S1 = 0x9c:5;
sbit	FCM0OUT = 0x9c:6;
sbit	FCM0EN = 0x9c:7;
sfr	CM0M1 = 0x9d;
sbit	FCM0G = 0x9d:0;
sbit	FCM0OEN = 0x9d:1;
sbit	FCMDB0 = 0x9d:2;
sbit	FCMDB1 = 0x9d:3;
sbit	FTCHEN = 0x9d:7;
sfr	CM0M2 = 0x9e;
sbit	FTCHCM0 = 0x9e:0;
sbit	FTCHCM1 = 0x9e:1;
sbit	FTCHCM2 = 0x9e:2;
sbit	FTRS0 = 0x9e:4;
sbit	FTRS1 = 0x9e:5;
sbit	FTRS2 = 0x9e:6;
sbit	FTRS3 = 0x9e:7;
sfr	T1M = 0xa0;
sbit	FT1VCOV = 0xa0:0;
sbit	FT1OV = 0xa0:1;
sbit	FCPTStart = 0xa0:2;
sbit	FCPTCKS = 0xa0:3;
sbit	FT1rate0 = 0xa0:4;
sbit	FT1rate1 = 0xa0:5;
sbit	FT1rate2 = 0xa0:6;
sbit	FT1ENB = 0xa0:7;
sfr	T1CL = 0xa1;
sfr	T1CH = 0xa2;
sfr	T1VCL = 0xa3;
sfr	T1VCH = 0xa4;
sfr	TC0R0 = 0xa8;
sfr	TC0R1 = 0xa9;
sfr	TC0R2 = 0xaa;
sfr	TC0R3 = 0xab;
sfr	TC0R4 = 0xac;
sfr	TC0R5 = 0xad;
sfr	TC0R6 = 0xae;
sfr	TC0R7 = 0xaf;
sfr	SIOM = 0xb4;
sbit	FSENB = 0xb4:7;
sbit	FSTART = 0xb4:6;
sbit	FSRATE1 = 0xb4:5;
sbit	FSRATE0 = 0xb4:4;
sbit	FMLSB = 0xb4:3;
sbit	FSCKMD = 0xb4:2;
sbit	FCPOL = 0xb4:1;
sbit	FCPHA = 0xb4:0;
sfr	SIOR = 0xb5;
sfr	SIOB = 0xb6;
sfr	P0M = 0xb8;
sbit	FP00M = 0xb8:0;
sbit	FP01M = 0xb8:1;
sbit	FP02M = 0xb8:2;
sbit	FP03M = 0xb8:3;
sbit	FP04M = 0xb8:4;
sfr	PEDGE = 0xbf;
sbit	FP00G1 = 0xbf:4;
sbit	FP00G0 = 0xbf:3;
sfr	P1W = 0xc0;
sfr	P1M = 0xc1;
sbit	FP10M = 0xc1:0;
sbit	FP11M = 0xc1:1;
sbit	FP12M = 0xc1:2;
sbit	FP13M = 0xc1:3;
sbit	FP14M = 0xc1:4;
sbit	FP15M = 0xc1:5;
sbit	FP16M = 0xc1:6;
sbit	FP17M = 0xc1:7;
sfr	P5M = 0xc5;
sbit	FP50M = 0xc5:0;
sbit	FP51M = 0xc5:1;
sbit	FP52M = 0xc5:2;
sbit	FP53M = 0xc5:3;
sbit	FP54M = 0xc5:4;
sbit	FP55M = 0xc5:5;
sbit	FP56M = 0xc5:6;
sbit	FP57M = 0xc5:7;
sfr	INTRQ = 0xc8;
sbit	FP00IRQ = 0xc8:0;
sbit	FMSPIRQ = 0xc8:1;
sbit	FT1IRQ = 0xc8:2;
sbit	FSIOIRQ = 0xc8:3;
sbit	FT0IRQ = 0xc8:4;
sbit	FTC1IRQ = 0xc8:6;
sbit	FCM0IRQ = 0xc8:7;
sfr	INTEN = 0xc9;
sbit	FP00IEN = 0xc9:0;
sbit	FMSPIEN = 0xc9:1;
sbit	FT1IEN = 0xc9:2;
sbit	FSIOIEN = 0xc9:3;
sbit	FT0IEN = 0xc9:4;
sbit	FTC1IEN = 0xc9:6;
sbit	FCM0IEN = 0xc9:7;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	LPWS = 0xcd;
sbit	FLPWS0 = 0xcd:0;
sbit	FLPWS1 = 0xcd:1;
sbit	FLPWS2 = 0xcd:2;
sbit	FLPWS3 = 0xcd:3;
sbit	FLPWS4 = 0xcd:4;
sbit	FLPWS5 = 0xcd:5;
sbit	FLPWS6 = 0xcd:6;
sbit	FLPWS7 = 0xcd:7;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP00 = 0xd0:0;
sbit	FP01 = 0xd0:1;
sbit	FP02 = 0xd0:2;
sbit	FP03 = 0xd0:3;
sbit	FP04 = 0xd0:4;
sbit	FP05 = 0xd0:5;
sfr	P1 = 0xd1;
sbit	FP10 = 0xd1:0;
sbit	FP11 = 0xd1:1;
sbit	FP12 = 0xd1:2;
sbit	FP13 = 0xd1:3;
sbit	FP14 = 0xd1:4;
sbit	FP15 = 0xd1:5;
sbit	FP16 = 0xd1:6;
sbit	FP17 = 0xd1:7;
sfr	P5 = 0xd5;
sbit	FP50 = 0xd5:0;
sbit	FP51 = 0xd5:1;
sbit	FP52 = 0xd5:2;
sbit	FP53 = 0xd5:3;
sbit	FP54 = 0xd5:4;
sbit	FP55 = 0xd5:5;
sbit	FP56 = 0xd5:6;
sbit	FP57 = 0xd5:7;
sfr	T0M = 0xd8;
sbit	FT0RATE0 = 0xd8:4;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0ENB = 0xd8:7;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FPWMDR = 0xda:0;
sbit	FTC0rate0 = 0xda:4;
sbit	FTC0rate1 = 0xda:5;
sbit	FTC0rate2 = 0xda:6;
sbit	FTC0ENB = 0xda:7;
sfr	TC0C = 0xdb;
sfr	TC1M = 0xdc;
sbit	FPWM1OUT = 0xdc:0;
sbit	FTC1CKS0 = 0xdc:2;
sbit	FTC1rate0 = 0xdc:4;
sbit	FTC1rate1 = 0xdc:5;
sbit	FTC1rate2 = 0xdc:6;
sbit	FTC1ENB = 0xdc:7;
sfr	TC1C = 0xdd;
sfr	TC1R = 0xde;
sfr	STKP = 0xdf;
sbit	FSTKPB0 = 0xdf:0;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB2 = 0xdf:2;
sbit	FGIE = 0xdf:7;
sfr	P0UR = 0xe0;
sbit	FP00R = 0xe0:0;
sbit	FP01R = 0xe0:1;
sbit	FP02R = 0xe0:2;
sbit	FP03R = 0xe0:3;
sbit	FP04R = 0xe0:4;
sfr	P1UR = 0xe1;
sbit	FP10R = 0xe1:0;
sbit	FP11R = 0xe1:1;
sbit	FP12R = 0xe1:2;
sbit	FP13R = 0xe1:3;
sbit	FP14R = 0xe1:4;
sbit	FP15R = 0xe1:5;
sbit	FP16R = 0xe1:6;
sbit	FP17R = 0xe1:7;
sfr	P5UR = 0xe5;
sbit	FP50R = 0xe5:0;
sbit	FP51R = 0xe5:1;
sbit	FP52R = 0xe5:2;
sbit	FP53R = 0xe5:3;
sbit	FP54R = 0xe5:4;
sbit	FP55R = 0xe5:5;
sbit	FP56R = 0xe5:6;
sbit	FP57R = 0xe5:7;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	P1OC = 0xe9;
sbit	FP50OC = 0xe9:2;
sbit	FP51OC = 0xe9:3;
sbit	FP52OC = 0xe9:4;
sfr	TC1D = 0xea;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
