#ifndef __SN8F2283__H
#define __SN8F2283__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }


sfr		H	=	0x80;
sfr		L	=	0x81;
sfr		R	=	0x82;
sfr		Z	=	0x83;
sfr		Y	=	0x84;
sfr		PFLAG	=	0x86;
sbit		FZ	=	0x86:0;
sbit		FDC	=	0x86:1;
sbit		FC	=	0x86:2;
sbit		FNPD	=	0x86:6;
sbit		FNT0	=	0x86:7;
sfr		RBANK	=	0x87;
sbit		FRBNKS0	=	0x87:0;
sbit		FRBNKS1	=	0x87:1;
sfr		HL	=	0x90;
sfr		YZ	=	0x91;
sfr		CTRL	=	0x92;
sbit		FP0CTRL	=	0x92:0;
sbit		FP1CTRL	=	0x92:1;
sbit		FP5CTRL	=	0x92:2;
sbit		FRSEL0	=	0x92:3;
sbit		FRSEL1	=	0x92:4;
sbit		FLVDS0	=	0x92:5;
sbit		FLVDS1	=	0x92:6;
sfr		PCL	=	0x93;
sfr		PCH	=	0x94;
sfr		OSCM	=	0x95;
sbit		FSTPHX	=	0x95:1;
sbit		FCLKMD	=	0x95:2;
sbit		FCPUM0	=	0x95:3;
sbit		FCPUM1	=	0x95:4;
sfr		WDTR	=	0x96;
sfr		INTRQ	=	0x97;
sbit		FINT0IF	=	0x97:0;
sbit		FP50IF	=	0x97:1;
sbit		FP54IF	=	0x97:2;
sbit		FP0P1IF	=	0x97:3;
sbit		FT1IF	=	0x97:4;
sbit		FTC0IF	=	0x97:5;
sbit		FTM1IF	=	0x97:6;
sfr		INTEN	=	0x99;
sbit		FINT0IE	=	0x99:0;
sbit		FP50IE	=	0x99:1;
sbit		FP54IE	=	0x99:2;
sbit		FP0P1IE	=	0x99:3;
sbit		FT1IE	=	0x99:4;
sbit		FTC0IE	=	0x99:5;
sbit		FTM1IE	=	0x99:6;
sfr		REM_REG	=	0x9a;
sbit		FDRVS0	=	0x9a:0;
sbit		FDRVS1	=	0x9a:1;
sbit		FDRVS2	=	0x9a:2;
sbit		FELEEN	=	0x9a:3;
sbit		FDRVS4	=	0x9a:4;
sbit		FDRVS5	=	0x9a:5;
sbit		FDRVS6	=	0x9a:6;
sbit		FDRVS7	=	0x9a:7;
sfr		P0W	=	0x9b;
sbit		FP00W	=	0x9b:0;
sbit		FP01W	=	0x9b:1;
sbit		FP02W	=	0x9b:2;
sbit		FP03W	=	0x9b:3;
sbit		FP04W	=	0x9b:4;
sbit		FP05W	=	0x9b:5;
sfr		P1W	=	0x9c;
sbit		FP10W	=	0x9c:0;
sbit		FP11W	=	0x9c:1;
sbit		FP12W	=	0x9c:2;
sbit		FP13W	=	0x9c:3;
sbit		FP14W	=	0x9c:4;
sbit		FP15W	=	0x9c:5;
sfr		PEDGE	=	0x9f;
sbit		FPG0	=	0x9f:0;
sbit		FPG1	=	0x9f:1;
sbit		FINTS	=	0x9f:3;
sbit		FIRXO	=	0x9f:5;
sbit		FIRXEN	=	0x9f:6;
sfr		P0M0	=	0xa0;
sbit		FP00M0	=	0xa0:0;
sbit		FP01M0	=	0xa0:1;
sbit		FP02M0	=	0xa0:2;
sbit		FP03M0	=	0xa0:3;
sbit		FP04M0	=	0xa0:4;
sbit		FP05M0	=	0xa0:5;
sfr		P1M0	=	0xa1;
sbit		FP10M0	=	0xa1:0;
sbit		FP11M0	=	0xa1:1;
sbit		FP12M0	=	0xa1:2;
sbit		FP13M0	=	0xa1:3;
sbit		FP14M0	=	0xa1:4;
sbit		FP15M0	=	0xa1:5;
sfr		P5M0	=	0xa4;
sbit		FP50M0	=	0xa4:0;
sbit		FP54M0	=	0xa4:4;
sfr		P0	=	0xa5;
sbit		FP00	=	0xa5:0;
sbit		FP01	=	0xa5:1;
sbit		FP02	=	0xa5:2;
sbit		FP03	=	0xa5:3;
sbit		FP04	=	0xa5:4;
sbit		FP05	=	0xa5:5;
sfr		P1	=	0xa6;
sbit		FP10	=	0xa6:0;
sbit		FP11	=	0xa6:1;
sbit		FP12	=	0xa6:2;
sbit		FP13	=	0xa6:3;
sbit		FP14	=	0xa6:4;
sbit		FP15	=	0xa6:5;
sfr		P5	=	0xa9;
sbit		FP50	=	0xa9:0;
sbit		FP54	=	0xa9:4;
sfr		P0M1	=	0xaa;
sbit		FP00M1	=	0xaa:0;
sbit		FP01M1	=	0xaa:1;
sbit		FP02M1	=	0xaa:2;
sbit		FP03M1	=	0xaa:3;
sbit		FP04M1	=	0xaa:4;
sbit		FP05M1	=	0xaa:5;
sfr		P1M1	=	0xab;
sbit		FP10M1	=	0xab:0;
sbit		FP11M1	=	0xab:1;
sbit		FP12M1	=	0xab:2;
sbit		FP13M1	=	0xab:3;
sbit		FP14M1	=	0xab:4;
sbit		FP15M1	=	0xab:5;
sfr		P5M1	=	0xae;
sbit		FP50M1	=	0xae:0;
sbit		FP54M1	=	0xae:4;
sfr		T1M	=	0xb5;
sbit		FTC0GN	=	0xb5:0;
sbit		FT1GATE	=	0xb5:1;
sbit		FT1CK	=	0xb5:2;
sbit		FTP1SEL	=	0xb5:3;
sbit		FTP1S0	=	0xb5:4;
sbit		FTP1S1	=	0xb5:5;
sbit		FTP1S2	=	0xb5:6;
sbit		FTR1	=	0xb5:7;
sfr		T1C_L	=	0xb6;
sfr		T1C_H	=	0xb7;
sfr		TC0M	=	0xb8;
sbit		FPWMOUT	=	0xb8:0;
sbit		FBUZOUT	=	0xb8:1;
sbit		FTC0I0	=	0xb8:2;
sbit		FTC0I1	=	0xb8:3;
sbit		FTC0S0	=	0xb8:4;
sbit		FTC0S1	=	0xb8:5;
sbit		FTC0S2	=	0xb8:6;
sbit		FTC0TR	=	0xb8:7;
sfr		TC0C	=	0xb9;
sfr		TC0R	=	0xba;
sfr		TC0D_TC0H	=	0xbb;
sfr		PWM0DL	=	0xc0;
sfr		PWM0DH	=	0xc1;
sfr		PWM0PL	=	0xc2;
sfr		PWM0PH	=	0xc3;
sfr		PWM0EN	=	0xc4;
sbit		FPWM0EN	=	0xc4:0;
sbit		FPWM0OEN	=	0xc4:1;
sbit		FPWM01OEN	=	0xc4:2;
sbit		FPWM0M	=	0xc4:3;
sbit		FPWM1OEN	=	0xc4:4;
sbit		FTM1SEL8	=	0xc4:5;
sbit		FTM1GN	=	0xc4:6;
sbit		FTM1EN	=	0xc4:7;
sfr		PWM0C	=	0xc5;
sbit		FCK00	=	0xc5:0;
sbit		PCK01	=	0xc5:1;
sbit		FPWM0S0	=	0xc5:2;
sbit		FPWM0S1	=	0xc5:3;
sbit		FCK02	=	0xc5:6;
sbit		FCK03	=	0xc5:7;
sfr		PWM0TL	=	0xc6;
sfr		PWM0TH	=	0xc7;
sfr		PWM0DTL	=	0xc8;
sfr		PWM0DTH	=	0xc9;
sfr		PWMPSCON	=	0xca;
sfr		PWM1DL	=	0xd0;
sfr		PWM1DH	=	0xd1;
sfr		OPTION_REG	=	0xcc;
sbit		FP0SCANW	=	0xcc:0;
sbit		FP1SCANW	=	0xcc:1;
sbit		FP5SCANW	=	0xcc:2;
sbit		FIESEL	=	0xcc:3;
sbit		FWDTPER0	=	0xcc:4;
sbit		FWDTPRE1	=	0xcc:5;
sbit		FWDTPRE2	=	0xcc:6;
sbit		FWDTEN	=	0xcc:7;
sfr		MTPQ	=	0xd6;
sbit		FMTPPROFLAG	=	0xd6:1;
sbit		FMTPEARFLAG	=	0xd6:2;
sbit		FMTPCERSFLAG	=	0xd6:3;
sfr		MTPEN	=	0xd8;
sbit		FMTPRD	=	0xd8:0;
sbit		FMTPPRO	=	0xd8:1;
sbit		FMTPERA	=	0xd8:2;
sbit		FMTPCERS	=	0xd8:3;
sbit		FMTPCPEN	=	0xd8:5;
sfr		MTPAH	=	0xda;
sfr		MTPC	=	0xdb;
sbit		FPROSEL0	=	0xdb:0;
sbit		FPROSEL1	=	0xdb:1;
sbit		FPROSEL2	=	0xdb:2;
sbit		FPROSEL3	=	0xdb:3;
sbit		FPROSEL4	=	0xdb:4;
sbit		FPROCLKS0	=	0xdb:5;
sbit		FPROCLKS1	=	0xdb:6;
sfr		MTPAL	=	0xdc;
sfr		MTPD	=	0xde;
sfr		T1M1	=	0xe9;
sbit		FT1OVW	=	0xe9:0;
sbit		FT1OVS	=	0xe9:1;
sbit		FINT0W	=	0xe9:2;
sbit		FPWMW1	=	0xe9:3;
sbit		FPWMW2	=	0xe9:4;
sfr		REV0T0L	=	0xea;
sfr		REV0T0H	=	0xeb;
sfr		REV1T0L	=	0xec;
sfr		REV1T0H	=	0xed;
sfr		STKP	=	0xef;
sbit		FSTKPB0	=	0xef:0;
sbit		FSTKPB1	=	0xef:1;
sbit		FSTKPB2	=	0xef:2;
sbit		FLVD1D8	=	0xef:4;
sbit		FLVD2X	=	0xef:5;
sbit		FGIE	=	0xef:7;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#define SET_P3_INPUT_PULLUP __asm{Set_P3_Input_Pullup}
#endif
