/******************************************************************
file name:-HS26F1328-def.h
2020.06.08
def_cuiyn: 
/*' function <<==================================================/
        VSS -1 ------------20- VDD
        P00 -2 -|_|       -19- P47
        P01 -3 -          -18- P46
        P02 -4 -          -17- P45
        P03 -5 -          -16- P44
        P04 -6 -          -15- P43
        P05 -7 -          -14- P42
        P06 -8 -          -13- P41
        P10 -9 -          -12- P40
        P11 -10------------11- P12
        
/****************************************************************'*/
#ifndef __HS26F1328__H
#define __HS26F1328__H

/* function <<==================================================*/
void _Clr_WDT(void);
void _Clr_RAM(void);

/* function <<==================================================*/
#define NOP(X)  	__asm{	_NOP X }                    
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }    

#define	RESET			0u		//
#define	SET			  	1u		//
#define	I_ClrWdtr		0x5A

/* function <<==================================================*/
typedef unsigned char BYTE;
typedef unsigned char U8;
typedef unsigned char u8;

typedef unsigned long WORD;
typedef unsigned char U16;
typedef unsigned long u16;

typedef unsigned long long DWORD;
typedef unsigned long long U32;
typedef unsigned long long u32;

/* function <<==================================================*/



/* function <<==================================================*/
struct bitRegister{
	unsigned bit0:1;
	unsigned bit1:1;
	unsigned bit2:1;
	unsigned bit3:1;
	unsigned bit4:1;
	unsigned bit5:1;
	unsigned bit6:1;
	unsigned bit7:1;
};

/* function <<==================================================*/

sfr	L       = 0x80;
sfr	H       = 0x81;

sfr	R       = 0x82;
sfr	Z       = 0x83;

sfr	Y       = 0x84;
sfr	X       = 0x85;

sfr	PFLAG   = 0x86;
    sbit	FZ          = 0x86:0;
    sbit	FDC         = 0x86:1;
    sbit	FC          = 0x86:2;
    sbit	FNPD        = 0x86:6;
    sbit	FNTO        = 0x86:7;
    
sfr	RBANK   = 0x87;
    sbit	FRBANKS     = 0x87:0;
    sbit	FSBANKS1    = 0x87:6;
    sbit	FSBANKS2    = 0x87:7;
    
sfr	W0      = 0x88;
sfr	W1      = 0x89;
sfr	W2      = 0x8a;
sfr	W3      = 0x8b;

sfr	W4      = 0x8c;
sfr	W5      = 0x8d;
sfr	W6      = 0x8e;
sfr	W7      = 0x8f;
/* function <<==================================================*/
sfr	_HL     = 0x90;
sfr	_YZ     = 0x91;

sfr	PCL     = 0x93;
sfr	PCH     = 0x94;

sfr	OSCM    = 0x95;
    sbit	F8M32KSEL   = 0x95:0;
    sbit	FSTPHX      = 0x95:1;
    sbit	FCLKMD      = 0x95:2;
    sbit	FCPUM0      = 0x95:3;
    sbit	FCPUM1      = 0x95:4;
    sbit	FLRCSXT     = 0x95:6;
    sbit	FLRCS32K    = 0x95:7;
    
sfr	WDTR    = 0x96;

sfr	INTRQ0  = 0x97;
    sbit	FINT0IF     = 0x97:0;
    sbit	FINT1IF     = 0x97:1;
    sbit	FINT2IF     = 0x97:2;
    sbit	FADCIF      = 0x97:3;
    sbit	FT0IF       = 0x97:4;
    sbit	FTC0IF      = 0x97:5;
    sbit	FT2IF       = 0x97:6;
    sbit	FPBIF       = 0x97:7;
    
sfr	INTRQ1  = 0x98;
    sbit	FTM1IF      = 0x98:0;
    sbit	FTM2IF      = 0x98:1;
    sbit	FCMPIF      = 0x98:4;
    sbit	FI2CIF      = 0x98:6;
    sbit	FSPIIF      = 0x98:7;
    
sfr	INTEN0  = 0x99;
    sbit	FINT0IE     = 0x99:0;
    sbit	FINT1IE     = 0x99:1;
    sbit	FINT2IE     = 0x99:2;
    sbit	FADCIE      = 0x99:3;
    sbit	FT0IE       = 0x99:4;
    sbit	FTC0IE      = 0x99:5;
    sbit	FT2IE       = 0x99:6;
    sbit	FPBIE       = 0x99:7;
    
sfr	INTEN1  = 0x9a;
    sbit	FTM1IE      = 0x9A:0;
    sbit	FTM2IE      = 0x9A:1;
    sbit	FCMPIE      = 0x9A:4;
    sbit	FI2CIE      = 0x9A:6;
    sbit	FSPIIE      = 0x9A:7;
    
sfr	P0W     = 0x9b;
    sbit	FP06W       = 0x9b:6;
    sbit	FP05W       = 0x9b:5;
    sbit	FP04W       = 0x9b:4;
    sbit	FP03W       = 0x9b:3;
    sbit	FP02W       = 0x9b:2;
    sbit	FP01W       = 0x9b:1;
    sbit	FP00W       = 0x9b:0;
    
sfr	P1W     = 0x9c;
    sbit	FP12W       = 0x9c:2;
    sbit	FP11W       = 0x9c:1;
    sbit	FP10W       = 0x9c:0;
    
sfr	P4W     = 0x9e;
    sbit	FP47W       = 0x9e:7;
    sbit	FP46W       = 0x9e:6;
    sbit	FP45W       = 0x9e:5;
    sbit	FP44W       = 0x9e:4;
    sbit	FP43W       = 0x9e:3;
    sbit	FP42W       = 0x9e:2;
    sbit	FP41W       = 0x9e:1;
    sbit	FP40W       = 0x9e:0;
    
sfr	PEDGE   = 0x9f;
    sbit	FPG0        = 0x9f:0;
    sbit	FPG1        = 0x9f:1;
    
/* function <<==================================================*/
sfr	P0M     = 0xa0;
    sbit	FP00M       = 0xa0:0;
    sbit	FP01M       = 0xa0:1;
    sbit	FP02M       = 0xa0:2;
    sbit	FP03M       = 0xa0:3;
    sbit	FP04M       = 0xa0:4;
    sbit	FP05M       = 0xa0:5;
    sbit	FP06M       = 0xa0:6;
    
sfr	P1M     = 0xa1;
    sbit	FP10M       = 0xa1:0;
    sbit	FP11M       = 0xa1:1;
    sbit	FP12M       = 0xa1:2;
    
sfr	P4M     = 0xa3;
    sbit	FP40M       = 0xa3:0;
    sbit	FP41M       = 0xa3:1;
    sbit	FP42M       = 0xa3:2;
    sbit	FP43M       = 0xa3:3;
    sbit	FP44M       = 0xa3:4;
    sbit	FP45M       = 0xa3:5;
    sbit	FP46M       = 0xa3:6;
    sbit	FP47M       = 0xa3:7;
    
sfr	P0      = 0xa5;
    sbit	FP00        = 0xa5:0;
    sbit	FP01        = 0xa5:1;
    sbit	FP02        = 0xa5:2;
    sbit	FP03        = 0xa5:3;
    sbit	FP04        = 0xa5:4;
    sbit	FP05        = 0xa5:5;
    sbit	FP06        = 0xa5:6;
    
sfr	P1      = 0xa6;
    sbit	FP10        = 0xa6:0;
    sbit	FP11        = 0xa6:1;
    sbit	FP12        = 0xa6:2;
    
sfr	P4      = 0xa8;
    sbit	FP40        = 0xa8:0;
    sbit	FP41        = 0xa8:1;
    sbit	FP42        = 0xa8:2;
    sbit	FP43        = 0xa8:3;
    sbit	FP44        = 0xa8:4;
    sbit	FP45        = 0xa8:5;
    sbit	FP46        = 0xa8:6;
    sbit	FP47        = 0xa8:7;
    
sfr	P0UR    = 0xaa;
    sbit	FP00UR      = 0xaa:0;
    sbit	FP01UR      = 0xaa:1;
    sbit	FP02UR      = 0xaa:2;
    sbit	FP03UR      = 0xaa:3;
    sbit	FP04UR      = 0xaa:4;
    sbit	FP05UR      = 0xaa:5;
    sbit	FP06UR      = 0xaa:6;
    
sfr	P1UR    = 0xab;
    sbit	FP10UR      = 0xab:0;
    sbit	FP11UR      = 0xab:1;
    sbit	FP12UR      = 0xab:2;
    
sfr	P4UR    = 0xad;
    sbit	FP40UR      = 0xad:0;
    sbit	FP41UR      = 0xad:1;
    sbit	FP42UR      = 0xad:2;
    sbit	FP43UR      = 0xad:3;
    sbit	FP44UR      = 0xad:4;
    sbit	FP45UR      = 0xad:5;
    sbit	FP46UR      = 0xad:6;
    sbit	FP47UR      = 0xad:7;
    
sfr	PREMC   = 0xaf;

/* function <<==================================================*/
sfr	PWM0DL  = 0xb5;
sfr	PWM0DH  = 0xb6;

sfr	PWM0PL  = 0xb7;
sfr	PWM0PH  = 0xb8;

sfr	PWM0EN  = 0xb9;
    sbit	FPWM0_EN    = 0xb9:0;
    sbit	FPWM0_OEN   = 0xb9:1;
    sbit	FPWM01_OEN  = 0xb9:2;
    sbit	FPWM0M      = 0xb9:3;
    sbit	FPWM1_OEN   = 0xb9:4;
    sbit	FTM1SEL8    = 0xb9:5;
    sbit	FTM1EN      = 0xb9:7;
    
sfr	PWM0C   = 0xba;
    sbit	FCK0_0      = 0xba:0;
    sbit	FCK0_1      = 0xba:1;
    sbit	FPWM0S_0    = 0xba:2;
    sbit	FPWM0S_1    = 0xba:3;
    sbit	FCK0_2      = 0xba:6;
    sbit	FCK0_3      = 0xba:7;
    
sfr	PWM0TL  = 0xbb;
sfr	PWM0TH  = 0xbc;

sfr	PWM0DTL = 0xbd;
sfr	PWM0DTH = 0xbe;

sfr	PWMPSC  = 0xbf;
    sbit	FPWM0S0     = 0xbf:0;
    sbit	FPWM01S0    = 0xbf:1;
    sbit	FPWM1S0     = 0xbf:2;
    
/* function <<==================================================*/
sfr	ADPCON1 = 0xc5;
    sbit	FADPC10     = 0xc5:0;
    sbit	FADPC11     = 0xc5:1;
    sbit	FADPC12     = 0xc5:2;
    sbit	FADPC13     = 0xc5:3;
    
sfr	ADPCON  = 0xc7;
    sbit	FADPC7       = 0xc7:7;
    sbit	FADPC6       = 0xc7:6;
    sbit	FADPC5       = 0xc7:5;
    sbit	FADPC4       = 0xc7:4;
    sbit	FADPC3       = 0xc7:3;
    sbit	FADPC2       = 0xc7:2;
    sbit	FADPC1       = 0xc7:1;
    sbit	FADPC0       = 0xc7:0;
    
sfr	ADM     = 0xc8;
    sbit	FADENB      = 0xc8:7;
    sbit	FADS        = 0xc8:6;
    sbit	FEOC        = 0xc8:5;
    sbit	FGCHS       = 0xc8:4;
    sbit	FCHS2       = 0xc8:2;
    sbit	FCHS1       = 0xc8:1;
    sbit	FCHS0       = 0xc8:0;
    
sfr	ADB     = 0xc9;
    sbit	FADB11      = 0xc9:7;
    sbit	FADB10      = 0xc9:6;
    sbit	FADB9       = 0xc9:5;
    sbit	FADB8       = 0xc9:4;
    sbit	FADB7       = 0xc9:3;
    sbit	FADB6       = 0xc9:2;
    sbit	FADB5       = 0xc9:1;
    sbit	FADB4       = 0xc9:0;
    
sfr	ADR     = 0xca;
    sbit	FADCKS1     = 0xca:6;
    sbit	FADCKS0     = 0xca:4;
    sbit	FADB3       = 0xca:3;
    sbit	FADB2       = 0xca:2;
    sbit	FADB1       = 0xca:1;
    sbit	FADB0       = 0xca:0;
    
sfr	ADT     = 0xcb;
    sbit	FADTS0      = 0xcb:4;
    sbit	FADT3       = 0xcb:3;
    sbit	FADT2       = 0xcb:2;
    sbit	FADT1       = 0xcb:1;
    sbit	FADT0       = 0xcb:0;
    
sfr	WDTC    = 0xcc;
    sbit	FWDT_EN     = 0xcc:7;
    sbit	FWDT_PRE2   = 0xcc:6;
    sbit	FWDT_PRE1   = 0xcc:5;
    sbit	FWDT_PRE0   = 0xcc:4;
    
sfr	VREFH   = 0xce;
    sbit	FEVHENB     = 0xce:7;
    sbit	FVHS1       = 0xce:1;
    sbit	FVHS0       = 0xce:0;
    
sfr	LVDC    = 0xcf;
    sbit	FLVDTE      = 0xcf:7;
    
/* function <<==================================================*/
sfr	P0PD    = 0xd0;
    sbit	FP00PD      = 0xd0:0;
    sbit	FP01PD      = 0xd0:1;
    sbit	FP02PD      = 0xd0:2;
    sbit	FP03PD      = 0xd0:3;
    sbit	FP04PD      = 0xd0:4;
    sbit	FP05PD      = 0xd0:5;
    sbit	FP06PD      = 0xd0:6;
    
sfr	P1PD    = 0xd1;
    sbit	FP10PD      = 0xd1:0;
    sbit	FP11PD      = 0xd1:1;
    sbit	FP12PD      = 0xd1:2;
    
sfr	P4PD    = 0xd3;
    sbit	FP40PD      = 0xd3:0;
    sbit	FP41PD      = 0xd3:1;
    sbit	FP42PD      = 0xd3:2;
    sbit	FP43PD      = 0xd3:3;
    sbit	FP44PD      = 0xd3:4;
    sbit	FP45PD      = 0xd3:5;
    sbit	FP46PD      = 0xd3:6;
    sbit	FP47PD      = 0xd3:7;
    
sfr	TKC0    = 0xd5;
    sbit	FTKEN       = 0xd5:7;
    sbit	FTKST       = 0xd5:6;
    sbit	FTKGCHS     = 0xd5:5;
    sbit	FCHRVS      = 0xd5:4;
    sbit	FTKPS_3     = 0xd5:3;
    sbit	FTKPS_2     = 0xd5:2;
    sbit	FTKPS_1     = 0xd5:1;
    sbit	FTKPS_0     = 0xd5:0;
    
sfr	TK16DH  = 0xd6;
sfr	TK16DL  = 0xd7;

sfr	TKC1    = 0xd8;
    sbit	FCCFLT_2    = 0xd8:6;
    sbit	FCCFLT_1    = 0xd8:5;
    sbit	FCCFLT_0    = 0xd8:4;
    sbit	FDCTS_1     = 0xd8:1;
    sbit	FDCTS_0     = 0xd8:0;
    
sfr	TKC2    = 0xd9;
    sbit	FCTS_0      = 0xd9:0;
    sbit	FCTS_1      = 0xd9:1;
    sbit	FCTS_2      = 0xd9:2;
    sbit	FCTS_3      = 0xd9:3;
    
sfr	TKC3    = 0xda;
    sbit	TKCMOD0     = 0xda:7;
    sbit	FCPSV_1     = 0xda:4;
    sbit	FCPSV_0     = 0xda:3;
    sbit	FCVREFS_1   = 0xda:1;
    sbit	FCVREFS_0   = 0xda:0;
    
sfr	TKSTA   = 0xdb;
    sbit	FTMOUT      = 0xdb:7;
    sbit	FTKINTIF    = 0xdb:6;
    sbit	FTKINTIE    = 0xdb:5;
    sbit	FDCMPO      = 0xdb:3;
    sbit	FACMPO      = 0xdb:2;
    sbit	FSACMPO     = 0xdb:1;
    
sfr	TKPDH   = 0xdc;
sfr	TKPDL   = 0xdd;

sfr	ADF1    = 0xde;
sfr	ADF0    = 0xdf;
/* function <<==================================================*/
sfr	P0OD    = 0xe0;
    sbit	FP00OD      = 0xe0:0;
    sbit	FP01OD      = 0xe0:1;
    sbit	FP02OD      = 0xe0:2;
    sbit	FP03OD      = 0xe0:3;
    sbit	FP04OD      = 0xe0:4;
    sbit	FP05OD      = 0xe0:5;
    sbit	FP06OD      = 0xe0:6;
    
sfr	P1OD    = 0xe1;
    sbit	FP10OD      = 0xe1:0;
    sbit	FP11OD      = 0xe1:1;
    sbit	FP12OD      = 0xe1:2;
    
sfr	P4OD    = 0xe3;
    sbit	FP40OD      = 0xe3:0;
    sbit	FP41OD      = 0xe3:1;
    sbit	FP42OD      = 0xe3:2;
    sbit	FP43OD      = 0xe3:3;
    sbit	FP44OD      = 0xe3:4;
    sbit	FP45OD      = 0xe3:5;
    sbit	FP46OD      = 0xe3:6;
    sbit	FP47OD      = 0xe3:7;
    
sfr	SMTS    = 0xe5;
    sbit	FSMTS0      = 0xe5:0;
    sbit	FSMTS1      = 0xe5:1;
    sbit	FSMTS4      = 0xe5:3;
    
sfr	TC0D2   = 0xe6;
sfr	TC0M1   = 0xe7;
    sbit	FPWM1EN      = 0xe7:0;
    sbit	FPWM2EN      = 0xe7:1;
    sbit	FPWM0S1      = 0xe7:5;
    sbit	FPWM1S1      = 0xe7:6;
    sbit	FPWM2S1      = 0xe7:7;
    
sfr	PWM2DL  = 0xe8;
sfr	PWM2DH  = 0xe9;

sfr	TC0M    = 0xea;
    sbit	FTC0TR      = 0xea:7;
    sbit	FTC0S2      = 0xea:6;
    sbit	FTC0S1      = 0xea:5;
    sbit	FTC0S0      = 0xea:4;
    sbit	FTCCKS      = 0xea:3;
    sbit	FINT0CK     = 0xea:2;
    sbit	FPWM0       = 0xea:0;
    
sfr	TC0R    = 0xeb;

sfr	TC0CL   = 0xec;
sfr	TC0CH   = 0xed;

sfr	TC0D1   = 0xee;

sfr	STKP = 0xef;
    sbit	FGIE        = 0xef:7;
    sbit	FSTKPB2     = 0xef:2;
    sbit	FSTKPB1     = 0xef:1;
    sbit	FSTKPB0     = 0xef:0;
    
/* function <<==================================================*/
sfr	STK7L   = 0xf0;
sfr	STK7H   = 0xf1;
sfr	STK6L   = 0xf2;
sfr	STK6H   = 0xf3;

sfr	STK5L   = 0xf4;
sfr	STK5H   = 0xf5;
sfr	STK4L   = 0xf6;
sfr	STK4H   = 0xf7;

sfr	STK3L   = 0xf8;
sfr	STK3H   = 0xf9;
sfr	STK2L   = 0xfa;
sfr	STK2H   = 0xfb;

sfr	STK1L   = 0xfc;
sfr	STK1H   = 0xfd;
sfr	STK0L   = 0xfe;
sfr	STK0H   = 0xff;


/* BANK1 function <<==================================================*/

sfr	PWM5DL  = 0xb3;
sfr	PWM5DH  = 0xb4;

sfr	PWM3DL  = 0xb5;
sfr	PWM3DH  = 0xb6;

sfr	PWM3PL  = 0xb7;
sfr	PWM3PH  = 0xb8;

sfr	PWM3EN  = 0xb9;
    sbit	FPWM3_EN    = 0xb9:0;
    sbit	FPWM3_OEN   = 0xb9:1;
    sbit	FPWM31_OEN  = 0xb9:2;
    sbit	FPWM3M      = 0xb9:3;
    sbit	FPWM5_OEN   = 0xb9:4;
    sbit	FTM2SEL8    = 0xb9:5;
    sbit	FTM2SEL16   = 0xb9:6;
    sbit	FTM2EN      = 0xb9:7;
    
sfr	PWM3C   = 0xba;
    sbit	FCK3_0      = 0xba:0;
    sbit	FCK3_1      = 0xba:1;
    sbit	FPWM3S_0    = 0xba:2;
    sbit	FPWM3S_1    = 0xba:3;
    sbit	FCK3_2      = 0xba:6;
    sbit	FCK3_3      = 0xba:7;
    
sfr	PWM3TL  = 0xbb;
sfr	PWM3TH  = 0xbc;

sfr	PWM3DTL = 0xbd;
sfr	PWM3DTH = 0xbe;

sfr	PWM3PSC = 0xbf;
    sbit	FPWM3S      = 0xbf:0;
    sbit	FPWM31S     = 0xbf:1;
    sbit	FPWM5S      = 0xbf:2;


/* BANK1 function <<==================================================*/

sfr	P0SC    = 0xc0;
    sbit	FP06SC      = 0xc0:6;
    sbit	FP05SC      = 0xc0:5;
    sbit	FP04SC      = 0xc0:4;
    sbit	FP03SC      = 0xc0:3;
    sbit	FP02SC      = 0xc0:2;
    sbit	FP01SC      = 0xc0:1;
    sbit	FP00SC      = 0xc0:0;

sfr	P4SC    = 0xc1;
    sbit	FP47SC      = 0xc1:7;
    sbit	FP46SC      = 0xc1:6;
    sbit	FP45SC      = 0xc1:5;
    sbit	FP44SC      = 0xc1:4;
    sbit	FP43SC      = 0xc1:3;
    sbit	FP42SC      = 0xc1:2;
    sbit	FP41SC      = 0xc1:1;
    sbit	FP40SC      = 0xc1:0;

sfr	P0IS    = 0xc2;
    sbit	FP03IS      = 0xc2:3;
    sbit	FP02IS      = 0xc2:2;
    sbit	FP01IS      = 0xc2:1;
    sbit	FP00IS      = 0xc2:0;
    
sfr	P1IS    = 0xc3;
    sbit	FP13IS      = 0xc3:3;
    sbit	FP12IS      = 0xc3:2;
    sbit	FP11IS      = 0xc3:1;
    sbit	FP10IS      = 0xc3:0;
    
sfr	P4IS    = 0xc5;
    sbit	FP43IS      = 0xc5:3;
    sbit	FP42IS      = 0xc5:2;
    sbit	FP41IS      = 0xc5:1;
    sbit	FP40IS      = 0xc5:0;
    
sfr	TL0M    = 0xc7;
    sbit	FT2TR       = 0xc7:7;
    sbit	FT2WC       = 0xc7:6;
    sbit	FTP2S2      = 0xc7:5;
    sbit	FTP2S1      = 0xc7:4;
    sbit	FTP2S0      = 0xc7:3;

sfr	TL0C    = 0xc8;

sfr	T0M     = 0xc9;
    sbit	FT0TR       = 0xc9:7;
    sbit	FTP0S2      = 0xc9:6;
    sbit	FTP0S1      = 0xc9:5;
    sbit	FTP0S0      = 0xc9:4;
    sbit	FTP0SEL     = 0xc9:3;
    sbit	FT0CK       = 0xc9:2;
    sbit	FTC0GN      = 0xc9:0;
    
sfr	T0L     = 0xca;
sfr	T0H     = 0xcb;

sfr	T0M1    = 0xcc;
    sbit	FPWMW2      = 0xcc:4;
    sbit	FPWMW1      = 0xcc:3;
    sbit	FINT0W      = 0xcc:2;
    sbit	FT0OVS      = 0xcc:1;
    sbit	FT0GN       = 0xcc:0;

sfr	TIRCF   = 0xce;
    
/* BANK1 function <<==================================================*/

sfr	I2CCON  = 0xd0;
    sbit	FI2CEN      = 0xd0:0;
    sbit	FI2CPU      = 0xd0:1;
    sbit	FCKP        = 0xd0:2;
    sbit	FTXAK       = 0xd0:3;
    sbit	FSRW        = 0xd0:4;
    sbit	FHBB        = 0xd0:5;
    sbit	FHAAS       = 0xd0:6;
    sbit	FHCF        = 0xd0:7;
    
sfr	I2CADR  = 0xd1;
sfr	I2CBUF  = 0xd2;
sfr	I2CTOV  = 0xd3;
    sbit	FTOS0       = 0xd3:0;
    sbit	FTOS1       = 0xd3:1;
    sbit	FTOS2       = 0xd3:2;
    sbit	FTOVF       = 0xd3:6;
    sbit	FTOVEN      = 0xd3:7;
   
sfr	TK1C0   = 0xd5;
    sbit	FTK1EN      = 0xd5:7;
    sbit	FTK1ST      = 0xd5:6;
    sbit	FTK1GCHS    = 0xd5:5;
    sbit	FCHRVS1     = 0xd5:4;
    sbit	FTK1PS3     = 0xd5:3;
    sbit	FTK1PS2     = 0xd5:2;
    sbit	FTK1PS1     = 0xd5:1;
    sbit	FTK1PS0     = 0xd5:0;

sfr	TK1DH   = 0xd6;
sfr	TK1DL   = 0xd7;

sfr	TK1C1   = 0xd8;
    sbit	FCCFLT1_2   = 0xd8:6;
    sbit	FCCFLT1_1   = 0xd8:5;
    sbit	FCCFLT1_0   = 0xd8:4;
    sbit	FDCTS1_1    = 0xd8:1;
    sbit	FDCTS1_0    = 0xd8:0;
    
sfr	TK1C2   = 0xd9;
    sbit	FCTS1_0     = 0xd9:0;
    sbit	FCTS1_1     = 0xd9:1;
    sbit	FCTS1_2     = 0xd9:2;
    sbit	FCTS1_3     = 0xd9:3;
    sbit	FTK1CAPSEL_0= 0xd9:4;
    sbit	FTK1CAPSEL_1= 0xd9:5;
    sbit	FTK1CAPSEL_2= 0xd9:6;
    sbit	FTK1CAPSEL_3= 0xd9:7;
    
sfr	TK1C3   = 0xda;
    sbit	TK1CMOD0    = 0xda:7;
    sbit	FCPSV1_1    = 0xda:4;
    sbit	FCPSV1_0    = 0xda:3;
    sbit	FCVREFS1_1  = 0xda:1;
    sbit	FCVREFS1_0  = 0xda:0;
    
sfr	TK1STA  = 0xdb;
    sbit	FTKOUT1     = 0xdb:7;
    sbit	FTK1INTIF   = 0xdb:6;
    sbit	FTK1INTIE   = 0xdb:5;
    sbit	FDCMPO1     = 0xdb:3;
    sbit	FACMPO1     = 0xdb:2;
    sbit	FSACMPO1    = 0xdb:1;
    
sfr	TK1PDH  = 0xdc;
sfr	TK1PDL  = 0xdd;
/* BANK1 function <<==================================================*/

sfr	RCSTA   = 0xe0; //
sfr	TXREG   = 0xe1; //

sfr	RCREG   = 0xe2; //
sfr	TXSTA   = 0xe3; //

sfr	SPBRG   = 0xe4; //
sfr	SPBRGH  = 0xe5; //

sfr	BANDCTL = 0xe6; //
    
sfr	SIMC0   = 0xe7;
    sbit	FSPIM2      = 0xe7:7;
    sbit	FSPIM1      = 0xe7:6;
    sbit	FSPIM0      = 0xe7:5;
    sbit	FSPIEN      = 0xe7:1;

sfr	SIMC1   = 0xe8;

sfr	SIMD    = 0xea;

sfr	ITFACES = 0xed; //


/* BANK2 function <<==================================================*/
sfr	LFSEL   = 0xb2; 
    sbit	FLFSEL0     = 0xb2:0;
    sbit	FLFSEL1     = 0xb2:1;
    sbit	FLFSEL2     = 0xb2:2;

sfr	EADRL   = 0xe0; //
    
sfr	EECON1  = 0xe1; //
    sbit	FREADEE     = 0xe1:0;
    sbit	FPROGEE     = 0xe1:1;
    sbit	FERASEEE    = 0xe1:2;
    sbit	FERSALLEE   = 0xe1:3;
    sbit	FTIMEEE     = 0xe1:6;
    
sfr	EDATL   = 0xe2; 

sfr	CMPCON  = 0xe3; 
sfr	CMPC	= 0xe3;
    sbit	FCOPOL      = 0xe3:1;
    sbit	FCVENH      = 0xe3:2;
    sbit	FCVENL      = 0xe3:3;
    sbit	FCODEB      = 0xe3:4;
    sbit	FFTCKS      = 0xe3:5;
    sbit	FC0MIF      = 0xe3:6;
    sbit	FCMPEN      = 0xe3:7;

sfr	CMPM    = 0xe4; 
    sbit	FVRS0       = 0xe4:0;
    sbit	FVRS1       = 0xe4:1;
    sbit	FVRS2       = 0xe4:2;
    sbit	FVRS3       = 0xe4:3;
    sbit	FXRVSEL     = 0xe4:4;
    sbit	FCPINS0     = 0xe4:5;
    sbit	FCPINS1     = 0xe4:6;
    sbit	FCMPSEL     = 0xe4:7;

sfr	OPAM    = 0xe5; 
sfr	OPAM1   = 0xe6; 

sfr	OPAMC   = 0xe7; 
sfr	OPAMC1  = 0xe8; 

sfr	FLER    = 0xe9; 

sfr	FADRH   = 0xea; 
sfr	FADRL   = 0xeb; 

sfr	FCON1   = 0xec; 
sfr	FCON2   = 0xed; 

sfr	FDATH   = 0xee; 
sfr	FDATL   = 0xef; 

/* function <<==================================================*/
#define SLEEPMODE   __asm{SleepMode}
#define GREENMODE   __asm{GreenMode}
#define SLOWMODE    __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
//#define SET_P3_INPUT_PULLUP __asm{Set_P3_Input_Pullup}

/* function <<==================================================*/
#define HIBYTE(wval)		*(((BYTE*)(&wval))+1)//16-bit数据 高8位
#define LWBYTE(wval)		*(((BYTE*)(&wval))+0)//16-bit数据 低8位

#define HIWORD(wval)		*(((WORD*)(&wval))+1)//32-bit数据 高8位
#define LWWORD(wval)		*(((WORD*)(&wval))+0)//32-bit数据 低8位

/* function <<==================================================*/
#endif

