#ifndef __SN8P2839__H
#define __SN8P2839__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	X = 0x85;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FLVD24 = 0x86:4;
sbit	FLVD36 = 0x86:5;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sbit	FRBNKS1 = 0x87:1;
sbit	FRBNKS2 = 0x87:2;
sbit	FRBNKS3 = 0x87:3;
sfr	LCDM = 0x89;
sbit	FLCDENB = 0x89:0;
sbit	FP2SEG = 0x89:2;
sbit	FRCLK = 0x89:3;
sbit	FRES0 = 0x89:6;
sbit	FRES1 = 0x89:7;
sfr	CPM = 0x8A;
sbit	FAREGEN1 = 0x8A:0;
sbit	FAREGEN2 = 0x8A:1;
sfr	CPCKS = 0x8B;
sbit	FCPCKS0 = 0x8B:0;
sbit	FCPCKS1 = 0x8B:1;
sfr	CALIHRCH = 0x8C;
sbit	FCALIHRCH0 = 0x8C:0;
sbit	FCALIHRCH1 = 0x8C:1;
sbit	FCALIHRCH2 = 0x8C:2;
sbit	FTC1CALCKS = 0x8C:6;
sbit	FCALSTART = 0x8C:7;
sfr	CALIHRCL = 0x8D;
sbit	FCALIHRCL0 = 0x8D:0;
sbit	FCALIHRCL1 = 0x8D:1;
sbit	FCALIHRCL2 = 0x8D:2;
sbit	FCALIHRCL3 = 0x8D:3;
sbit	FCALIHRCL4 = 0x8D:4;
sbit	FCALIHRCL5 = 0x8D:5;
sfr	TRIM2 = 0x8E;
sbit	FDVDDR_0 = 0x8E:0;
sbit	FDVDDR_1 = 0x8E:1;
sbit	FDVDDR_2 = 0x8E:2;
sbit	FDVDDR_3 = 0x8E:3;
sfr	TRIM1 = 0x8F;
sbit	FAVDDR2_0 = 0x8F:0;
sbit	FAVDDR2_1 = 0x8F:1;
sbit	FAVDDR2_2 = 0x8F:2;
sbit	FAVDDR2_3 = 0x8F:3;
sbit	FAVDDR1_0 = 0x8F:4;
sbit	FAVDDR1_1 = 0x8F:5;
sbit	FAVDDR1_2 = 0x8F:6;
sbit	FAVDDR1_3 = 0x8F:7;
sfr	STK15L = 0x90;
sfr	STK15H = 0x91;
sfr	STK14L = 0x92;
sfr	STK14H = 0x93;
sfr	STK13L = 0x94;
sfr	STK13H = 0x95;
sfr	STK12L = 0x96;
sfr	STK12H = 0x97;
sfr	STK11L = 0x98;
sfr	STK11H = 0x99;
sfr	STK10L = 0x9a;
sfr	STK10H = 0x9b;
sfr	STK9L = 0x9c;
sfr	STK9H = 0x9d;
sfr	STK8L = 0x9e;
sfr	STK8H = 0x9f;
sfr	STK7L = 0xa0;
sfr	STK7H = 0xa1;
sfr	STK6L = 0xa2;
sfr	STK6H = 0xa3;
sfr	STK5L = 0xa4;
sfr	STK5H = 0xa5;
sfr	STK4L = 0xa6;
sfr	STK4H = 0xa7;
sfr	STK3L = 0xa8;
sfr	STK3H = 0xa9;
sfr	STK2L = 0xaa;
sfr	STK2H = 0xab;
sfr	STK1L = 0xac;
sfr	STK1H = 0xad;
sfr	STK0L = 0xae;
sfr	STK0H = 0xaf;
sfr	ADM = 0xb1;
sbit	FCHS0 = 0xb1:0;
sbit	FCHS1 = 0xb1:1;
sbit	FCHS2 = 0xb1:2;
sbit	FGCHS = 0xb1:4;
sbit	FEOC = 0xb1:5;
sbit	FADS = 0xb1:6;
sbit	FADENB = 0xb1:7;
sfr	ADB = 0xb2;
sfr	ADR = 0xb3;
sbit	FADB0 = 0xb3:0;
sbit	FADB1 = 0xb3:1;
sbit	FADB2 = 0xb3:2;
sbit	FADB3 = 0xb3:3;
sbit	FADCKS0 = 0xb3:4;
sbit	FADCKS1 = 0xb3:5;
sbit	FADCKS2 = 0xb3:6;
sfr	SIOM = 0xb4;
sbit	FCPHA = 0xb4:0;
sbit	FCPOL = 0xb4:1;
sbit	FSCKMD = 0xb4:2;
sbit	FMLSB = 0xb4:3;
sbit	FSRATE0 = 0xb4:4;
sbit	FSRATE1 = 0xb4:5;
sbit	FSTART = 0xb4:6;
sbit	FSENB = 0xb4:7;
sfr	SIOR = 0xb5;
sfr	SIOB = 0xb6;
sfr	P0M = 0xb8;
sbit	FP00M = 0xb8:0;
sbit	FP01M = 0xb8:1;
sfr	PGIA2CKS = 0xb9;
sfr	PGIA2M = 0xba;
sbit	FPGIA2ENB = 0xba:0;
sbit	FP3GS0 = 0xba:1;
sbit	FP3GS1 = 0xba:2;
sbit	FP4GS0 = 0xba:4;
sbit	FP4GS1 = 0xba:5;
sbit	FP4GS2 = 0xba:6;
sbit	FP4GS3 = 0xba:7;
sfr	PGIA1CKS = 0xbb;
sfr	PGIA1M = 0xbc;
sbit	FPGIA1ENB = 0xbc:0;
sbit	FP1GS0 = 0xbc:1;
sbit	FP1GS1 = 0xbc:2;
sbit	FP2GS0 = 0xbc:4;
sbit	FP2GS1 = 0xbc:5;
sbit	FP2GS2 = 0xbc:6;
sbit	FP2GS3 = 0xbc:7;
sfr	OPM = 0xbd;
sbit	FOP1ENB = 0xbd:0;
sbit	FOP2ENB = 0xbd:1;
sbit	FOP1UGB = 0xbd:2;
sbit	FOP2UGB = 0xbd:3;
sfr	P4CON = 0xBE;
sbit	FP4CON0 = 0xBE:0;
sbit	FP4CON1 = 0xBE:1;
sbit	FP4CON2 = 0xBE:2;
sbit	FP4CON3 = 0xBE:3;
sbit	FP4CON4 = 0xBE:4;
sbit	FP4CON5 = 0xBE:5;
sbit	FP4CON6 = 0xBE:6;
sfr	PEDGE = 0xbf;
sbit	FP00G0 = 0xbf:0;
sbit	FP00G1 = 0xbf:1;
sbit	FP01G0 = 0xbf:2;
sbit	FP01G1 = 0xbf:3;
sfr	P1W = 0xc0;
sbit	FP10W = 0xc0:0;
sbit	FP11W = 0xc0:1;
sbit	FP12W = 0xc0:2;
sbit	FP13W = 0xc0:3;
sbit	FP14W = 0xc0:4;
sbit	FP15W = 0xc0:5;
sfr	P1M = 0xc1;
sbit	FP10M = 0xc1:0;
sbit	FP11M = 0xc1:1;
sbit	FP12M = 0xc1:2;
sbit	FP13M = 0xc1:3;
sbit	FP14M = 0xc1:4;
sbit	FP15M = 0xc1:5;
sfr	P2M = 0xc2;
sbit	FP20M = 0xc2:0;
sbit	FP21M = 0xc2:1;
sbit	FP22M = 0xc2:2;
sbit	FP23M = 0xc2:3;
sfr	P4M = 0xc4;
sbit	FP40M = 0xc4:0;
sbit	FP41M = 0xc4:1;
sbit	FP42M = 0xc4:2;
sbit	FP43M = 0xc4:3;
sbit	FP44M = 0xc4:4;
sbit	FP45M = 0xc4:5;
sbit	FP46M = 0xc4:6;
sfr	P5M = 0xc5;
sbit	FP50M = 0xc5:0;
sbit	FP51M = 0xc5:1;
sbit	FP52M = 0xc5:2;
sbit	FP53M = 0xc5:3;
sbit	FP54M = 0xc5:4;
sbit	FP55M = 0xc5:5;
sbit	FP56M = 0xc5:6;
sfr	INTRQ1 = 0xc6;
sbit	FP10IRQ = 0xc6:0;
sbit	FP11IRQ = 0xc6:1;
sbit	FP12IRQ = 0xc6:2;
sbit	FP13IRQ = 0xc6:3;
sbit	FP14IRQ = 0xc6:4;
sbit	FP15IRQ = 0xc6:5;
sbit	FADCIRQ = 0xc6:6;
sbit	FSIOIRQ = 0xc6:7;
sfr	INTEN1 = 0xc7;
sbit	FP10IEN = 0xc7:0;
sbit	FP11IEN = 0xc7:1;
sbit	FP12IEN = 0xc7:2;
sbit	FP13IEN = 0xc7:3;
sbit	FP14IEN = 0xc7:4;
sbit	FP15IEN = 0xc7:5;
sbit	FADCIEN = 0xc7:6;
sbit	FSIOIEN = 0xc7:7;
sfr	INTRQ0 = 0xc8;
sbit	FP00IRQ = 0xc8:0;
sbit	FP01IRQ = 0xc8:1;
sbit	FTXIRQ = 0xc8:2;
sbit	FRXIRQ = 0xc8:3;
sbit	FT0IRQ = 0xc8:4;
sbit	FT1IRQ = 0xc8:5;
sbit	FTC0IRQ = 0xc8:6;
sbit	FTC1IRQ = 0xc8:7;
sfr	INTEN0 = 0xc9;
sbit	FP00IEN = 0xc9:0;
sbit	FP01IEN = 0xc9:1;
sbit	FTXIEN = 0xc9:2;
sbit	FRXIEN = 0xc9:3;
sbit	FT0IEN = 0xc9:4;
sbit	FT1IEN = 0xc9:5;
sbit	FTC0IEN = 0xc9:6;
sbit	FTC1IEN = 0xc9:7;
sfr	OSCM = 0xca;
sbit	FSTPHX = 0xca:1;
sbit	FCLKMD = 0xca:2;
sbit	FCPUM0 = 0xca:3;
sbit	FCPUM1 = 0xca:4;
sfr	WDTR = 0xcc;
sfr	TC0R = 0xcd;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP00 = 0xd0:0;
sbit	FP01 = 0xd0:1;
sfr	P1 = 0xd1;
sbit	FP10 = 0xd1:0;
sbit	FP11 = 0xd1:1;
sbit	FP12 = 0xd1:2;
sbit	FP13 = 0xd1:3;
sbit	FP14 = 0xd1:4;
sbit	FP15 = 0xd1:5;
sfr	P2 = 0xd2;
sbit	FP20 = 0xd2:0;
sbit	FP21 = 0xd2:1;
sbit	FP22 = 0xd2:2;
sbit	FP23 = 0xd2:3;
sfr	P4 = 0xd4;
sbit	FP40 = 0xd4:0;
sbit	FP41 = 0xd4:1;
sbit	FP42 = 0xd4:2;
sbit	FP43 = 0xd4:3;
sbit	FP44 = 0xd4:4;
sbit	FP45 = 0xd4:5;
sbit	FP46 = 0xd4:6;
sfr	P5 = 0xd5;
sbit	FP50 = 0xd5:0;
sbit	FP51 = 0xd5:1;
sbit	FP52 = 0xd5:2;
sbit	FP53 = 0xd5:3;
sbit	FP54 = 0xd5:4;
sbit	FP55 = 0xd5:5;
sbit	FP56 = 0xd5:6;
sfr	T1M = 0xd6;
sbit	FT1CKS = 0xd6:3;
sbit	FT1RATE0 = 0xd6:4;
sbit	FT1RATE1 = 0xd6:5;
sbit	FT1RATE2 = 0xd6:6;
sbit	FT1ENB = 0xd6:7;
sfr	T1C = 0xd7;
sfr	T0M = 0xd8;
sbit	FT0TB = 0xd8:0;
sbit	FTC0GN = 0xd8:1;
sbit	FTC0X8 = 0xd8:2;
sbit	FTC1X8 = 0xd8:3;
sbit	FT0RATE0 = 0xd8:4;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0ENB = 0xd8:7;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FPWM0OUT = 0xda:0;
sbit	FTC0OUT = 0xda:1;
sbit	FALOAD0 = 0xda:2;
sbit	FTC0CKS = 0xda:3;
sbit	FTC0RATE0 = 0xda:4;
sbit	FTC0RATE1 = 0xda:5;
sbit	FTC0RATE2 = 0xda:6;
sbit	FTC0ENB = 0xda:7;
sfr	TC0C = 0xdb;
sfr	TC1M = 0xdc;
sbit	FPWM1OUT = 0xdc:0;
sbit	FTC1OUT = 0xdc:1;
sbit	FALOAD1 = 0xdc:2;
sbit	FTC1CKS = 0xdc:3;
sbit	FTC1RATE0 = 0xdc:4;
sbit	FTC1RATE1 = 0xdc:5;
sbit	FTC1RATE2 = 0xdc:6;
sbit	FTC1ENB = 0xdc:7;
sfr	TC1C = 0xdd;
sfr	TC1R = 0xde;
sfr	STKP = 0xdf;
sbit	FSTKPB0 = 0xdf:0;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB3 = 0xdf:3;
sbit	FSTKPB4 = 0xdf:4;
sbit	FGIE = 0xdf:7;
sfr	P0UR = 0xe0;
sbit	FP00R = 0xe0:0;
sbit	FP01R = 0xe0:1;
sfr	P1UR = 0xe1;
sbit	FP10R = 0xe1:0;
sbit	FP11R = 0xe1:1;
sbit	FP12R = 0xe1:2;
sbit	FP13R = 0xe1:3;
sfr	P2UR = 0xe2;
sbit	FP20R = 0xe2:0;
sbit	FP21R = 0xe2:1;
sbit	FP22R = 0xe2:2;
sbit	FP23R = 0xe2:3;
sfr	P4UR = 0xe4;
sbit	FP40R = 0xe4:0;
sbit	FP41R = 0xe4:1;
sbit	FP42R = 0xe4:2;
sbit	FP43R = 0xe4:3;
sbit	FP44R = 0xe4:4;
sbit	FP45R = 0xe4:5;
sbit	FP46R = 0xe4:6;
sfr	P5UR = 0xe5;
sbit	FP50R = 0xe5:0;
sbit	FP51R = 0xe5:1;
sbit	FP52R = 0xe5:2;
sbit	FP53R = 0xe5:3;
sbit	FP54R = 0xe5:4;
sbit	FP55R = 0xe5:5;
sbit	FP56R = 0xe5:6;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	P1OC = 0xe9;
sbit	FP10OC = 0xe9:0;
sbit	FP11OC = 0xe9:1;
sbit	FP12OC = 0xe9:2;
sbit	FP13OC = 0xe9:3;
sbit	FP50OC = 0xe9:4;
sbit	FP51OC = 0xe9:5;
sbit	FP52OC = 0xe9:6;
sfr	T2M = 0xea;
sbit	FT2ENB = 0xea:7;
sbit	FT2rate2 = 0xea:6;
sbit	FT2rate1 = 0xea:5;
sbit	FT2rate0 = 0xea:4;
sbit	FT2CKS = 0xea:3;
sfr	T2CL = 0xeb;
sfr	T2CH = 0xec;
sfr	CPT2M = 0xed;
sbit	FCPT2EN = 0xed:7;
sbit	FCPT2MD = 0xed:3;
sbit	FCPT2Start = 0xed:2;
sbit	FCPT2G1 = 0xed:1;
sbit	FCPT2G0 = 0xed:0;
sfr	CPT2CL = 0xee;
sfr	CPT2CH = 0xef;
sfr	URRX = 0xf0;
sbit	FURS0 = 0xf0:0;
sbit	FURS1 = 0xf0:1;
sbit	FURS2 = 0xf0:2;
sbit	FUFMER = 0xf0:3;
sbit	FURXPC = 0xf0:4;
sbit	FURXPS = 0xf0:5;
sbit	FURXPEN = 0xf0:6;
sbit	FURXEN = 0xf0:7;
sfr	URTX = 0xf1;
sbit	FUTXBZ = 0xf1:2;
sbit	FURXBZ = 0xf1:3;
sbit	FUTXBRK = 0xf1:4;
sbit	FUTXPS = 0xf1:5;
sbit	FUTXPEN = 0xf1:6;
sbit	FUTXEN = 0xf1:7;
sfr	URCR = 0xf2;
sbit	FURCR0 = 0xf2:0;
sbit	FURCR1 = 0xf2:1;
sbit	FURCR2 = 0xf2:2;
sbit	FURCR3 = 0xf2:3;
sbit	FURCR4 = 0xf2:4;
sbit	FURCR5 = 0xf2:5;
sbit	FURCR6 = 0xf2:6;
sbit	FURCR7 = 0xf2:7;
sfr	UTXD = 0xf3;
sbit	FUTXD0 = 0xf3:0;
sbit	FUTXD1 = 0xf3:1;
sbit	FUTXD2 = 0xf3:2;
sbit	FUTXD3 = 0xf3:3;
sbit	FUTXD4 = 0xf3:4;
sbit	FUTXD5 = 0xf3:5;
sbit	FUTXD6 = 0xf3:6;
sbit	FUTXD7 = 0xf3:7;
sfr	URXD = 0xf4;
sbit	FURXD0 = 0xf4:0;
sbit	FURXD1 = 0xf4:1;
sbit	FURXD2 = 0xf4:2;
sbit	FURXD3 = 0xf4:3;
sbit	FURXD4 = 0xf4:4;
sbit	FURXD5 = 0xf4:5;
sbit	FURXD6 = 0xf4:6;
sbit	FURXD7 = 0xf4:7;
sfr	INTRQ2 = 0xf5;
sbit	FT2IRQ = 0xf5:0;
sbit	FT3IRQ = 0xf5:1;
sfr	INTEN2 = 0xf6;
sbit	FT2IEN = 0xf6:0;
sbit	FT3IEN = 0xf6:1;
sfr	DAM = 0xf7;
sbit	FDAEN = 0xf7:7;
sfr	DABL = 0xf8;
sfr	DABH = 0xf9;
sfr	T3M = 0xfa;
sbit	FT3ENB = 0xfa:7;
sbit	FT3rate2 = 0xfa:6;
sbit	FT3rate1 = 0xfa:5;
sbit	FT3rate0 = 0xfa:4;
sbit	FT3CKS = 0xfa:3;
sfr	T3CL = 0xfb;
sfr	T3CH = 0xfc;
sfr	CPT3M = 0xfd;
sbit	FCPT3EN = 0xfd:7;
sbit	FCPT3MD = 0xfd:3;
sbit	FCPT3Start = 0xfd:2;
sbit	FCPT3G1 = 0xfd:1;
sbit	FCPT3G0 = 0xfd:0;
sfr	CPT3CL = 0xfe;
sfr	CPT3CH = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SLowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
