#ifndef __SN8F25E24L__H
#define __SN8F25E24L__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	X = 0x85;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FSTKOV = 0x86:4;
sbit	FRST = 0x86:5;
sbit	FWDT = 0x86:6;
sbit	FPOR = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBANKS0 = 0x87:0;
sbit	FRBANKS1 = 0x87:1;
sbit	FRBANKS2 = 0x87:2;
sfr	W0 = 0x88;
sfr	W1 = 0x89;
sfr	W2 = 0x8a;
sfr	W3 = 0x8b;
sfr	W4 = 0x8c;
sfr	W5 = 0x8d;
sfr	W6 = 0x8e;
sfr	W7 = 0x8f;
sfr	_HL = 0x90;
sfr	_YZ = 0x91;
sfr	P2OC = 0x92;
sbit	FP20OC = 0x92:0;
sbit	FP21OC = 0x92:1;
sbit	FP24OC = 0x92:4;
sbit	FP25OC = 0x92:5;
sfr	PCL = 0x93;
sfr	PCH = 0x94;
sfr	OSCM = 0x95;
sbit	FCPUM1 = 0x95:4;
sbit	FCPUM0 = 0x95:3;
sbit	FCLKMD = 0x95:2;
sbit	FSTPHX = 0x95:1;
sfr	WDTR = 0x96;
sfr	INTRQ0 = 0x97;
sbit	FCM0IRQ = 0x97:7;
sbit	FT1IRQ = 0x97:6;
sbit	FTC2IRQ = 0x97:5;
sbit	FTC1IRQ = 0x97:4;
sbit	FTC0IRQ = 0x97:3;
sbit	FT0IRQ = 0x97:2;
sbit	FP01IRQ = 0x97:1;
sbit	FP00IRQ = 0x97:0;
sfr	INTRQ1 = 0x98;
sbit	FMSPIRQ = 0x98:4;
sbit	FUTXIRQ = 0x98:3;
sbit	FURXIRQ = 0x98:2;
sbit	FSIOIRQ = 0x98:1;
sbit	FWAKEIRQ = 0x98:0;
sfr	INTEN0 = 0x9a;
sbit	FCM0IEN = 0x9a:7;
sbit	FT1IEN = 0x9a:6;
sbit	FTC2IEN = 0x9a:5;
sbit	FTC1IEN = 0x9a:4;
sbit	FTC0IEN = 0x9a:3;
sbit	FT0IEN = 0x9a:2;
sbit	FP01IEN = 0x9a:1;
sbit	FP00IEN = 0x9a:0;
sfr	INTEN1 = 0x9b;
sbit	FMSPIEN = 0x9b:4;
sbit	FUTXIEN = 0x9b:3;
sbit	FURXIEN = 0x9b:2;
sbit	FSIOIEN = 0x9b:1;
sbit	FWAKEIEN = 0x9b:0;
sfr	P1W = 0x99;
sbit	FP17W = 0x99:7;
sbit	FP16W = 0x99:6;
sbit	FP15W = 0x99:5;
sbit	FP14W = 0x99:4;
sbit	FP13W = 0x99:3;
sbit	FP12W = 0x99:2;
sbit	FP11W = 0x99:1;
sbit	FP10W = 0x99:0;
sfr	CM0M = 0x9c;
sbit	FCMCH0 = 0x9c:0;
sbit	FCMCH1 = 0x9c:1;
sbit	FCMCH2 = 0x9c:2;
sbit	FCMCH3 = 0x9c:3;
sbit	FCMCH4 = 0x9c:4;
sbit	FCM0S0 = 0x9c:5;
sbit	FCM0S1 = 0x9c:6;
sbit	FCM0EN = 0x9c:7;
sfr	CM0M1 = 0x9d;
sbit	FCM0G = 0x9d:0;
sbit	FCM0OEN = 0x9d:1;
sbit	FCMDB0 = 0x9d:2;
sbit	FCMDB1 = 0x9d:3;
sbit	FCM0OUT = 0x9d:6;
sbit	FTCHEN = 0x9d:7;
sfr	CM0M2 = 0x9e;
sbit	FTCHCM0 = 0x9e:0;
sbit	FTCHCM1 = 0x9e:1;
sbit	FTCHCM2 = 0x9e:2;
sbit	FTRS0 = 0x9e:4;
sbit	FTRS1 = 0x9e:5;
sbit	FTRS2 = 0x9e:6;
sbit	FTRS3 = 0x9e:7;
sfr	PEDGE = 0x9f;
sbit	FP01G1 = 0x9f:3;
sbit	FP01G0 = 0x9f:2;
sbit	FP00G1 = 0x9f:1;
sbit	FP00G0 = 0x9f:0;
sfr	P0M = 0xa0;
sbit	FP07M = 0xa0:7;
sbit	FP06M = 0xa0:6;
sbit	FP05M = 0xa0:5;
sbit	FP04M = 0xa0:4;
sbit	FP03M = 0xa0:3;
sbit	FP02M = 0xa0:2;
sbit	FP01M = 0xa0:1;
sbit	FP00M = 0xa0:0;
sfr	P1M = 0xa1;
sbit	FP17M = 0xa1:7;
sbit	FP16M = 0xa1:6;
sbit	FP15M = 0xa1:5;
sbit	FP14M = 0xa1:4;
sbit	FP13M = 0xa1:3;
sbit	FP12M = 0xa1:2;
sbit	FP11M = 0xa1:1;
sbit	FP10M = 0xa1:0;
sfr	P2M = 0xa2;
sbit	FP25M = 0xa2:5;
sbit	FP24M = 0xa2:4;
sbit	FP23M = 0xa2:3;
sbit	FP22M = 0xa2:2;
sbit	FP21M = 0xa2:1;
sbit	FP20M = 0xa2:0;
sfr	P5M = 0xa5;
sbit	FP57M = 0xa5:7;
sbit	FP56M = 0xa5:6;
sbit	FP55M = 0xa5:5;
sbit	FP54M = 0xa5:4;
sbit	FP53M = 0xa5:3;
sbit	FP52M = 0xa5:2;
sbit	FP51M = 0xa5:1;
sbit	FP50M = 0xa5:0;
sfr	P0 = 0xa6;
sbit	FP07 = 0xa6:7;
sbit	FP06 = 0xa6:6;
sbit	FP05 = 0xa6:5;
sbit	FP04 = 0xa6:4;
sbit	FP03 = 0xa6:3;
sbit	FP02 = 0xa6:2;
sbit	FP01 = 0xa6:1;
sbit	FP00 = 0xa6:0;
sfr	P1 = 0xa7;
sbit	FP17 = 0xa7:7;
sbit	FP16 = 0xa7:6;
sbit	FP15 = 0xa7:5;
sbit	FP14 = 0xa7:4;
sbit	FP13 = 0xa7:3;
sbit	FP12 = 0xa7:2;
sbit	FP11 = 0xa7:1;
sbit	FP10 = 0xa7:0;
sfr	P2 = 0xa8;
sbit	FP25 = 0xa8:5;
sbit	FP24 = 0xa8:4;
sbit	FP23 = 0xa8:3;
sbit	FP22 = 0xa8:2;
sbit	FP21 = 0xa8:1;
sbit	FP20 = 0xa8:0;
sfr	P5 = 0xab;
sbit	FP57 = 0xab:7;
sbit	FP56 = 0xab:6;
sbit	FP55 = 0xab:5;
sbit	FP54 = 0xab:4;
sbit	FP53 = 0xab:3;
sbit	FP52 = 0xab:2;
sbit	FP51 = 0xab:1;
sbit	FP50 = 0xab:0;
sfr	P0UR = 0xac;
sbit	FP00R = 0xac:0;
sbit	FP01R = 0xac:1;
sbit	FP02R = 0xac:2;
sbit	FP03R = 0xac:3;
sbit	FP04R = 0xac:4;
sbit	FP05R = 0xac:5;
sbit	FP06R = 0xac:6;
sbit	FP07R = 0xac:7;
sfr	P1UR = 0xad;
sbit	FP10R = 0xad:0;
sbit	FP11R = 0xad:1;
sbit	FP12R = 0xad:2;
sbit	FP13R = 0xad:3;
sbit	FP14R = 0xad:4;
sbit	FP15R = 0xad:5;
sbit	FP16R = 0xad:6;
sbit	FP17R = 0xad:7;
sfr	P2UR = 0xae;
sbit	FP20R = 0xae:0;
sbit	FP21R = 0xae:1;
sbit	FP22R = 0xae:2;
sbit	FP23R = 0xae:3;
sbit	FP24R = 0xae:4;
sbit	FP25R = 0xae:5;
sfr	P5UR = 0xb1;
sbit	FP50R = 0xb1:0;
sbit	FP51R = 0xb1:1;
sbit	FP52R = 0xb1:2;
sbit	FP53R = 0xb1:3;
sbit	FP54R = 0xb1:4;
sbit	FP55R = 0xb1:5;
sbit	FP56R = 0xb1:6;
sbit	FP57R = 0xb1:7;
sfr	T0M = 0xb2;
sbit	FT0ENB = 0xb2:7;
sbit	FT0RATE2 = 0xb2:6;
sbit	FT0RATE1 = 0xb2:5;
sbit	FT0RATE0 = 0xb2:4;
sbit	FT0TB = 0xb2:0;
sfr	T0C = 0xb3;
sfr	TC0M = 0xb4;
sbit	FTC0ENB = 0xb4:7;
sbit	FTC0RATE2 = 0xb4:6;
sbit	FTC0RATE1 = 0xb4:5;
sbit	FTC0RATE0 = 0xb4:4;
sbit	FTC0CKS1 = 0xb4:3;
sbit	FTC0CKS0 = 0xb4:2;
sbit	FTC0PO = 0xb4:1;
sbit	FPWM0OUT = 0xb4:0;
sfr	TC0C = 0xb5;
sfr	TC0R = 0xb6;
sfr	TC0D = 0xb7;
sfr	TC1M = 0xb8;
sbit	FTC1ENB = 0xb8:7;
sbit	FTC1RATE2 = 0xb8:6;
sbit	FTC1RATE1 = 0xb8:5;
sbit	FTC1RATE0 = 0xb8:4;
sbit	FTC1CKS1 = 0xb8:3;
sbit	FTC1CKS0 = 0xb8:2;
sbit	FTC1PO = 0xb8:1;
sbit	FPWM1OUT = 0xb8:0;
sfr	TC1C = 0xb9;
sfr	TC1R = 0xba;
sfr	TC1D = 0xbb;
sfr	TC2M = 0xbc;
sbit	FTC2ENB = 0xbc:7;
sbit	FTC2RATE2 = 0xbc:6;
sbit	FTC2RATE1 = 0xbc:5;
sbit	FTC2RATE0 = 0xbc:4;
sbit	FTC2CKS1 = 0xbc:3;
sbit	FTC2CKS0 = 0xbc:2;
sbit	FTC2PO = 0xbc:1;
sbit	FPWM2OUT = 0xbc:0;
sfr	TC2C = 0xbd;
sfr	TC2R = 0xbe;
sfr	TC2D = 0xbf;
sfr	T1M = 0xc0;
sbit	FT1VCOV = 0xc0:0;
sbit	FT1OV = 0xc0:1;
sbit	FCPTStart = 0xc0:2;
sbit	FCPTCKS = 0xc0:3;
sbit	FT1rate0 = 0xc0:4;
sbit	FT1rate1 = 0xc0:5;
sbit	FT1rate2 = 0xc0:6;
sbit	FT1ENB = 0xc0:7;
sfr	T1CL = 0xc1;
sfr	T1CH = 0xc2;
sfr	T1VCL = 0xc4;
sfr	T1VCH = 0xc5;
sfr	PECMD = 0xdb;
sfr	PEROML = 0xdc;
sfr	PEROMH = 0xdd;
sfr	PERAML = 0xde;
sfr	PERAMCNT = 0xdf;
sfr	SIOM = 0xe0;
sbit	FSENB = 0xe0:7;
sbit	FSTART = 0xe0:6;
sbit	FSRATE1 = 0xe0:5;
sbit	FSRATE0 = 0xe0:4;
sbit	FMLSB = 0xe0:3;
sbit	FSCKMD = 0xe0:2;
sbit	FCPOL = 0xe0:1;
sbit	FCPHA = 0xe0:0;
sfr	SIOR = 0xe1;
sfr	SIOB = 0xe2;
sfr	URTX = 0xe4;
sbit	FUTXEN = 0xe4:7;
sbit	FUTXPEN = 0xe4:6;
sbit	FUTXPS = 0xe4:5;
sbit	FUTXBRK = 0xe4:4;
sbit	FURXBZ = 0xe4:3;
sbit	FUTXBZ = 0xe4:2;
sfr	URRX = 0xe5;
sbit	FURXEN = 0xe5:7;
sbit	FURXPEN = 0xe5:6;
sbit	FURXPS = 0xe5:5;
sbit	FURXPC = 0xe5:4;
sbit	FUFMER = 0xe5:3;
sbit	FURS2 = 0xe5:2;
sbit	FURS1 = 0xe5:1;
sbit	FURS0 = 0xe5:0;
sfr	URCR = 0xe6;
sfr	UTXD = 0xe7;
sfr	URXD = 0xe8;
sfr	MSPSTAT = 0xea;
sbit	FCKE = 0xea:6;
sbit	FD_A = 0xea:5;
sbit	FP = 0xea:4;
sbit	FS = 0xea:3;
sbit	FRED_WRT = 0xea:2;
sbit	FBF = 0xea:0;
sfr	MSPM1 = 0xeb;
sbit	FWCOL = 0xeb:7;
sbit	FMSPOV = 0xeb:6;
sbit	FMSPENB = 0xeb:5;
sbit	FCKP = 0xeb:4;
sbit	FSLRXCKP = 0xeb:3;
sbit	FMSPWK = 0xeb:2;
sbit	FMSPC = 0xeb:0;
sfr	MSPM2 = 0xec;
sbit	FGCEN = 0xec:7;
sbit	FACKSTAT = 0xec:6;
sbit	FACKDT = 0xec:5;
sbit	FACKEN = 0xec:4;
sbit	FRCEN = 0xec:3;
sbit	FPEN = 0xec:2;
sbit	FRSEN = 0xec:1;
sbit	FSEN = 0xec:0;
sfr	MSPBUF = 0xed;
sbit	FMSPBUF7 = 0xed:7;
sbit	FMSPBUF6 = 0xed:6;
sbit	FMSPBUF5 = 0xed:5;
sbit	FMSPBUF4 = 0xed:4;
sbit	FMSPBUF3 = 0xed:3;
sbit	FMSPBUF2 = 0xed:2;
sbit	FMSPBUF1 = 0xed:1;
sbit	FMSPBUF0 = 0xed:0;
sfr	MSPADR = 0xee;
sbit	FMSPADR7 = 0xee:7;
sbit	FMSPADR6 = 0xee:6;
sbit	FMSPADR5 = 0xee:5;
sbit	FMSPADR4 = 0xee:4;
sbit	FMSPADR3 = 0xee:3;
sbit	FMSPADR2 = 0xee:2;
sbit	FMSPADR1 = 0xee:1;
sbit	FMSPADR0 = 0xee:0;
sfr	STKP = 0xef;
sbit	FGIE = 0xef:7;
sbit	FLVD24 = 0xef:6;
sbit	FLVD33 = 0xef:5;
sbit	FSTKPB2 = 0xef:2;
sbit	FSTKPB1 = 0xef:1;
sbit	FSTKPB0 = 0xef:0;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
