#ifndef __SN8P2949__H
#define __SN8P2949__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	X = 0x85;
sfr	PFLAG = 0x86;
sbit	FC = 0x86:2;
sbit	FDC = 0x86:1;
sbit	FZ = 0x86:0;
sfr	RBANK = 0x87;
sbit	FRBNKS3 = 0x87:3;
sbit	FRBNKS2 = 0x87:2;
sbit	FRBNKS1 = 0x87:1;
sbit	FRBNKS0 = 0x87:0;
sfr	LCDM1 = 0x89;
sbit	FLCDREF1 = 0x89:7;
sbit	FLCDREF0 = 0x89:6;
sbit	FLCDBNK = 0x89:5;
sbit	FLCDTYPE = 0x89:4;
sbit	FLCDENB = 0x89:3;
sbit	FLCDBIAS = 0x89:2;
sbit	FLCDRATE = 0x89:1;
sbit	FLCDCLK = 0x89:0;
sfr	LCDM2 = 0x8a;
sbit	FBGM = 0x8a:6;
sbit	FLCDPENB = 0x8a:5;
sbit	FVPPINTL = 0x8a:4;
sbit	FVCP3 = 0x8a:3;
sbit	FVCP2 = 0x8a:2;
sbit	FVCP1 = 0x8a:1;
sbit	FVCP0 = 0x8a:0;
sfr	VREG = 0x90;
sbit	FBGRENB = 0x90:7;
sbit	FACMSEL = 0x90:6;
sbit	FACMENB = 0x90:5;
sbit	FAVESEL = 0x90:4;
sbit	FAVENB = 0x90:3;
sbit	FAVDDRSEL = 0x90:2;
sbit	FAVDDRENB = 0x90:1;
sfr	AMPM1 = 0x91;
sbit	FCHS3 = 0x91:7;
sbit	FCHS2 = 0x91:6;
sbit	FCHS1 = 0x91:5;
sbit	FCHS0 = 0x91:4;
sbit	FGS2 = 0x91:3;
sbit	FGS1 = 0x91:2;
sbit	FGS0 = 0x91:1;
sbit	FAMPENB = 0x91:0;
sfr	AMPM2 = 0x92;
sbit	FINRENB = 0x92:7;
sbit	FGX = 0x92:6;
sbit	FGR = 0x92:5;
sbit	FAMPCKS1 = 0x92:4;
sbit	FAMPCKS0 = 0x92:3;
sbit	FPCHPENB = 0x92:2;
sbit	FDTENB = 0x92:1;
sbit	FDTSEL = 0x92:0;
sfr	ADCM1 = 0x93;
sbit	FRVS = 0x93:7;
sbit	FIRVS3 = 0x93:6;
sbit	FIRVS2 = 0x93:5;
sbit	FIRVS1 = 0x93:4;
sbit	FIRVS0 = 0x93:3;
sbit	FADGN1 = 0x93:2;
sbit	FADGN0 = 0x93:1;
sbit	FADCENB = 0x93:0;
sfr	ADCM2 = 0x94;
sbit	FOSR2 = 0x94:6;
sbit	FOSR1 = 0x94:5;
sbit	FOSR0 = 0x94:4;
sbit	FOFSEL1 = 0x94:2;
sbit	FOFSEL0 = 0x94:1;
sbit	FDRDY = 0x94:0;
sfr	ADCM3 = 0x95;
sbit	FACHPENB = 0x95:4;
sbit	FADCKINV = 0x95:3;
sbit	FADCKS2 = 0x95:2;
sbit	FADCKS1 = 0x95:1;
sbit	FADCKS0 = 0x95:0;
sfr	LBTM = 0x96;
sbit	FP51IO = 0x96:6;
sbit	FLBTSEL3 = 0x96:5;
sbit	FLBTSEL2 = 0x96:4;
sbit	FLBTSEL1 = 0x96:3;
sbit	FLBTSEL0 = 0x96:2;
sbit	FLBTO = 0x96:1;
sbit	FLBTENB = 0x96:0;
sfr	ADCDH = 0x97;
sfr	ADCDM = 0x98;
sfr	ADCDL = 0x99;
sfr	LEDCPM = 0x9a;
sbit	FVLEDENB = 0x9a:4;
sbit	FCPCKS2 = 0x9a:3;
sbit	FCPCKS1 = 0x9a:2;
sbit	FCPCKS0 = 0x9a:1;
sbit	FCPRENB = 0x9a:0;
sfr	ROMADRH = 0xa0;
sbit	FVPPCHK = 0xa0:7;
sbit	FROMADR12 = 0xa0:4;
sbit	FROMADR11 = 0xa0:3;
sbit	FROMADR10 = 0xa0:2;
sbit	FROMADR9 = 0xa0:1;
sbit	FROMADR8 = 0xa0:0;
sfr	ROMADRL = 0xa1;
sbit	FROMADR7 = 0xa1:7;
sbit	FROMADR6 = 0xa1:6;
sbit	FROMADR5 = 0xa1:5;
sbit	FROMADR4 = 0xa1:4;
sbit	FROMADR3 = 0xa1:3;
sbit	FROMADR2 = 0xa1:2;
sbit	FROMADR1 = 0xa1:1;
sbit	FROMADR0 = 0xa1:0;
sfr	ROMDAH = 0xa2;
sbit	FROMDA15 = 0xa2:7;
sbit	FROMDA14 = 0xa2:6;
sbit	FROMDA13 = 0xa2:5;
sbit	FROMDA12 = 0xa2:4;
sbit	FROMDA11 = 0xa2:3;
sbit	FROMDA10 = 0xa2:2;
sbit	FROMDA9 = 0xa2:1;
sbit	FROMDA8 = 0xa2:0;
sfr	ROMDAL = 0xa3;
sbit	FROMDA7 = 0xa3:7;
sbit	FROMDA6 = 0xa3:6;
sbit	FROMDA5 = 0xa3:5;
sbit	FROMDA4 = 0xa3:4;
sbit	FROMDA3 = 0xa3:3;
sbit	FROMDA2 = 0xa3:2;
sbit	FROMDA1 = 0xa3:1;
sbit	FROMDA0 = 0xa3:0;
sfr	ROMCNT = 0xa4;
sbit	ROMCNT1 = 0xa4:1;
sbit	ROMCNT0 = 0xa4:0;
sfr	P0M = 0xb8;
sbit	FP07M = 0xb8:7;
sbit	FP06M = 0xb8:6;
sbit	FP05M = 0xb8:5;
sbit	FP04M = 0xb8:4;
sbit	FP03M = 0xb8:3;
sbit	FP02M = 0xb8:2;
sbit	FP01M = 0xb8:1;
sbit	FP00M = 0xb8:0;
sfr	PEDGE = 0xbf;
sbit	FP01G1 = 0xbf:3;
sbit	FP01G0 = 0xbf:2;
sbit	FP00G1 = 0xbf:1;
sbit	FP00G0 = 0xbf:0;
sfr	P1W = 0xc0;
sbit	FP14W = 0xc0:4;
sbit	FP13W = 0xc0:3;
sbit	FP12W = 0xc0:2;
sbit	FP11W = 0xc0:1;
sbit	FP10W = 0xc0:0;
sfr	P1M = 0xc1;
sbit	FP14M = 0xc1:4;
sbit	FP13M = 0xc1:3;
sbit	FP12M = 0xc1:2;
sbit	FP11M = 0xc1:1;
sbit	FP10M = 0xc1:0;
sfr	P2M = 0xc2;
sbit	FP21M = 0xc2:1;
sbit	FP20M = 0xc2:0;
sfr	P5M = 0xc5;
sbit	FP54M = 0xc5:4;
sbit	FP53M = 0xc5:3;
sbit	FP52M = 0xc5:2;
sbit	FP51M = 0xc5:1;
sbit	FP50M = 0xc5:0;
sfr	INTRQ = 0xc8;
sbit	FADCIRQ = 0xc8:7;
sbit	FTC1IRQ = 0xc8:6;
sbit	FTC0IRQ = 0xc8:5;
sbit	FT0IRQ = 0xc8:4;
sbit	FP01IRQ = 0xc8:1;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN = 0xc9;
sbit	FADCIEN = 0xc9:7;
sbit	FTC1IEN = 0xc9:6;
sbit	FTC0IEN = 0xc9:5;
sbit	FT0IEN = 0xc9:4;
sbit	FP01IEN = 0xc9:1;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	TC0R = 0xcd;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP07 = 0xd0:7;
sbit	FP06 = 0xd0:6;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP14 = 0xd1:4;
sbit	FP13 = 0xd1:3;
sbit	FP12 = 0xd1:2;
sbit	FP11 = 0xd1:1;
sbit	FP10 = 0xd1:0;
sfr	P2 = 0xd2;
sbit	FP21 = 0xd2:1;
sbit	FP20 = 0xd2:0;
sfr	P5 = 0xd5;
sbit	FP54 = 0xd5:4;
sbit	FP53 = 0xd5:3;
sbit	FP52 = 0xd5:2;
sbit	FP51 = 0xd5:1;
sbit	FP50 = 0xd5:0;
sfr	T0M = 0xd8;
sbit	FT0ENB = 0xd8:7;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE0 = 0xd8:4;
sbit	FTC1X8 = 0xd8:3;
sbit	FTC0X8 = 0xd8:2;
sbit	FTC0GN = 0xd8:1;
sbit	FT0TB = 0xd8:0;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FTC0ENB = 0xda:7;
sbit	FTC0RATE2 = 0xda:6;
sbit	FTC0RATE1 = 0xda:5;
sbit	FTC0RATE0 = 0xda:4;
sbit	FTC0CKS = 0xda:3;
sbit	FALOAD0 = 0xda:2;
sbit	FTC0OUT = 0xda:1;
sbit	FPWM0OUT = 0xda:0;
sfr	TC0C = 0xdb;
sfr	TC1M = 0xdc;
sbit	FTC1ENB = 0xdc:7;
sbit	FTC1RATE2 = 0xdc:6;
sbit	FTC1RATE1 = 0xdc:5;
sbit	FTC1RATE0 = 0xdc:4;
sbit	FTC1CKS = 0xdc:3;
sbit	FALOAD1 = 0xdc:2;
sbit	FTC1OUT = 0xdc:1;
sbit	FPWM1OUT = 0xdc:0;
sfr	TC1C = 0xdd;
sfr	TC1R = 0xde;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sbit	FP07R = 0xe0:7;
sbit	FP06R = 0xe0:6;
sbit	FP05R = 0xe0:5;
sbit	FP04R = 0xe0:4;
sbit	FP03R = 0xe0:3;
sbit	FP02R = 0xe0:2;
sbit	FP01R = 0xe0:1;
sbit	FP00R = 0xe0:0;
sfr	P1UR = 0xe1;
sbit	FP14R = 0xe1:4;
sbit	FP13R = 0xe1:3;
sbit	FP12R = 0xe1:2;
sbit	FP11R = 0xe1:1;
sbit	FP10R = 0xe1:0;
sfr	P2UR = 0xe2;
sbit	FP21R = 0xe2:1;
sbit	FP20R = 0xe2:0;
sfr	P5UR = 0xe5;
sbit	FP54R = 0xe5:4;
sbit	FP53R = 0xe5:3;
sbit	FP52R = 0xe5:2;
sbit	FP51R = 0xe5:1;
sbit	FP50R = 0xe5:0;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SLowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#define ROMWRTVPP __asm{RomwrtVpp}
#endif
