#ifndef __SN8F27E93L__H
#define __SN8F27E93L__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	X = 0x85;
sfr	PFLAG = 0x86;
sbit	FPOR = 0x86:7;
sbit	FWDT = 0x86:6;
sbit	FRST = 0x86:5;
sbit	FSTKOV = 0x86:4;
sbit	FC = 0x86:2;
sbit	FDC = 0x86:1;
sbit	FZ = 0x86:0;
sfr	RBANK = 0x87;
sbit	FRBNKS2 = 0x87:2;
sbit	FRBNKS1 = 0x87:1;
sbit	FRBNKS0 = 0x87:0;
sfr	W0 = 0x88;
sfr	W1 = 0x89;
sfr	W2 = 0x8a;
sfr	W3 = 0x8b;
sfr	W4 = 0x8c;
sfr	W5 = 0x8d;
sfr	W6 = 0x8e;
sfr	W7 = 0x8f;
sfr	_HL = 0x90;
sfr	_YZ = 0x91;
sfr	PCL = 0x93;
sfr	PCH = 0x94;
sfr	OSCM = 0x95;
sbit	FCPUM1 = 0x95:4;
sbit	FCPUM0 = 0x95:3;
sbit	FCLKMD = 0x95:2;
sbit	FSTPHX = 0x95:1;
sfr	WDTR = 0x96;
sfr	INTRQ0 = 0x97;
sbit	FADCIRQ = 0x97:7;
sbit	FT1IRQ = 0x97:6;
sbit	FTC0IRQ = 0x97:3;
sbit	FT0IRQ = 0x97:2;
sbit	FP01IRQ = 0x97:1;
sbit	FP00IRQ = 0x97:0;
sfr	INTRQ1 = 0x98;
sbit	FMSPIRQ = 0x98:4;
sbit	FUTXIRQ = 0x98:3;
sbit	FURXIRQ = 0x98:2;
sbit	FSIOIRQ = 0x98:1;
sbit	FWAKEIRQ = 0x98:0;
sfr	INTEN0 = 0x9a;
sbit	FADCIEN = 0x9a:7;
sbit	FT1IEN = 0x9a:6;
sbit	FTC0IEN = 0x9a:3;
sbit	FT0IEN = 0x9a:2;
sbit	FP01IEN = 0x9a:1;
sbit	FP00IEN = 0x9a:0;
sfr	INTEN1 = 0x9b;
sbit	FMSPIEN = 0x9b:4;
sbit	FUTXIEN = 0x9b:3;
sbit	FURXIEN = 0x9b:2;
sbit	FSIOIEN = 0x9b:1;
sbit	FWAKEIEN = 0x9b:0;
sfr	P0OC = 0x9c;
sbit	FP04OC = 0x9c:2;
sbit	FP03OC = 0x9c:1;
sbit	FP02OC = 0x9c:0;
sfr	P1W = 0x9e;
sbit	FP13W = 0x9e:3;
sbit	FP12W = 0x9e:2;
sbit	FP11W = 0x9e:1;
sbit	FP10W = 0x9e:0;
sfr	PEDGE = 0x9f;
sbit	FP01G1 = 0x9f:3;
sbit	FP01G0 = 0x9f:2;
sbit	FP00G1 = 0x9f:1;
sbit	FP00G0 = 0x9f:0;
sfr	P0M = 0xa0;
sbit	FP07M = 0xa0:7;
sbit	FP06M = 0xa0:6;
sbit	FP05M = 0xa0:5;
sbit	FP04M = 0xa0:4;
sbit	FP03M = 0xa0:3;
sbit	FP02M = 0xa0:2;
sbit	FP01M = 0xa0:1;
sbit	FP00M = 0xa0:0;
sfr	P1M = 0xa1;
sbit	FP13M = 0xa1:3;
sbit	FP12M = 0xa1:2;
sbit	FP11M = 0xa1:1;
sbit	FP10M = 0xa1:0;
sfr	P4M = 0xa4;
sbit	FP41M = 0xa4:1;
sbit	FP40M = 0xa4:0;
sfr	P0 = 0xa6;
sbit	FP07 = 0xa6:7;
sbit	FP06 = 0xa6:6;
sbit	FP05 = 0xa6:5;
sbit	FP04 = 0xa6:4;
sbit	FP03 = 0xa6:3;
sbit	FP02 = 0xa6:2;
sbit	FP01 = 0xa6:1;
sbit	FP00 = 0xa6:0;
sfr	P1 = 0xa7;
sbit	FP13 = 0xa7:3;
sbit	FP12 = 0xa7:2;
sbit	FP11 = 0xa7:1;
sbit	FP10 = 0xa7:0;
sfr	P4 = 0xaa;
sbit	FP41 = 0xaa:1;
sbit	FP40 = 0xaa:0;
sfr	P0UR = 0xac;
sbit	FP07UR = 0xac:7;
sbit	FP06UR = 0xac:6;
sbit	FP05UR = 0xac:5;
sbit	FP04UR = 0xac:4;
sbit	FP03UR = 0xac:3;
sbit	FP02UR = 0xac:2;
sbit	FP01UR = 0xac:1;
sbit	FP00UR = 0xac:0;
sfr	P1UR = 0xad;
sbit	FP13UR = 0xad:3;
sbit	FP12UR = 0xad:2;
sbit	FP11UR = 0xad:1;
sbit	FP10UR = 0xad:0;
sfr	P4UR = 0xb0;
sbit	FP41UR = 0xb0:1;
sbit	FP40UR = 0xb0:0;
sfr	T0M = 0xb2;
sbit	FT0ENB = 0xb2:7;
sbit	FT0RATE2 = 0xb2:6;
sbit	FT0RATE1 = 0xb2:5;
sbit	FT0RATE0 = 0xb2:4;
sbit	FT0TB = 0xb2:0;
sfr	T0C = 0xb3;
sbit	FT0C7 = 0xb3:7;
sbit	FT0C6 = 0xb3:6;
sbit	FT0C5 = 0xb3:5;
sbit	FT0C4 = 0xb3:4;
sbit	FT0C3 = 0xb3:3;
sbit	FT0C2 = 0xb3:2;
sbit	FT0C1 = 0xb3:1;
sbit	FT0C0 = 0xb3:0;
sfr	TC0M = 0xb4;
sbit	FTC0ENB = 0xb4:7;
sbit	FTC0RATE2 = 0xb4:6;
sbit	FTC0RATE1 = 0xb4:5;
sbit	FTC0RATE0 = 0xb4:4;
sbit	FTC0CKS1 = 0xb4:3;
sbit	FTC0CKS0 = 0xb4:2;
sbit	FPWM0OUT = 0xb4:0;
sfr	TC0C = 0xb5;
sbit	FTC0C7 = 0xb5:7;
sbit	FTC0C6 = 0xb5:6;
sbit	FTC0C5 = 0xb5:5;
sbit	FTC0C4 = 0xb5:4;
sbit	FTC0C3 = 0xb5:3;
sbit	FTC0C2 = 0xb5:2;
sbit	FTC0C1 = 0xb5:1;
sbit	FTC0C0 = 0xb5:0;
sfr	TC0R = 0xb6;
sfr	TC0D = 0xb7;
sbit	FTC0D7 = 0xb7:7;
sbit	FTC0D6 = 0xb7:6;
sbit	FTC0D5 = 0xb7:5;
sbit	FTC0D4 = 0xb7:4;
sbit	FTC0D3 = 0xb7:3;
sbit	FTC0D2 = 0xb7:2;
sbit	FTC0D1 = 0xb7:1;
sbit	FTC0D0 = 0xb7:0;
sfr	ADM2 = 0xb9;
sbit	FGCHS2 = 0xb9:7;
sfr	AIN2M = 0xba;
sbit	FAIN2M5 = 0xba:5;
sbit	FAIN2M4 = 0xba:4;
sbit	FAIN2M3 = 0xba:3;
sbit	FAIN2M2 = 0xba:2;
sbit	FAIN2M1 = 0xba:1;
sbit	FAIN2M0 = 0xba:0;
sfr	AIN3M = 0xbb;
sbit	FAIN3M5 = 0xbb:5;
sbit	FAIN3M4 = 0xbb:4;
sbit	FAIN3M3 = 0xbb:3;
sbit	FAIN3M2 = 0xbb:2;
sbit	FAIN3M1 = 0xbb:1;
sbit	FAIN3M0 = 0xbb:0;
sfr	AIN4M = 0xbc;
sbit	FAIN4M5 = 0xbc:5;
sbit	FAIN4M4 = 0xbc:4;
sbit	FAIN4M3 = 0xbc:3;
sbit	FAIN4M2 = 0xbc:2;
sbit	FAIN4M1 = 0xbc:1;
sbit	FAIN4M0 = 0xbc:0;
sfr	AIN5M = 0xbd;
sbit	FAIN5M5 = 0xbd:5;
sbit	FAIN5M4 = 0xbd:4;
sbit	FAIN5M3 = 0xbd:3;
sbit	FAIN5M2 = 0xbd:2;
sbit	FAIN5M1 = 0xbd:1;
sbit	FAIN5M0 = 0xbd:0;
sfr	T1M = 0xc0;
sbit	FT1ENB = 0xc0:7;
sbit	FT1RATE2 = 0xc0:6;
sbit	FT1RATE1 = 0xc0:5;
sbit	FT1RATE0 = 0xc0:4;
sbit	FT1CKS = 0xc0:3;
sfr	T1CL = 0xc1;
sbit	FT1C7 = 0xc1:7;
sbit	FT1C6 = 0xc1:6;
sbit	FT1C5 = 0xc1:5;
sbit	FT1C4 = 0xc1:4;
sbit	FT1C3 = 0xc1:3;
sbit	FT1C2 = 0xc1:2;
sbit	FT1C1 = 0xc1:1;
sbit	FT1C0 = 0xc1:0;
sfr	T1CH = 0xc2;
sbit	FT1C15 = 0xc2:7;
sbit	FT1C14 = 0xc2:6;
sbit	FT1C13 = 0xc2:5;
sbit	FT1C12 = 0xc2:4;
sbit	FT1C11 = 0xc2:3;
sbit	FT1C10 = 0xc2:2;
sbit	FT1C9 = 0xc2:1;
sbit	FT1C8 = 0xc2:0;
sfr	P4CON = 0xc6;
sbit	FP4CON1 = 0xc6:1;
sbit	FP4CON0 = 0xc6:0;
sfr	ADM = 0xc8;
sbit	FADENB = 0xc8:7;
sbit	FADS = 0xc8:6;
sbit	FEOC = 0xc8:5;
sbit	FGCHS = 0xc8:4;
sbit	FCHS1 = 0xc8:1;
sbit	FCHS0 = 0xc8:0;
sfr	ADB = 0xc9;
sbit	FADB11 = 0xc9:7;
sbit	FADB10 = 0xc9:6;
sbit	FADB9 = 0xc9:5;
sbit	FADB8 = 0xc9:4;
sbit	FADB7 = 0xc9:3;
sbit	FADB6 = 0xc9:2;
sbit	FADB5 = 0xc9:1;
sbit	FADB4 = 0xc9:0;
sfr	ADR = 0xca;
sbit	FADCKS1 = 0xca:6;
sbit	FADCKS0 = 0xca:5;
sbit	FADLEN = 0xca:4;
sbit	FADB3 = 0xca:3;
sbit	FADB2 = 0xca:2;
sbit	FADB1 = 0xca:1;
sbit	FADB0 = 0xca:0;
sfr	PECMD = 0xcc;
sfr	PEROML = 0xcd;
sfr	PEROMH = 0xce;
sfr	PERAML = 0xcf;
sfr	PERAMCNT = 0xd0;
sfr	SIOM = 0xd1;
sbit	FSENB = 0xd1:7;
sbit	FSTART = 0xd1:6;
sbit	FSRATE1 = 0xd1:5;
sbit	FSRATE0 = 0xd1:4;
sbit	FMLSB = 0xd1:3;
sbit	FSCKMD = 0xd1:2;
sbit	FCPOL = 0xd1:1;
sbit	FCPHA = 0xd1:0;
sfr	SIOR = 0xd2;
sfr	SIOB = 0xd3;
sfr	SIOC = 0xd4;
sbit	FSIOBZ = 0xd4:2;
sfr	URTX = 0xd5;
sbit	FUTXEN = 0xd5:7;
sbit	FUTXPEN = 0xd5:6;
sbit	FUTXPS = 0xd5:5;
sbit	FUTXBRK = 0xd5:4;
sbit	FURXBZ = 0xd5:3;
sbit	FUTXBZ = 0xd5:2;
sfr	URRX = 0xd6;
sbit	FURXEN = 0xd6:7;
sbit	FURXPEN = 0xd6:6;
sbit	FURXPS = 0xd6:5;
sbit	FURXPC = 0xd6:4;
sbit	FUFMER = 0xd6:3;
sbit	FURS2 = 0xd6:2;
sbit	FURS1 = 0xd6:1;
sbit	FURS0 = 0xd6:0;
sfr	URCR = 0xd7;
sfr	UTXD = 0xd8;
sfr	URXD = 0xd9;
sfr	MSPSTAT = 0xda;
sbit	FCKE = 0xda:6;
sbit	FD_A = 0xda:5;
sbit	FP = 0xda:4;
sbit	FS = 0xda:3;
sbit	FRED_WRT = 0xda:2;
sbit	FBF = 0xda:0;
sfr	MSPM1 = 0xdb;
sbit	FWCOL = 0xdb:7;
sbit	FMSPOV = 0xdb:6;
sbit	FMSPENB = 0xdb:5;
sbit	FCKP = 0xdb:4;
sbit	FSLRXCKP = 0xdb:3;
sbit	FMSPWK = 0xdb:2;
sbit	FMSPC = 0xdb:0;
sfr	MSPM2 = 0xdc;
sbit	FGCEN = 0xdc:7;
sbit	FACKSTAT = 0xdc:6;
sbit	FACKDT = 0xdc:5;
sbit	FACKEN = 0xdc:4;
sbit	FRCEN = 0xdc:3;
sbit	FPEN = 0xdc:2;
sbit	FRSEN = 0xdc:1;
sbit	FSEN = 0xdc:0;
sfr	MSPBUF = 0xdd;
sbit	FMSPBUF7 = 0xdd:7;
sbit	FMSPBUF6 = 0xdd:6;
sbit	FMSPBUF5 = 0xdd:5;
sbit	FMSPBUF4 = 0xdd:4;
sbit	FMSPBUF3 = 0xdd:3;
sbit	FMSPBUF2 = 0xdd:2;
sbit	FMSPBUF1 = 0xdd:1;
sbit	FMSPBUF0 = 0xdd:0;
sfr	MSPADR = 0xde;
sbit	FMSPADR7 = 0xde:7;
sbit	FMSPADR6 = 0xde:6;
sbit	FMSPADR5 = 0xde:5;
sbit	FMSPADR4 = 0xde:4;
sbit	FMSPADR3 = 0xde:3;
sbit	FMSPADR2 = 0xde:2;
sbit	FMSPADR1 = 0xde:1;
sbit	FMSPADR0 = 0xde:0;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FLVD23 = 0xdf:6;
sbit	FLVD30 = 0xdf:5;
sbit	FSTKPB3 = 0xdf:3;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	STKFL = 0xe0;
sfr	STKFH = 0xe1;
sfr	STKEL = 0xe2;
sfr	STKEH = 0xe3;
sfr	STKDL = 0xe4;
sfr	STKDH = 0xe5;
sfr	STKCL = 0xe6;
sfr	STKCH = 0xe7;
sfr	STKBL = 0xe8;
sfr	STKBH = 0xe9;
sfr	STKAL = 0xea;
sfr	STKAH = 0xeb;
sfr	STK9L = 0xec;
sfr	STK9H = 0xed;
sfr	STK8L = 0xee;
sfr	STK8H = 0xef;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SLowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
