#ifndef __SN8P2201__H
#define __SN8P2201__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sfr	UDA = 0xa0;
sbit	FUDE = 0xa0:7;
sbit	FUDA6 = 0xa0:6;
sbit	FUDA5 = 0xa0:5;
sbit	FUDA4 = 0xa0:4;
sbit	FUDA3 = 0xa0:3;
sbit	FUDA2 = 0xa0:2;
sbit	FUDA1 = 0xa0:1;
sbit	FUDA0 = 0xa0:0;
sfr	UE0R = 0xa1;
sbit	FUE0E = 0xa1:7;
sbit	FUE0S = 0xa1:6;
sbit	FUE0DO = 0xa1:5;
sbit	FUE0DI = 0xa1:4;
sbit	FUE0C3 = 0xa1:3;
sbit	FUE0C2 = 0xa1:2;
sbit	FUE0C1 = 0xa1:1;
sbit	FUE0C0 = 0xa1:0;
sfr	UE1R = 0xa2;
sbit	FUE1E = 0xa2:7;
sbit	FFFS1 = 0xa2:6;
sbit	FUE1DO = 0xa2:5;
sbit	FUE1DI = 0xa2:4;
sbit	FUE1C3 = 0xa2:3;
sbit	FUE1C2 = 0xa2:2;
sbit	FUE1C1 = 0xa2:1;
sbit	FUE1C0 = 0xa2:0;
sfr	UE2R = 0xa3;
sbit	FUE2E = 0xa3:7;
sbit	FFFS2 = 0xa3:6;
sbit	FUE2DO = 0xa3:5;
sbit	FUE2DI = 0xa3:4;
sbit	FUE2C3 = 0xa3:3;
sbit	FUE2C2 = 0xa3:2;
sbit	FUE2C1 = 0xa3:1;
sbit	FUE2C0 = 0xa3:0;
sfr	UE3R = 0xa4;
sbit	FUE3E = 0xa4:7;
sbit	FFFS3 = 0xa4:6;
sbit	FUE3DO = 0xa4:5;
sbit	FUE3DI = 0xa4:4;
sbit	FUE3C3 = 0xa4:3;
sbit	FUE3C2 = 0xa4:2;
sbit	FUE3C1 = 0xa4:1;
sbit	FUE3C0 = 0xa4:0;
sfr	UDP0 = 0xa5;
sbit	FUDP04 = 0xa5:4;
sbit	FUDP03 = 0xa5:3;
sbit	FUDP02 = 0xa5:2;
sbit	FUDP01 = 0xa5:1;
sbit	FUDP00 = 0xa5:0;
sfr	UDR0 = 0xa6;
sbit	FUDR07 = 0xa6:7;
sbit	FUDR06 = 0xa6:6;
sbit	FUDR05 = 0xa6:5;
sbit	FUDR04 = 0xa6:4;
sbit	FUDR03 = 0xa6:3;
sbit	FUDR02 = 0xa6:2;
sbit	FUDR01 = 0xa6:1;
sbit	FUDR00 = 0xa6:0;
sfr	UDP1 = 0xa7;
sbit	FUDP14 = 0xa7:4;
sbit	FUDP13 = 0xa7:3;
sbit	FUDP12 = 0xa7:2;
sbit	FUDP11 = 0xa7:1;
sbit	FUDP10 = 0xa7:0;
sfr	UDR1 = 0xa8;
sbit	FUDR17 = 0xa8:7;
sbit	FUDR16 = 0xa8:6;
sbit	FUDR15 = 0xa8:5;
sbit	FUDR14 = 0xa8:4;
sbit	FUDR13 = 0xa8:3;
sbit	FUDR12 = 0xa8:2;
sbit	FUDR11 = 0xa8:1;
sbit	FUDR10 = 0xa8:0;
sfr	USTATUS = 0xa9;
sbit	FFFS0 = 0xa9:7;
sbit	FUSPND = 0xa9:6;
sbit	FURST = 0xa9:5;
sbit	FUEP0OC4 = 0xa9:4;
sbit	FUEP0OC3 = 0xa9:3;
sbit	FUEP0OC2 = 0xa9:2;
sbit	FUEP0OC1 = 0xa9:1;
sbit	FUEP0OC0 = 0xa9:0;
sfr	UPID = 0xaa;
sbit	FUBDE = 0xaa:2;
sbit	FDDP = 0xaa:1;
sbit	FDDN = 0xaa:0;
sfr	T1M = 0xab;
sbit	FT1ENB = 0xab:7;
sbit	FT1rate2 = 0xab:6;
sbit	FT1rate1 = 0xab:5;
sbit	FT1rate0 = 0xab:4;
sbit	FT1G1 = 0xab:1;
sbit	FT1G0 = 0xab:0;
sfr	T1C = 0xac;
sbit	FT1C7 = 0xac:7;
sbit	FT1C6 = 0xac:6;
sbit	FT1C5 = 0xac:5;
sbit	FT1C4 = 0xac:4;
sbit	FT1C3 = 0xac:3;
sbit	FT1C2 = 0xac:2;
sbit	FT1C1 = 0xac:1;
sbit	FT1C0 = 0xac:0;
sfr	T2M = 0xad;
sbit	FT2ENB = 0xad:7;
sbit	FT2rate2 = 0xad:6;
sbit	FT2rate1 = 0xad:5;
sbit	FT2rate0 = 0xad:4;
sbit	FT2G1 = 0xad:1;
sbit	FT2G0 = 0xad:0;
sfr	T2C = 0xae;
sbit	FT2C7 = 0xae:7;
sbit	FT2C6 = 0xae:6;
sbit	FT2C5 = 0xae:5;
sbit	FT2C4 = 0xae:4;
sbit	FT2C3 = 0xae:3;
sbit	FT2C2 = 0xae:2;
sbit	FT2C1 = 0xae:1;
sbit	FT2C0 = 0xae:0;
sfr	PS2M = 0xaf;
sbit	FPS2ENB = 0xaf:7;
sbit	FSDA = 0xaf:3;
sbit	FSCK = 0xaf:2;
sbit	FSDAM = 0xaf:1;
sbit	FSCKM = 0xaf:0;
sfr	P0M = 0xb8;
sbit	FP06M = 0xb8:6;
sbit	FP05M = 0xb8:5;
sbit	FP04M = 0xb8:4;
sbit	FP03M = 0xb8:3;
sbit	FP02M = 0xb8:2;
sbit	FP01M = 0xb8:1;
sbit	FP00M = 0xb8:0;
sfr	PEDGE = 0xbf;
sbit	FP00G1 = 0xbf:4;
sbit	FP00G0 = 0xbf:3;
sfr	P1W = 0xc0;
sbit	FP17W = 0xc0:7;
sbit	FP16W = 0xc0:6;
sbit	FP15W = 0xc0:5;
sbit	FP14W = 0xc0:4;
sbit	FP13W = 0xc0:3;
sbit	FP12W = 0xc0:2;
sbit	FP11W = 0xc0:1;
sbit	FP10W = 0xc0:0;
sfr	P1M = 0xc1;
sbit	FP17M = 0xc1:7;
sbit	FP16M = 0xc1:6;
sbit	FP15M = 0xc1:5;
sbit	FP13M = 0xc1:3;
sbit	FP12M = 0xc1:2;
sbit	FP11M = 0xc1:1;
sbit	FP10M = 0xc1:0;
sfr	P5M = 0xc5;
sbit	FP57M = 0xc5:7;
sbit	FP56M = 0xc5:6;
sbit	FP55M = 0xc5:5;
sbit	FP54M = 0xc5:4;
sbit	FP53M = 0xc5:3;
sbit	FP52M = 0xc5:2;
sbit	FP51M = 0xc5:1;
sbit	FP50M = 0xc5:0;
sfr	P6M = 0xc6;
sbit	FP61M = 0xc6:1;
sbit	FP60M = 0xc6:0;
sfr	INTRQ = 0xc8;
sbit	FUSBIRQ = 0xc8:6;
sbit	FTC0IRQ = 0xc8:5;
sbit	FT0IRQ = 0xc8:4;
sbit	FT2IRQ = 0xc8:2;
sbit	FT1IRQ = 0xc8:1;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN = 0xc9;
sbit	FUSBIEN = 0xc9:6;
sbit	FTC0IEN = 0xc9:5;
sbit	FT0IEN = 0xc9:4;
sbit	FT2IEN = 0xc9:2;
sbit	FT1IEN = 0xc9:1;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	TC0R = 0xcd;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP06 = 0xd0:6;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP17 = 0xd1:7;
sbit	FP16 = 0xd1:6;
sbit	FP15 = 0xd1:5;
sbit	FP14 = 0xd1:4;
sbit	FP13 = 0xd1:3;
sbit	FP12 = 0xd1:2;
sbit	FP11 = 0xd1:1;
sbit	FP10 = 0xd1:0;
sfr	P5 = 0xd5;
sbit	FP57 = 0xd5:7;
sbit	FP56 = 0xd5:6;
sbit	FP55 = 0xd5:5;
sbit	FP54 = 0xd5:4;
sbit	FP53 = 0xd5:3;
sbit	FP52 = 0xd5:2;
sbit	FP51 = 0xd5:1;
sbit	FP50 = 0xd5:0;
sfr	P6 = 0xd6;
sbit	FP61 = 0xd6:1;
sbit	FP60 = 0xd6:0;
sfr	T0M = 0xd8;
sbit	FT0ENB = 0xd8:7;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE0 = 0xd8:4;
sbit	FT0TB = 0xd8:0;
sfr	T0C = 0xd9;
sfr	TC0M = 0xda;
sbit	FTC0ENB = 0xda:7;
sbit	FTC0RATE2 = 0xda:6;
sbit	FTC0RATE1 = 0xda:5;
sbit	FTC0RATE0 = 0xda:4;
sbit	FTC0CKS = 0xda:3;
sbit	FALOAD0 = 0xda:2;
sbit	FTC0OUT = 0xda:1;
sbit	FPWM0OUT = 0xda:0;
sfr	TC0C = 0xdb;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sfr	P1UR = 0xe1;
sfr	P5UR = 0xe5;
sfr	_YZ = 0xe7;
sfr	P1OC = 0xe9;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
