<?xml version="1.0" encoding="UTF-8"?>
<chip>
	<configure-file-ver>1.0</configure-file-ver>
	<chip-name>HS23F2211</chip-name>
	<chip-classes>Flash</chip-classes>
	<chip-id>72</chip-id>
	<chip-ver>0</chip-ver>
	<ccs-file-ver>4</ccs-file-ver>
	<ram-start-addr>0</ram-start-addr>
	<ram-size>256</ram-size>
	<otp-body-size>2048</otp-body-size>
	<user-rom-size>2048</user-rom-size>
	<reset-addr>7ff</reset-addr>
	<stack-level>5</stack-level>
	<config-word-count>5</config-word-count>	
	<max-breakpoint>16</max-breakpoint>
	<asm-inc>$(DevEnvDir)\asm_inc\$(ChipName).inc</asm-inc>
	<clang-inc>$(DevEnvDir)\include\$(ChipName).h</clang-inc>			
	<description></description>
	<rams>
		<ram mode="fpga" start-addr="0" length="256">
			<ram-segment start-addr="00" size="16" write-addr="00" read-addr="00" value-addr="00" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="10" size="64" write-addr="10" read-addr="10" value-addr="10" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="50" size="48" write-addr="50" read-addr="50" value-addr="50" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="90" size="64" write-addr="90" read-addr="90" value-addr="90" visiable="true" bank="1"></ram-segment>
			<ram-segment start-addr="d0" size="48" write-addr="d0" read-addr="d0" value-addr="d0" visiable="false" bank="1"></ram-segment>	
			<ram-segment start-addr="8000" size="8" write-addr="8000" read-addr="8000" value-addr="8000" visiable="false" bank="-1"></ram-segment>				
		</ram>
		<ram mode="ic" start-addr="0" length="256">
			<ram-segment start-addr="00" size="16" write-addr="00" read-addr="00" value-addr="00" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="10" size="64" write-addr="10" read-addr="10" value-addr="10" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="50" size="48" write-addr="50" read-addr="50" value-addr="50" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="90" size="64" write-addr="8000" read-addr="8000" value-addr="90" visiable="true" bank="1"></ram-segment>
			<ram-segment start-addr="d0" size="48" write-addr="8050" read-addr="8050" value-addr="d0" visiable="false" bank="1"></ram-segment>	
			<ram-segment start-addr="3f0" size="7" write-addr="3f0" read-addr="3f0" value-addr="3f0" visiable="false" bank="-1"></ram-segment>	
		</ram>	
		<ram mode="ic_3211" start-addr="0" length="256">
			<ram-segment start-addr="00" size="16" write-addr="00" read-addr="00" value-addr="00" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="10" size="64" write-addr="10" read-addr="10" value-addr="10" visiable="true" bank="0"></ram-segment>
			<ram-segment start-addr="50" size="48" write-addr="50" read-addr="50" value-addr="50" visiable="false" bank="0"></ram-segment>
			<ram-segment start-addr="90" size="64" write-addr="110" read-addr="110" value-addr="90" visiable="true" bank="1"></ram-segment>
			<ram-segment start-addr="d0" size="48" write-addr="150" read-addr="150" value-addr="d0" visiable="false" bank="1"></ram-segment>	
			<ram-segment start-addr="3f0" size="7" write-addr="3f0" read-addr="3f0" value-addr="3f0" visiable="false" bank="-1"></ram-segment>	
			<ram-segment start-addr="ff0" size="1" write-addr="ff0" read-addr="ff0" value-addr="ff0" visiable="false" bank="-1"></ram-segment>
		</ram>		
	</rams>
	<configs>
		<config-word index="0" or-value="0000" and-value="ffff" mapto="0"></config-word>
		<config-word index="1" or-value="0000" and-value="ffff" mapto="1"></config-word>	
		<config-word index="2" or-value="0000" and-value="ffff" mapto="3"></config-word>
		<config-word index="3" or-value="0000" and-value="ffff" mapto="2"></config-word>	
		<config-word index="4" or-value="0000" and-value="ffff" mapto="4"></config-word>	
		
		<config-item name="加密" width="1" offset="1" default-value="1" enable="true" config-index="1">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>加密</description>
		</config-item>				
		<config-item name="复位管脚" width="1" offset="12" default-value="1" enable="true" config-index="0">
			<config-item-value name="As RESET Pin" value="0"></config-item-value>
			<config-item-value name="As IO" value="1"></config-item-value>
			<description>PB3功能</description>
		</config-item>
		<config-item name="看门狗" width="1" offset="0" default-value="1" enable="true" config-index="1">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="Enable" value="1"></config-item-value>
			<description>看门狗</description>
		</config-item>			
		<config-item name="OSC Pin" width="1" offset="11" default-value="0" enable="true" config-index="0">
			<config-item-value name="As IO" value="0"></config-item-value>
			<config-item-value name="As OSCO" value="1"></config-item-value>
			<description>PB4功能</description>
		</config-item>	
		<config-item name="分频数选择" width="2" offset="2" default-value="2" enable="true" config-index="1">
			<config-item-value name="4分频" value="0"></config-item-value>
			<config-item-value name="2分频" value="2"></config-item-value>
			<config-item-value name="8分频" value="3"></config-item-value>
			<description>系统分频</description>
		</config-item>	
		<config-item name="振荡频率模式" width="1" offset="2" default-value="0" enable="true" config-index="0">
			<config-item-value name="IRC" value="0"></config-item-value>
			<config-item-value name="IRC and RTC" value="1"></config-item-value>
			<description>时钟源选择</description>
		</config-item>			
		<config-item name="复位时间" width="3" offset="8" default-value="3" enable="true" config-index="0">
			<config-item-value name="PWRT=WDT=18ms" value="0"></config-item-value>
			<config-item-value name="PWRT=WDT=4.5ms" value="1"></config-item-value>
			<config-item-value name="PWRT=WDT=288ms" value="2"></config-item-value>
			<config-item-value name="PWRT=WDT=72ms" value="3"></config-item-value>
			<config-item-value name="PWRT=640us,WDT=18ms" value="4"></config-item-value>
			<config-item-value name="PWRT=640us,WDT=4.5ms" value="5"></config-item-value>
			<config-item-value name="PWRT=640us,WDT=288ms" value="6"></config-item-value>
			<config-item-value name="PWRT=640us,WDT=72ms" value="7"></config-item-value>
			<description>PWRT</description>
		</config-item>
		<config-item name="内置RC频率" width="2" offset="6" default-value="0" enable="true" config-index="0">
			<config-item-value name="4M" value="0"></config-item-value>
			<config-item-value name="8M" value="1"></config-item-value>
			<config-item-value name="1M" value="2"></config-item-value>
			<config-item-value name="455K" value="3"></config-item-value>
			<description>FIRC</description>
		</config-item>	
		<config-item name="低压检测" width="3" offset="3" default-value="2" enable="true" config-index="0">
			<config-item-value name="Disable" value="0"></config-item-value>
			<config-item-value name="2.0v" value="1"></config-item-value>
			<config-item-value name="2.2v" value="2"></config-item-value>
			<config-item-value name="2.4v" value="3"></config-item-value>
			<config-item-value name="2.6v" value="4"></config-item-value>
			<config-item-value name="2.6v" value="5"></config-item-value>
			<config-item-value name="2.6v" value="6"></config-item-value>
			<config-item-value name="2.6v" value="7"></config-item-value>
			<description>LVD</description>
		</config-item>
		<config-item name="读端口" width="1" offset="5" default-value="0" enable="true" config-index="1">
			<config-item-value name="Form register" value="0"></config-item-value>
			<config-item-value name="Form Pins" value="1"></config-item-value>
			<description>读端口</description>
		</config-item>		
		<config-item name="施密特" width="1" offset="6" default-value="0" enable="true" config-index="1">
			<config-item-value name="有" value="0"></config-item-value>
			<config-item-value name="无" value="1"></config-item-value>
			<description>管脚施密特</description>
		</config-item>					
		<config-item name="32K晶振增强" width="1" offset="11" default-value="0" enable="true" config-index="1">
			<config-item-value name="不增强" value="0"></config-item-value>
			<config-item-value name="增强" value="1"></config-item-value>
			<description>外部32K晶振增强</description>
		</config-item>	
		<config-item name="Cycle" width="3" offset="8" default-value="0" enable="true" config-index="1">
			<config-item-value name="全周期" value="0"></config-item-value>
			<config-item-value name="半周期" value="4"></config-item-value>
			<config-item-value name="1/4周期" value="6"></config-item-value>
			<config-item-value name="低功耗模式" value="5"></config-item-value>
			<description>读周期选择</description>
		</config-item>		
		<config-item name="RC频率加倍" width="1" offset="13" default-value="0" enable="true" config-index="2">
			<config-item-value name="不加倍" value="0"></config-item-value>
			<config-item-value name="加倍" value="1"></config-item-value>
			<description>频率加倍</description>
		</config-item>						
	</configs>
		
	<sfrs>
		<sfr mode="fpga">
			<reg name="OPTION" addr="8001" read-addr="8001" write-addr="8001" value-addr="8001" addr-visiable="false" bank="-1">
				<bit name="PS0" offset="0"></bit>
				<bit name="PS1" offset="1"></bit>
				<bit name="PS2" offset="2"></bit>
				<bit name="PSA" offset="3"></bit>
				<bit name="T0SE" offset="4"></bit>
				<bit name="T0CS" offset="5"></bit>
				<bit name="INTEDG" offset="6"></bit>
				<bit name="INT1DGE" offset="7"></bit>
			</reg>		
		
			<reg name="ACC" addr="8007" read-addr="8007" write-addr="8007" value-addr="8007" addr-visiable="false" bank="-1"></reg>
			<reg name="INDF" addr="00" read-addr="00" write-addr="00" value-addr="00" addr-visiable="true" bank="0"></reg>
			<reg name="TMR0" addr="01"  read-addr="01" write-addr="01" value-addr="01" addr-visiable="true" bank="0"></reg>
			<reg name="PCL" addr="02" read-addr="02" write-addr="02" value-addr="02" addr-visiable="true" bank="0"></reg>
			<reg name="PCH" addr="8002" read-addr="8002" write-addr="8002" value-addr="8002" addr-visiable="false" bank="-1"></reg>
			
			<reg name="STATUS" addr="03" read-addr="03" write-addr="03" value-addr="03" addr-visiable="true" bank="0">
				<bit name="C" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="Z" offset="2"></bit>
				<bit name="PD" offset="3"></bit>
				<bit name="TO" offset="4"></bit>
				<bit name="RP0" offset="5"></bit>
				<bit name="RP1" offset="6"></bit>
				<bit name="RST" offset="7"></bit>
			</reg>
			
			<reg name="FSR" addr="04"  read-addr="04" write-addr="04" value-addr="04" addr-visiable="true" bank="0"></reg>	
			<reg name="PORTA" addr="05"  read-addr="05" write-addr="05" value-addr="05" addr-visiable="true" bank="0"></reg>
			<reg name="IOSTA" addr="8005"  read-addr="8005" write-addr="8005" value-addr="8005" addr-visiable="false" bank="-1"></reg>
			<reg name="PORTB" addr="06"  read-addr="06" write-addr="06" value-addr="06" addr-visiable="true" bank="0"></reg>
			<reg name="IOSTB" addr="8006"  read-addr="8006" write-addr="8006" value-addr="8006" addr-visiable="false" bank="-1"></reg>
			
			<reg name="PCON" addr="08" read-addr="08" write-addr="08" value-addr="08" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="LVDTE" offset="5"></bit>
				<bit name="EIS" offset="6"></bit>
				<bit name="WDTE" offset="7"></bit>
			</reg>			
			
			<reg name="WUCON" addr="09" read-addr="09" write-addr="09" value-addr="09" addr-visiable="true" bank="0"></reg>	
			<reg name="PCHBUF" addr="0a"  read-addr="0a" write-addr="0a" value-addr="0a" addr-visiable="true" bank="0"></reg>
			<reg name="PDCON" addr="0b"  read-addr="0b" write-addr="0b" value-addr="0b" addr-visiable="true" bank="0"></reg>
			<reg name="ODCON" addr="0c"  read-addr="0c" write-addr="0c" value-addr="0c" addr-visiable="true" bank="0"></reg>
			<reg name="PHCON" addr="0d"  read-addr="0d" write-addr="0d" value-addr="0d" addr-visiable="true" bank="0"></reg>

			<reg name="INTEN" addr="0e"  read-addr="0e" write-addr="0e" value-addr="0e" addr-visiable="true" bank="0">
				<bit name="T0IE" offset="0"></bit>
				<bit name="PBIE" offset="1"></bit>
				<bit name="INTIE" offset="2"></bit>	
				<bit name="TC0IE" offset="3"></bit>
				<bit name="TP0IE" offset="4"></bit>	
				<bit name="INT1IE" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>			
			
			<reg name="INTFLAG" addr="0f"  read-addr="0f" write-addr="0f" value-addr="0f" addr-visiable="true" bank="0">
				<bit name="T0IF" offset="0"></bit>
				<bit name="PBIF" offset="1"></bit>
				<bit name="INTIF" offset="2"></bit>	
				<bit name="TC0IF" offset="3"></bit>	
				<bit name="TP0IF" offset="4"></bit>	
				<bit name="INT1IF" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>			
			
			<reg name="PWM0EN" addr="50" read-addr="50" write-addr="50" value-addr="50" addr-visiable="true" bank="0">
				<bit name="PWM0EN" offset="0"></bit>
				<bit name="PWM0OEN" offset="1"></bit>
				<bit name="PWM01OEN" offset="2"></bit>	
				<bit name="PWM0M" offset="3"></bit>	
				<bit name="PWM1OEN" offset="4"></bit>	
				<bit name="TPSEL8" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="TPEN" offset="7"></bit>
			</reg>		
			
			<reg name="PWM0C" addr="51" read-addr="51" write-addr="51" value-addr="51" addr-visiable="true" bank="0">
				<bit name="CK0" offset="0"></bit>
				<bit name="CK1" offset="1"></bit>
				<bit name="PWM0S0" offset="2"></bit>	
				<bit name="PWM0S1" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="CK2" offset="6"></bit>
				<bit name="CK3" offset="7"></bit>
			</reg>		

			<reg name="PWM0TL" addr="52" read-addr="52" write-addr="52" value-addr="52" addr-visiable="true" bank="0"></reg>		
			<reg name="PWM0TH" addr="53" read-addr="53" write-addr="53" value-addr="53" addr-visiable="true" bank="0"></reg>	
			<reg name="PWM0PL" addr="54" read-addr="54" write-addr="54" value-addr="54" addr-visiable="true" bank="0"></reg>	
			<reg name="PWM0PH" addr="55" read-addr="55" write-addr="55" value-addr="55" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DL" addr="56" read-addr="56" write-addr="56" value-addr="56" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DH" addr="57" read-addr="57" write-addr="57" value-addr="57" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DTL" addr="58" read-addr="58" write-addr="58" value-addr="58" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DTH" addr="59" read-addr="59" write-addr="59" value-addr="59" addr-visiable="true" bank="0"></reg>
			
			<reg name="PWMPSCON" addr="5b" read-addr="5b" write-addr="5b" value-addr="5b" addr-visiable="true" bank="0">
				<bit name="PWM0S0" offset="0"></bit>
				<bit name="PWM0S1" offset="1"></bit>
				<bit name="PWM01S0" offset="2"></bit>	
				<bit name="PWM01S1" offset="3"></bit>	
				<bit name="PWM1S0" offset="4"></bit>	
				<bit name="PWM1S0" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>
			
			<reg name="PWM1DL" addr="60" read-addr="60" write-addr="60" value-addr="60" addr-visiable="true" bank="0"></reg>
			<reg name="PWM1DH" addr="61" read-addr="61" write-addr="61" value-addr="61" addr-visiable="true" bank="0"></reg>

			<reg name="PBIC0" addr="6d" read-addr="6d" write-addr="6d" value-addr="6d" addr-visiable="true" bank="0"></reg>
			<reg name="PAHCON" addr="6e" read-addr="6e" write-addr="6e" value-addr="6e" addr-visiable="true" bank="0"></reg>
			<reg name="PAIC0" addr="70" read-addr="70" write-addr="70" value-addr="70" addr-visiable="true" bank="0"></reg>
			<reg name="TC0L" addr="71" read-addr="71" write-addr="71" value-addr="71" addr-visiable="true" bank="0"></reg>
			<reg name="TC0M" addr="72" read-addr="72" write-addr="72" value-addr="72" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R" addr="73" read-addr="73" write-addr="73" value-addr="73" addr-visiable="true" bank="0"></reg>
			<reg name="TC0H" addr="74" read-addr="74" write-addr="74" value-addr="74" addr-visiable="true" bank="0"></reg>
			<reg name="TC0D1" addr="75" read-addr="75" write-addr="75" value-addr="75" addr-visiable="true" bank="0"></reg>
			<reg name="TC0D2" addr="76" read-addr="76" write-addr="76" value-addr="76" addr-visiable="true" bank="0"></reg>

			<reg name="PWMCON" addr="77"  read-addr="77" write-addr="77" value-addr="77" addr-visiable="true" bank="0">
				<bit name="PWM1EN" offset="0"></bit>
				<bit name="PWM2EN" offset="1"></bit>
				<bit name="PWM1S" offset="2"></bit>	
				<bit name="PWM2S" offset="3"></bit>	
				<bit name="PWM1XR0" offset="4"></bit>	
				<bit name="PWM1XR1" offset="5"></bit>	
				<bit name="PWM2XR0" offset="6"></bit>
				<bit name="PWM2XR1" offset="7"></bit>		
			</reg>	

			<reg name="PADCON" addr="78" read-addr="78" write-addr="78" value-addr="78" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="PADC4" offset="4"></bit>
				<bit name="PADC5" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>	
			
			<reg name="OSCM" addr="79" read-addr="79" write-addr="79" value-addr="79" addr-visiable="true" bank="0">
				<bit name="CLKMD" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="XTSEL" offset="2"></bit>	
				<bit name="SLCON" offset="3"></bit>	
				<bit name="SLT0C" offset="4"></bit>	
				<bit name="GREENEN" offset="5"></bit>	
				<bit name="WAKEMODE" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	

			<reg name="EECON1" addr="7a" read-addr="7a" write-addr="7a" value-addr="7a" addr-visiable="true" bank="0">
				<bit name="READEE" offset="0"></bit>
				<bit name="PROGEE" offset="1"></bit>
				<bit name="ERASEEE" offset="2"></bit>	
				<bit name="ERSALLEE" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="TIMEE" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	
	
			<reg name="EEADRL" addr="7c" read-addr="7c" write-addr="7c" value-addr="7c" addr-visiable="true" bank="0"></reg>	
			<reg name="EEDATL" addr="7e" read-addr="7e" write-addr="7e" value-addr="7e" addr-visiable="true" bank="0"></reg>
							
			<reg name="CMPC" addr="99" read-addr="99" write-addr="99" value-addr="99" addr-visiable="true" bank="1">
				<bit name="--" offset="0"></bit>
				<bit name="COPOL" offset="1"></bit>
				<bit name="CVEN" offset="2"></bit>	
				<bit name="CPEN" offset="3"></bit>	
				<bit name="CODEB" offset="4"></bit>	
				<bit name="FTCKS" offset="5"></bit>	
				<bit name="CMPIF" offset="6"></bit>
				<bit name="CMPEN" offset="7"></bit>			
			</reg>
			<reg name="CMPM" addr="9a" read-addr="9a" write-addr="9a" value-addr="9a" addr-visiable="true" bank="1">
				<bit name="VRS0" offset="0"></bit>
				<bit name="VRS1" offset="1"></bit>
				<bit name="VRS2" offset="2"></bit>	
				<bit name="VRS3" offset="3"></bit>	
				<bit name="XRVSEL" offset="4"></bit>	
				<bit name="CPINS0" offset="5"></bit>	
				<bit name="CPINS1" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	
		
			<reg name="INTEN1" addr="9e" read-addr="9e" write-addr="9e" value-addr="9e" addr-visiable="true" bank="1">
				<bit name="TKINTEN" offset="0"></bit>
				<bit name="COMINTEN" offset="1"></bit>	
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>	
				<bit name="--" offset="7"></bit>			
			</reg>			
			
			<reg name="INTFLAG1" addr="9f"  read-addr="9f" write-addr="9f" value-addr="9f" addr-visiable="true" bank="1">
				<bit name="TKINTF" offset="0"></bit>
				<bit name="COMINTF" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>			
		</sfr>
		
		<sfr mode="ic">
			<reg name="OPTION" addr="3f4" read-addr="3f4" write-addr="3f4" value-addr="3f4" addr-visiable="false" bank="-1">
				<bit name="PS0" offset="0"></bit>
				<bit name="PS1" offset="1"></bit>
				<bit name="PS2" offset="2"></bit>
				<bit name="PSA" offset="3"></bit>
				<bit name="T0SE" offset="4"></bit>
				<bit name="T0CS" offset="5"></bit>
				<bit name="INTEDG" offset="6"></bit>
				<bit name="INT1DGE" offset="7"></bit>
			</reg>		
		
			<reg name="ACC" addr="3f0" read-addr="3f0" write-addr="3f0" value-addr="3f0" addr-visiable="false" bank="-1"></reg>
			<reg name="INDF" addr="00" read-addr="00" write-addr="00" value-addr="00" addr-visiable="true" bank="0"></reg>
			<reg name="TMR0" addr="01"  read-addr="01" write-addr="01" value-addr="01" addr-visiable="true" bank="0"></reg>
			<reg name="PCL" addr="02" read-addr="02" write-addr="02" value-addr="02" addr-visiable="true" bank="0"></reg>
			<reg name="PCH" addr="8002" read-addr="8002" write-addr="8002" value-addr="8002" addr-visiable="false" bank="-1"></reg>
			
			<reg name="STATUS" addr="03" read-addr="03" write-addr="03" value-addr="03" addr-visiable="true" bank="0">
				<bit name="C" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="Z" offset="2"></bit>
				<bit name="PD" offset="3"></bit>
				<bit name="TO" offset="4"></bit>
				<bit name="RP0" offset="5"></bit>
				<bit name="RP1" offset="6"></bit>
				<bit name="RST" offset="7"></bit>
			</reg>
			
			<reg name="FSR" addr="04"  read-addr="04" write-addr="04" value-addr="04" addr-visiable="true" bank="0"></reg>	
			<reg name="PORTA" addr="05"  read-addr="05" write-addr="05" value-addr="05" addr-visiable="true" bank="0"></reg>
			<reg name="IOSTA" addr="3f5"  read-addr="3f5" write-addr="3f5" value-addr="3f5" addr-visiable="false" bank="-1"></reg>
			<reg name="PORTB" addr="06"  read-addr="06" write-addr="06" value-addr="06" addr-visiable="true" bank="0"></reg>
			<reg name="IOSTB" addr="3f6"  read-addr="3f6" write-addr="3f6" value-addr="3f6" addr-visiable="false" bank="-1"></reg>
			
			<reg name="PCON" addr="08" read-addr="08" write-addr="08" value-addr="08" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="LVDTE" offset="5"></bit>
				<bit name="EIS" offset="6"></bit>
				<bit name="WDTE" offset="7"></bit>
			</reg>			
			
			<reg name="WUCON" addr="09" read-addr="09" write-addr="09" value-addr="09" addr-visiable="true" bank="0"></reg>	
			<reg name="PCHBUF" addr="0a"  read-addr="0a" write-addr="0a" value-addr="0a" addr-visiable="true" bank="0"></reg>
			<reg name="PDCON" addr="0b"  read-addr="0b" write-addr="0b" value-addr="0b" addr-visiable="true" bank="0"></reg>
			<reg name="ODCON" addr="0c"  read-addr="0c" write-addr="0c" value-addr="0c" addr-visiable="true" bank="0"></reg>
			<reg name="PHCON" addr="0d"  read-addr="0d" write-addr="0d" value-addr="0d" addr-visiable="true" bank="0"></reg>

			<reg name="INTEN" addr="0e"  read-addr="0e" write-addr="0e" value-addr="0e" addr-visiable="true" bank="0">
				<bit name="T0IE" offset="0"></bit>
				<bit name="PBIE" offset="1"></bit>
				<bit name="INTIE" offset="2"></bit>	
				<bit name="TC0IE" offset="3"></bit>
				<bit name="TP0IE" offset="4"></bit>	
				<bit name="INT1IE" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>			
			
			<reg name="INTFLAG" addr="0f"  read-addr="0f" write-addr="0f" value-addr="0f" addr-visiable="true" bank="0">
				<bit name="T0IF" offset="0"></bit>
				<bit name="PBIF" offset="1"></bit>
				<bit name="INTIF" offset="2"></bit>	
				<bit name="TC0IF" offset="3"></bit>	
				<bit name="TP0IF" offset="4"></bit>	
				<bit name="INT1IF" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>			
			
			<reg name="PWM0EN" addr="50" read-addr="50" write-addr="50" value-addr="50" addr-visiable="true" bank="0">
				<bit name="PWM0EN" offset="0"></bit>
				<bit name="PWM0OEN" offset="1"></bit>
				<bit name="PWM01OEN" offset="2"></bit>	
				<bit name="PWM0M" offset="3"></bit>	
				<bit name="PWM1OEN" offset="4"></bit>	
				<bit name="TPSEL8" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="TPEN" offset="7"></bit>
			</reg>		
			
			<reg name="PWM0C" addr="51" read-addr="51" write-addr="51" value-addr="51" addr-visiable="true" bank="0">
				<bit name="CK0" offset="0"></bit>
				<bit name="CK1" offset="1"></bit>
				<bit name="PWM0S0" offset="2"></bit>	
				<bit name="PWM0S1" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="CK2" offset="6"></bit>
				<bit name="CK3" offset="7"></bit>
			</reg>		

			<reg name="PWM0TL" addr="52" read-addr="52" write-addr="52" value-addr="52" addr-visiable="true" bank="0"></reg>		
			<reg name="PWM0TH" addr="53" read-addr="53" write-addr="53" value-addr="53" addr-visiable="true" bank="0"></reg>	
			<reg name="PWM0PL" addr="54" read-addr="54" write-addr="54" value-addr="54" addr-visiable="true" bank="0"></reg>	
			<reg name="PWM0PH" addr="55" read-addr="55" write-addr="55" value-addr="55" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DL" addr="56" read-addr="56" write-addr="56" value-addr="56" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DH" addr="57" read-addr="57" write-addr="57" value-addr="57" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DTL" addr="58" read-addr="58" write-addr="58" value-addr="58" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DTH" addr="59" read-addr="59" write-addr="59" value-addr="59" addr-visiable="true" bank="0"></reg>
			
			<reg name="PWMPSCON" addr="5b" read-addr="5b" write-addr="5b" value-addr="5b" addr-visiable="true" bank="0">
				<bit name="PWM0S0" offset="0"></bit>
				<bit name="PWM0S1" offset="1"></bit>
				<bit name="PWM01S0" offset="2"></bit>	
				<bit name="PWM01S1" offset="3"></bit>	
				<bit name="PWM1S0" offset="4"></bit>	
				<bit name="PWM1S0" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>
			
			<reg name="PWM1DL" addr="60" read-addr="60" write-addr="60" value-addr="60" addr-visiable="true" bank="0"></reg>
			<reg name="PWM1DH" addr="61" read-addr="61" write-addr="61" value-addr="61" addr-visiable="true" bank="0"></reg>

			<reg name="PBIC0" addr="6d" read-addr="6d" write-addr="6d" value-addr="6d" addr-visiable="true" bank="0"></reg>
			<reg name="PAHCON" addr="6e" read-addr="6e" write-addr="6e" value-addr="6e" addr-visiable="true" bank="0"></reg>
			<reg name="PAIC0" addr="70" read-addr="70" write-addr="70" value-addr="70" addr-visiable="true" bank="0"></reg>
			<reg name="TC0L" addr="71" read-addr="71" write-addr="71" value-addr="71" addr-visiable="true" bank="0"></reg>
			<reg name="TC0M" addr="72" read-addr="72" write-addr="72" value-addr="72" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R" addr="73" read-addr="73" write-addr="73" value-addr="73" addr-visiable="true" bank="0"></reg>
			<reg name="TC0H" addr="74" read-addr="74" write-addr="74" value-addr="74" addr-visiable="true" bank="0"></reg>
			<reg name="TC0D1" addr="75" read-addr="75" write-addr="75" value-addr="75" addr-visiable="true" bank="0"></reg>
			<reg name="TC0D2" addr="76" read-addr="76" write-addr="76" value-addr="76" addr-visiable="true" bank="0"></reg>

			<reg name="PWMCON" addr="77"  read-addr="77" write-addr="77" value-addr="77" addr-visiable="true" bank="0">
				<bit name="PWM1EN" offset="0"></bit>
				<bit name="PWM2EN" offset="1"></bit>
				<bit name="PWM1S" offset="2"></bit>	
				<bit name="PWM2S" offset="3"></bit>	
				<bit name="PWM1XR0" offset="4"></bit>	
				<bit name="PWM1XR1" offset="5"></bit>	
				<bit name="PWM2XR0" offset="6"></bit>
				<bit name="PWM2XR1" offset="7"></bit>		
			</reg>	

			<reg name="PADCON" addr="78" read-addr="78" write-addr="78" value-addr="78" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="PADC4" offset="4"></bit>
				<bit name="PADC5" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>	
			
			<reg name="OSCM" addr="79" read-addr="79" write-addr="79" value-addr="79" addr-visiable="true" bank="0">
				<bit name="CLKMD" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="XTSEL" offset="2"></bit>	
				<bit name="SLCON" offset="3"></bit>	
				<bit name="SLT0C" offset="4"></bit>	
				<bit name="GREENEN" offset="5"></bit>	
				<bit name="WAKEMODE" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	

			<reg name="EECON1" addr="7a" read-addr="7a" write-addr="7a" value-addr="7a" addr-visiable="true" bank="0">
				<bit name="READEE" offset="0"></bit>
				<bit name="PROGEE" offset="1"></bit>
				<bit name="ERASEEE" offset="2"></bit>	
				<bit name="ERSALLEE" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="TIMEE" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	
	
			<reg name="EEADRL" addr="7c" read-addr="7c" write-addr="7c" value-addr="7c" addr-visiable="true" bank="0"></reg>	
			<reg name="EEDATL" addr="7e" read-addr="7e" write-addr="7e" value-addr="7e" addr-visiable="true" bank="0"></reg>		
					
			<reg name="CMPC" addr="99" read-addr="99" write-addr="99" value-addr="99" addr-visiable="true" bank="1">
				<bit name="--" offset="0"></bit>
				<bit name="COPOL" offset="1"></bit>
				<bit name="CVEN" offset="2"></bit>	
				<bit name="CPEN" offset="3"></bit>	
				<bit name="CODEB" offset="4"></bit>	
				<bit name="FTCKS" offset="5"></bit>	
				<bit name="CMPIF" offset="6"></bit>
				<bit name="CMPEN" offset="7"></bit>			
			</reg>
			<reg name="CMPM" addr="9a" read-addr="9a" write-addr="9a" value-addr="9a" addr-visiable="true" bank="1">
				<bit name="VRS0" offset="0"></bit>
				<bit name="VRS1" offset="1"></bit>
				<bit name="VRS2" offset="2"></bit>	
				<bit name="VRS3" offset="3"></bit>	
				<bit name="XRVSEL" offset="4"></bit>	
				<bit name="CPINS0" offset="5"></bit>	
				<bit name="CPINS1" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>				
			
			<reg name="INTEN1" addr="9e" read-addr="9e" write-addr="9e" value-addr="9e" addr-visiable="true" bank="1">
				<bit name="TKINTEN" offset="0"></bit>
				<bit name="COMINTEN" offset="1"></bit>	
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>	
				<bit name="--" offset="7"></bit>			
			</reg>			
			
			<reg name="INTFLAG1" addr="9f"  read-addr="9f" write-addr="9f" value-addr="9f" addr-visiable="true" bank="1">
				<bit name="TKINTF" offset="0"></bit>
				<bit name="COMINTF" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>			
		</sfr>		
		<sfr mode="ic_3211">
			<reg name="OPTION" addr="3f4" read-addr="3f4" write-addr="3f4" value-addr="3f4" addr-visiable="false" bank="-1">
				<bit name="PS0" offset="0"></bit>
				<bit name="PS1" offset="1"></bit>
				<bit name="PS2" offset="2"></bit>
				<bit name="PSA" offset="3"></bit>
				<bit name="T0SE" offset="4"></bit>
				<bit name="T0CS" offset="5"></bit>
				<bit name="INTEDG" offset="6"></bit>
				<bit name="INT1DGE" offset="7"></bit>
			</reg>		
		
			<reg name="ACC" addr="ff0" read-addr="ff0" write-addr="ff0" value-addr="ff0" addr-visiable="false" bank="-1"></reg>
			<reg name="INDF" addr="00" read-addr="00" write-addr="00" value-addr="00" addr-visiable="true" bank="0"></reg>
			<reg name="TMR0" addr="01"  read-addr="01" write-addr="01" value-addr="01" addr-visiable="true" bank="0"></reg>
			<reg name="PCL" addr="02" read-addr="02" write-addr="02" value-addr="02" addr-visiable="true" bank="0"></reg>
			<reg name="PCH" addr="8002" read-addr="8002" write-addr="8002" value-addr="8002" addr-visiable="false" bank="-1"></reg>
			
			<reg name="STATUS" addr="03" read-addr="03" write-addr="03" value-addr="03" addr-visiable="true" bank="0">
				<bit name="C" offset="0"></bit>
				<bit name="DC" offset="1"></bit>
				<bit name="Z" offset="2"></bit>
				<bit name="PD" offset="3"></bit>
				<bit name="TO" offset="4"></bit>
				<bit name="RP0" offset="5"></bit>
				<bit name="RP1" offset="6"></bit>
				<bit name="RST" offset="7"></bit>
			</reg>
			
			<reg name="FSR" addr="04"  read-addr="04" write-addr="04" value-addr="04" addr-visiable="true" bank="0"></reg>	
			<reg name="PORTA" addr="05"  read-addr="05" write-addr="05" value-addr="05" addr-visiable="true" bank="0"></reg>
			<reg name="IOSTA" addr="3f5"  read-addr="3f5" write-addr="3f5" value-addr="3f5" addr-visiable="false" bank="-1"></reg>
			<reg name="PORTB" addr="06"  read-addr="06" write-addr="06" value-addr="06" addr-visiable="true" bank="0"></reg>
			<reg name="IOSTB" addr="3f6"  read-addr="3f6" write-addr="3f6" value-addr="3f6" addr-visiable="false" bank="-1"></reg>
			
			<reg name="PCON" addr="08" read-addr="08" write-addr="08" value-addr="08" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="LVDTE" offset="5"></bit>
				<bit name="EIS" offset="6"></bit>
				<bit name="WDTE" offset="7"></bit>
			</reg>			
			
			<reg name="WUCON" addr="09" read-addr="09" write-addr="09" value-addr="09" addr-visiable="true" bank="0"></reg>	
			<reg name="PCHBUF" addr="0a"  read-addr="0a" write-addr="0a" value-addr="0a" addr-visiable="true" bank="0"></reg>
			<reg name="PDCON" addr="0b"  read-addr="0b" write-addr="0b" value-addr="0b" addr-visiable="true" bank="0"></reg>
			<reg name="ODCON" addr="0c"  read-addr="0c" write-addr="0c" value-addr="0c" addr-visiable="true" bank="0"></reg>
			<reg name="PHCON" addr="0d"  read-addr="0d" write-addr="0d" value-addr="0d" addr-visiable="true" bank="0"></reg>

			<reg name="INTEN" addr="0e"  read-addr="0e" write-addr="0e" value-addr="0e" addr-visiable="true" bank="0">
				<bit name="T0IE" offset="0"></bit>
				<bit name="PBIE" offset="1"></bit>
				<bit name="INTIE" offset="2"></bit>	
				<bit name="TC0IE" offset="3"></bit>
				<bit name="TP0IE" offset="4"></bit>	
				<bit name="INT1IE" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="GIE" offset="7"></bit>
			</reg>			
			
			<reg name="INTFLAG" addr="0f"  read-addr="0f" write-addr="0f" value-addr="0f" addr-visiable="true" bank="0">
				<bit name="T0IF" offset="0"></bit>
				<bit name="PBIF" offset="1"></bit>
				<bit name="INTIF" offset="2"></bit>	
				<bit name="TC0IF" offset="3"></bit>	
				<bit name="TP0IF" offset="4"></bit>	
				<bit name="INT1IF" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>
			</reg>			
			
			<reg name="PWM0EN" addr="50" read-addr="50" write-addr="50" value-addr="50" addr-visiable="true" bank="0">
				<bit name="PWM0EN" offset="0"></bit>
				<bit name="PWM0OEN" offset="1"></bit>
				<bit name="PWM01OEN" offset="2"></bit>	
				<bit name="PWM0M" offset="3"></bit>	
				<bit name="PWM1OEN" offset="4"></bit>	
				<bit name="TPSEL8" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="TPEN" offset="7"></bit>
			</reg>		
			
			<reg name="PWM0C" addr="51" read-addr="51" write-addr="51" value-addr="51" addr-visiable="true" bank="0">
				<bit name="CK0" offset="0"></bit>
				<bit name="CK1" offset="1"></bit>
				<bit name="PWM0S0" offset="2"></bit>	
				<bit name="PWM0S1" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="CK2" offset="6"></bit>
				<bit name="CK3" offset="7"></bit>
			</reg>		

			<reg name="PWM0TL" addr="52" read-addr="52" write-addr="52" value-addr="52" addr-visiable="true" bank="0"></reg>		
			<reg name="PWM0TH" addr="53" read-addr="53" write-addr="53" value-addr="53" addr-visiable="true" bank="0"></reg>	
			<reg name="PWM0PL" addr="54" read-addr="54" write-addr="54" value-addr="54" addr-visiable="true" bank="0"></reg>	
			<reg name="PWM0PH" addr="55" read-addr="55" write-addr="55" value-addr="55" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DL" addr="56" read-addr="56" write-addr="56" value-addr="56" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DH" addr="57" read-addr="57" write-addr="57" value-addr="57" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DTL" addr="58" read-addr="58" write-addr="58" value-addr="58" addr-visiable="true" bank="0"></reg>
			<reg name="PWM0DTH" addr="59" read-addr="59" write-addr="59" value-addr="59" addr-visiable="true" bank="0"></reg>
			
			<reg name="PWMPSCON" addr="5b" read-addr="5b" write-addr="5b" value-addr="5b" addr-visiable="true" bank="0">
				<bit name="PWM0S0" offset="0"></bit>
				<bit name="PWM0S1" offset="1"></bit>
				<bit name="PWM01S0" offset="2"></bit>	
				<bit name="PWM01S1" offset="3"></bit>	
				<bit name="PWM1S0" offset="4"></bit>	
				<bit name="PWM1S0" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>
			
			<reg name="PWM1DL" addr="60" read-addr="60" write-addr="60" value-addr="60" addr-visiable="true" bank="0"></reg>
			<reg name="PWM1DH" addr="61" read-addr="61" write-addr="61" value-addr="61" addr-visiable="true" bank="0"></reg>

			<reg name="PBIC0" addr="6d" read-addr="6d" write-addr="6d" value-addr="6d" addr-visiable="true" bank="0"></reg>
			<reg name="PAHCON" addr="6e" read-addr="6e" write-addr="6e" value-addr="6e" addr-visiable="true" bank="0"></reg>
			<reg name="PAIC0" addr="70" read-addr="70" write-addr="70" value-addr="70" addr-visiable="true" bank="0"></reg>
			<reg name="TC0L" addr="71" read-addr="71" write-addr="71" value-addr="71" addr-visiable="true" bank="0"></reg>
			<reg name="TC0M" addr="72" read-addr="72" write-addr="72" value-addr="72" addr-visiable="true" bank="0"></reg>
			<reg name="TC0R" addr="73" read-addr="73" write-addr="73" value-addr="73" addr-visiable="true" bank="0"></reg>
			<reg name="TC0H" addr="74" read-addr="74" write-addr="74" value-addr="74" addr-visiable="true" bank="0"></reg>
			<reg name="TC0D1" addr="75" read-addr="75" write-addr="75" value-addr="75" addr-visiable="true" bank="0"></reg>
			<reg name="TC0D2" addr="76" read-addr="76" write-addr="76" value-addr="76" addr-visiable="true" bank="0"></reg>

			<reg name="PWMCON" addr="77"  read-addr="77" write-addr="77" value-addr="77" addr-visiable="true" bank="0">
				<bit name="PWM1EN" offset="0"></bit>
				<bit name="PWM2EN" offset="1"></bit>
				<bit name="PWM1S" offset="2"></bit>	
				<bit name="PWM2S" offset="3"></bit>	
				<bit name="PWM1XR0" offset="4"></bit>	
				<bit name="PWM1XR1" offset="5"></bit>	
				<bit name="PWM2XR0" offset="6"></bit>
				<bit name="PWM2XR1" offset="7"></bit>		
			</reg>	

			<reg name="PADCON" addr="78" read-addr="78" write-addr="78" value-addr="78" addr-visiable="true" bank="0">
				<bit name="--" offset="0"></bit>
				<bit name="--" offset="1"></bit>
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="PADC4" offset="4"></bit>
				<bit name="PADC5" offset="5"></bit>
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>	
			
			<reg name="OSCM" addr="79" read-addr="79" write-addr="79" value-addr="79" addr-visiable="true" bank="0">
				<bit name="CLKMD" offset="0"></bit>
				<bit name="STPHX" offset="1"></bit>
				<bit name="XTSEL" offset="2"></bit>	
				<bit name="SLCON" offset="3"></bit>	
				<bit name="SLT0C" offset="4"></bit>	
				<bit name="GREENEN" offset="5"></bit>	
				<bit name="WAKEMODE" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	

			<reg name="EECON1" addr="7a" read-addr="7a" write-addr="7a" value-addr="7a" addr-visiable="true" bank="0">
				<bit name="READEE" offset="0"></bit>
				<bit name="PROGEE" offset="1"></bit>
				<bit name="ERASEEE" offset="2"></bit>	
				<bit name="ERSALLEE" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="TIMEE" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>	
	
			<reg name="EEADRL" addr="7c" read-addr="7c" write-addr="7c" value-addr="7c" addr-visiable="true" bank="0"></reg>	
			<reg name="EEDATL" addr="7e" read-addr="7e" write-addr="7e" value-addr="7e" addr-visiable="true" bank="0"></reg>

			<reg name="CMPC" addr="99" read-addr="99" write-addr="99" value-addr="99" addr-visiable="true" bank="1">
				<bit name="--" offset="0"></bit>
				<bit name="COPOL" offset="1"></bit>
				<bit name="CVEN" offset="2"></bit>	
				<bit name="CPEN" offset="3"></bit>	
				<bit name="CODEB" offset="4"></bit>	
				<bit name="FTCKS" offset="5"></bit>	
				<bit name="CMPIF" offset="6"></bit>
				<bit name="CMPEN" offset="7"></bit>			
			</reg>
			<reg name="CMPM" addr="9a" read-addr="9a" write-addr="9a" value-addr="9a" addr-visiable="true" bank="1">
				<bit name="VRS0" offset="0"></bit>
				<bit name="VRS1" offset="1"></bit>
				<bit name="VRS2" offset="2"></bit>	
				<bit name="VRS3" offset="3"></bit>	
				<bit name="XRVSEL" offset="4"></bit>	
				<bit name="CPINS0" offset="5"></bit>	
				<bit name="CPINS1" offset="6"></bit>
				<bit name="--" offset="7"></bit>			
			</reg>				
			
			<reg name="INTEN1" addr="9e" read-addr="9e" write-addr="9e" value-addr="9e" addr-visiable="true" bank="1">
				<bit name="TKINTEN" offset="0"></bit>
				<bit name="COMINTEN" offset="1"></bit>	
				<bit name="--" offset="2"></bit>
				<bit name="--" offset="3"></bit>
				<bit name="--" offset="4"></bit>
				<bit name="--" offset="5"></bit>
				<bit name="--" offset="6"></bit>	
				<bit name="--" offset="7"></bit>			
			</reg>			
			
			<reg name="INTFLAG1" addr="9f"  read-addr="9f" write-addr="9f" value-addr="9f" addr-visiable="true" bank="1">
				<bit name="TKINTF" offset="0"></bit>
				<bit name="COMINTF" offset="1"></bit>
				<bit name="--" offset="2"></bit>	
				<bit name="--" offset="3"></bit>	
				<bit name="--" offset="4"></bit>	
				<bit name="--" offset="5"></bit>	
				<bit name="--" offset="6"></bit>
				<bit name="--" offset="7"></bit>		
			</reg>			
		</sfr>	
	</sfrs>
	<eeprom>
		<size>128</size>
		<addr>0</addr>	
		<update-addr>400</update-addr>
	</eeprom>
	<ccs-config>
		<!--默认擦除EE-->
		<config-item addr="548" bit="no">1</config-item>
	</ccs-config>		
	<insts>
		<inst name="call" value="1000" mask-value="3800"/>
		<inst name="return" value="007c" mask-value="3fff"/>
		<inst name="return" value="007e" mask-value="3fff"/>
		<inst name="return" value="3c00" mask-value="3c00"/>
	</insts>
	<compilers>
		<compiler>	
			<compiler-item type="c" name="cc1" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 2 -ram-bank 10-7f,90-ff -common 07-08  -rst-addr 7ffh -int-addr 08h -tran-exe ptran3.exe   -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
				<action-before-compile>
				</action-before-compile> 
				<action-after-compile >
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="asm" name="ac0" command-path="$(DevEnvDir)\ac0.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -ram-start $(RamStartAddr) -ram-size $(RamSize) -reset-addr $(ResetAddr) -inst-set INST_SET_FM153 -otp-body-size $(OtpBodySize) -debug false -symbol-file true  -listfile true -workdir "$(ProjectDir)" -include-path "$GetFolders(';')" -file "$(EntryFile)" -output "$(OutDir)" -project-name "$(ProjectName)" -config "$(ConfigWord)"</option>
				<action-before-compile>
				</action-before-compile>
				<action-after-compile>
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="c" name="cc1" out-type="lib" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 2 -ram-bank 10-7f,90-ff -common 07-08  -rst-addr 7ffh -int-addr 08h -tran-exe ptran3.exe   -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
			</compiler-item>			
		</compiler>
		<compiler mode="release">	
			<compiler-item type="c" name="cc1" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 2 -ram-bank 10-7f,90-ff -common 07-08  -rst-addr 7ffh -int-addr 08h -tran-exe ptran3.exe   -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
				<action-before-compile>
				</action-before-compile> 
				<action-after-compile >
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
					<action-item  name="StackChecker" command-path="$(DevEnvDir)\StackChecker.exe">"$(ProjectDir)\$(ProjectName).lst" 5</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="asm" name="ac0" command-path="$(DevEnvDir)\ac0.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -ram-start $(RamStartAddr) -ram-size $(RamSize) -reset-addr $(ResetAddr) -inst-set INST_SET_FM153 -otp-body-size $(OtpBodySize) -debug false -symbol-file true  -listfile true -workdir "$(ProjectDir)" -include-path "$GetFolders(';')" -file "$(EntryFile)" -output "$(OutDir)" -project-name "$(ProjectName)" -config "$(ConfigWord)"</option>
				<action-before-compile>
				</action-before-compile>
				<action-after-compile>
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="c" name="cc1" out-type="lib" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 2 -ram-bank 10-7f,90-ff -common 07-08  -rst-addr 7ffh -int-addr 08h -tran-exe ptran3.exe   -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
			</compiler-item>			
		</compiler>
		<compiler mode="compatible">	
			<compiler-item type="c" name="cc1" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 2 -ram-bank 10-7f,90-ff -common 7e-7f  -rst-addr 00h -int-addr 08h -tran-exe ptran3_compatible.exe    -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
				<action-before-compile>
				</action-before-compile> 
				<action-after-compile >
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
					<action-item  name="StackChecker" command-path="$(DevEnvDir)\StackChecker.exe">"$(ProjectDir)\$(ProjectName).lst" 5</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="asm" name="ac0" command-path="$(DevEnvDir)\ac0.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -ram-start $(RamStartAddr) -ram-size $(RamSize) -reset-addr $(ResetAddr) -inst-set INST_SET_FM153 -otp-body-size $(OtpBodySize) -debug false -symbol-file true  -listfile true -workdir "$(ProjectDir)" -include-path "$GetFolders(';')" -file "$(EntryFile)" -output "$(OutDir)" -project-name "$(ProjectName)" -config "$(ConfigWord)"</option>
				<action-before-compile>
				</action-before-compile>
				<action-after-compile>
					<action-item  name="ccs_e" command-path="$(DevEnvDir)\ccs_e.exe">"$(ProjectDir)\$(ProjectName).ccs" -E</action-item>
				</action-after-compile>
			</compiler-item>
			<compiler-item type="c" name="cc1" out-type="lib" command-path="$(DevEnvDir)\cc1.exe">
				<option>-chip $(ChipName) -rom-size $(UserRomSize) -banks 2 -ram-bank 10-7f,90-ff -common 7e-7f  -rst-addr 00h -int-addr 08h -tran-exe ptran3_compatible.exe    -debug false  -prj-name "$(ProjectName)" -work-dir "$(ProjectDir)" -output-dir "$(OutDir)" -picc-path "$(CompilerPath)" -config "$(ConfigWord)" -out-type $(ProjectType) "-I$(DevEnvDir)\include" $AddEndponitStrForeach('"','"',$AddEndponitStrForeach('-I','',$GetFolders('?'),'?','?'),'?',' ') $AddEndponitStrForeach('"','"',$GetFiles('.c;.lpp','?'),'?',' ')</option>
			</compiler-item>			
		</compiler>		
	</compilers>
	<debugers>
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>picc</debuger-c>
			<device type="1" version="0">
				<simulator type="1" version="0" code-first="true" config-item="true" config-item-id="5">
					<pc-addr pcl="02" pch="8002"/>
					<config-word-addr>800</config-word-addr>
					<ram-mode>fpga</ram-mode>
					<sfr-mode>fpga</sfr-mode>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>
		</debuger>
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>picc</debuger-c>
			<device type="3" version="0">
				<simulator type="0" version="0" code-first="false" config-item="false" config-item-id="-1">
					<pc-addr pcl="3f1" pch="3f2" />
					<config-word-addr>800</config-word-addr>
					<ram-mode>ic</ram-mode>
					<sfr-mode>ic</sfr-mode>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>			
		</debuger>		
		<debuger>
			<debuger-asm>ac0</debuger-asm>
			<debuger-c>picc</debuger-c>
			<device type="3" version="0">
				<simulator type="0" version="0" code-first="false" config-item="false" config-item-id="-1">
					<pc-addr pcl="3f1" pch="3f2" />
					<config-word-addr>800</config-word-addr>
					<ram-mode>ic_3211</ram-mode>
					<sfr-mode>ic_3211</sfr-mode>
				</simulator>
			</device>
			<action-before-debug-start></action-before-debug-start>
			<action-after-debug-start></action-after-debug-start>			
		</debuger>	
	</debugers>
	<editor-language>
		<c-lang name="c1-lang"/>
		<asm-lang name="asm1-lang"/>
	</editor-language>	
</chip>