#ifndef __SN8P2267__H
#define __SN8P2267__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	L = 0x80;
sfr	H = 0x81;
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sfr	TC0M = 0x88;
sbit	FTC0ENB = 0x88:7;
sbit	FTC0RATE2 = 0x88:6;
sbit	FTC0RATE1 = 0x88:5;
sbit	FTC0RATE0 = 0x88:4;
sbit	FTC0CKS = 0x88:3;
sbit	FALOAD0 = 0x88:2;
sbit	FTC0OUT = 0x88:1;
sbit	FPWM0OUT = 0x88:0;
sfr	TC0C = 0x89;
sfr	TC0R = 0x8a;
sfr	UDA = 0x90;
sbit	FUDE = 0x90:7;
sbit	FUDA6 = 0x90:6;
sbit	FUDA5 = 0x90:5;
sbit	FUDA4 = 0x90:4;
sbit	FUDA3 = 0x90:3;
sbit	FUDA2 = 0x90:2;
sbit	FUDA1 = 0x90:1;
sbit	FUDA0 = 0x90:0;
sfr	USTATUS = 0x91;
sbit	FCRCERR = 0x91:7;
sbit	FPKTERR = 0x91:6;
sbit	FBUS_RST = 0x91:4;
sbit	FSUSPEND = 0x91:3;
sbit	FEP0SETUP = 0x91:2;
sbit	FEP0IN = 0x91:1;
sbit	FEP0OUT = 0x91:0;
sfr	EP0OUT_CNT = 0x92;
sbit	FUEP0OC4 = 0x92:4;
sbit	FUEP0OC3 = 0x92:3;
sbit	FUEP0OC2 = 0x92:2;
sbit	FUEP0OC1 = 0x92:1;
sbit	FUEP0OC0 = 0x92:0;
sfr	USB_INT_EN = 0x93;
sbit	REG_EN = 0x93:7;
sbit	FDP_PU_EN = 0x93:6;
sbit	FLENGTH4_TOGGLE = 0x93:2;
sbit	FUE2D = 0x93:1;
sbit	FUE1D = 0x93:0;
sfr	EP_ACK = 0x94;
sbit	FEP2_ACK = 0x94:1;
sbit	FEP1_ACK = 0x94:0;
sfr	UE0R = 0x96;
sbit	FUE0E = 0x96:7;
sbit	FUE0M1 = 0x96:6;
sbit	FUE0M0 = 0x96:5;
sbit	FUE0C3 = 0x96:3;
sbit	FUE0C2 = 0x96:2;
sbit	FUE0C1 = 0x96:1;
sbit	FUE0C0 = 0x96:0;
sfr	UE1R = 0x97;
sbit	FUE1E = 0x97:7;
sbit	FUE1M1 = 0x97:6;
sbit	FUE1M0 = 0x97:5;
sbit	FUE1C3 = 0x97:3;
sbit	FUE1C2 = 0x97:2;
sbit	FUE1C1 = 0x97:1;
sbit	FUE1C0 = 0x97:0;
sfr	UE2R = 0x98;
sbit	FUE2E = 0x98:7;
sbit	FUE2M1 = 0x98:6;
sbit	FUE2M0 = 0x98:5;
sbit	FUE2C3 = 0x98:3;
sbit	FUE2C2 = 0x98:2;
sbit	FUE2C1 = 0x98:1;
sbit	FUE2C0 = 0x98:0;
sfr	UDP0_L = 0xa3;
sbit	FUDP07 = 0xa3:7;
sbit	FUDP06 = 0xa3:6;
sbit	FUDP05 = 0xa3:5;
sbit	FUDP04 = 0xa3:4;
sbit	FUDP03 = 0xa3:3;
sbit	FUDP02 = 0xa3:2;
sbit	FUDP01 = 0xa3:1;
sbit	FUDP00 = 0xa3:0;
sfr	UDP0_H = 0xa4;
sbit	FWE0 = 0xa4:7;
sbit	FRE0 = 0xa4:6;
sfr	UDR0_R = 0xa5;
sbit	FUDR0_R7 = 0xa5:7;
sbit	FUDR0_R6 = 0xa5:6;
sbit	FUDR0_R5 = 0xa5:5;
sbit	FUDR0_R4 = 0xa5:4;
sbit	FUDR0_R3 = 0xa5:3;
sbit	FUDR0_R2 = 0xa5:2;
sbit	FUDR0_R1 = 0xa5:1;
sbit	FUDR0_R0 = 0xa5:0;
sfr	UDR0_W = 0xa6;
sbit	FUDR0_W7 = 0xa6:7;
sbit	FUDR0_W6 = 0xa6:6;
sbit	FUDR0_W5 = 0xa6:5;
sbit	FUDR0_W4 = 0xa6:4;
sbit	FUDR0_W3 = 0xa6:3;
sbit	FUDR0_W2 = 0xa6:2;
sbit	FUDR0_W1 = 0xa6:1;
sbit	FUDR0_W0 = 0xa6:0;
sfr	UPID = 0xab;
sbit	FUBDE = 0xab:2;
sbit	FDDP = 0xab:1;
sbit	FDDN = 0xab:0;
sfr	UTOGGLE = 0xac;
sbit	FEP2_DATA01 = 0xac:1;
sbit	FEP1_DATA01 = 0xac:0;
sfr	PS2M = 0xaf;
sbit	FPS2ENB = 0xaf:7;
sbit	FSDA = 0xaf:3;
sbit	FSCK = 0xaf:2;
sbit	FSDAM = 0xaf:1;
sbit	FSCKM = 0xaf:0;
sfr	IHRCU = 0xb0;
sbit	FIHRCU5 = 0xb0:5;
sbit	FIHRCU4 = 0xb0:4;
sbit	FIHRCU3 = 0xb0:3;
sbit	FIHRCU2 = 0xb0:2;
sbit	FIHRCU1 = 0xb0:1;
sbit	FEP0_IN_STALL = 0xb0:0;
sfr	IHRCL = 0xb1;
sbit	FIHRCL5 = 0xb1:5;
sbit	FIHRCL4 = 0xb1:4;
sbit	FIHRCL3 = 0xb1:3;
sbit	FIHRCL2 = 0xb1:2;
sbit	FIHRCL1 = 0xb1:1;
sbit	FEP0_OUT_STALL = 0xb1:0;
sfr	IHRC_VALUE = 0xb3;
sfr	P0M = 0xb8;
sbit	FP07M = 0xb8:7;
sbit	FP06M = 0xb8:6;
sbit	FP05M = 0xb8:5;
sbit	FP04M = 0xb8:4;
sbit	FP03M = 0xb8:3;
sbit	FP02M = 0xb8:2;
sbit	FP01M = 0xb8:1;
sbit	FP00M = 0xb8:0;
sfr	PEDGE = 0xbf;
sbit	FP00G1 = 0xbf:1;
sbit	FP00G0 = 0xbf:0;
sfr	P1M = 0xc1;
sbit	FP17M = 0xc1:7;
sbit	FP16M = 0xc1:6;
sbit	FP15M = 0xc1:5;
sbit	FP14M = 0xc1:4;
sbit	FP13M = 0xc1:3;
sbit	FP12M = 0xc1:2;
sbit	FP11M = 0xc1:1;
sbit	FP10M = 0xc1:0;
sfr	P2M = 0xc2;
sbit	FP27M = 0xc2:7;
sbit	FP26M = 0xc2:6;
sbit	FP25M = 0xc2:5;
sbit	FP24M = 0xc2:4;
sbit	FP23M = 0xc2:3;
sbit	FP22M = 0xc2:2;
sbit	FP21M = 0xc2:1;
sbit	FP20M = 0xc2:0;
sfr	P3M = 0xc3;
sbit	FP36M = 0xc3:6;
sbit	FP35M = 0xc3:5;
sbit	FP34M = 0xc3:4;
sbit	FP33M = 0xc3:3;
sbit	FP32M = 0xc3:2;
sbit	FP31M = 0xc3:1;
sbit	FP30M = 0xc3:0;
sfr	P5M = 0xc5;
sbit	FP55M = 0xc5:5;
sbit	FP54M = 0xc5:4;
sbit	FP53M = 0xc5:3;
sbit	FP52M = 0xc5:2;
sbit	FP51M = 0xc5:1;
sbit	FP50M = 0xc5:0;
sfr	INTRQ = 0xc8;
sbit	FUSBIRQ = 0xc8:6;
sbit	FTC0IRQ = 0xc8:5;
sbit	FT0IRQ = 0xc8:4;
sbit	FWAKEIRQ = 0xc8:2;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN = 0xc9;
sbit	FUSBIEN = 0xc9:6;
sbit	FTC0IEN = 0xc9:5;
sbit	FT0IEN = 0xc9:4;
sbit	FWAKEIEN = 0xc9:2;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	PCL = 0xce;
sfr	PCH = 0xcf;
sfr	P0 = 0xd0;
sbit	FP07 = 0xd0:7;
sbit	FP06 = 0xd0:6;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP17 = 0xd1:7;
sbit	FP16 = 0xd1:6;
sbit	FP15 = 0xd1:5;
sbit	FP14 = 0xd1:4;
sbit	FP13 = 0xd1:3;
sbit	FP12 = 0xd1:2;
sbit	FP11 = 0xd1:1;
sbit	FP10 = 0xd1:0;
sfr	P2 = 0xd2;
sbit	FP27 = 0xd2:7;
sbit	FP26 = 0xd2:6;
sbit	FP25 = 0xd2:5;
sbit	FP24 = 0xd2:4;
sbit	FP23 = 0xd2:3;
sbit	FP22 = 0xd2:2;
sbit	FP21 = 0xd2:1;
sbit	FP20 = 0xd2:0;
sfr	P3 = 0xd3;
sbit	FP37 = 0xd3:7;
sbit	FP36 = 0xd3:6;
sbit	FP35 = 0xd3:5;
sbit	FP34 = 0xd3:4;
sbit	FP33 = 0xd3:3;
sbit	FP32 = 0xd3:2;
sbit	FP31 = 0xd3:1;
sbit	FP30 = 0xd3:0;
sfr	P5 = 0xd5;
sbit	FP55 = 0xd5:5;
sbit	FP54 = 0xd5:4;
sbit	FP53 = 0xd5:3;
sbit	FP52 = 0xd5:2;
sbit	FP51 = 0xd5:1;
sbit	FP50 = 0xd5:0;
sfr	T0M = 0xd8;
sbit	FT0ENB = 0xd8:7;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE0 = 0xd8:4;
sfr	T0C = 0xd9;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sfr	P1UR = 0xe1;
sfr	P2UR = 0xe2;
sfr	P3UR = 0xe3;
sfr	P5UR = 0xe5;
sfr	_HL = 0xe6;
sfr	_YZ = 0xe7;
sfr	STK7L = 0xf0;
sfr	STK7H = 0xf1;
sfr	STK6L = 0xf2;
sfr	STK6H = 0xf3;
sfr	STK5L = 0xf4;
sfr	STK5H = 0xf5;
sfr	STK4L = 0xf6;
sfr	STK4H = 0xf7;
sfr	STK3L = 0xf8;
sfr	STK3H = 0xf9;
sfr	STK2L = 0xfa;
sfr	STK2H = 0xfb;
sfr	STK1L = 0xfc;
sfr	STK1H = 0xfd;
sfr	STK0L = 0xfe;
sfr	STK0H = 0xff;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#endif
