/******************************************************************
;UPDATA DATE:2019/12/17
;USER:Cuiyn
;HS23P6621
******************************************************************/
#ifndef _DEF_H
#define _DEF_H

/////////////////////////////////////////
struct bitRegister{
    unsigned bit0:1;
    unsigned bit1:1;
    unsigned bit2:1;
    unsigned bit3:1;
    unsigned bit4:1;
    unsigned bit5:1;
    unsigned bit6:1;
    unsigned bit7:1;
};
//////////////////////////////////////////
typedef unsigned char   BYTE;
typedef unsigned long   WORD;
typedef double          DWORD;
////////////////////////////////////////////
//sfr define for HS23P6610
////////////////////////////////////////////
//=================================================
//¼Ä´æÆ÷ºê¶¨Òå 
//=================================================
//0X80~0X8F
sfr     L       =   0x80;
sfr     H       =   0x81;
sfr     R       =   0x82;
sfr     Z       =   0x83;

sfr     Y       =   0x84;
sfr     PFLAG   =   0x86;
    sbit    FZ      =   0x86:0;
    sbit    FDC     =   0x86:1;
    sbit    FC      =   0x86:2;

    sbit    FLVD24  =   0x86:4;
    sbit    FLVD36  =   0x86:5;
    sbit    FNPD    =   0x86:6;
    sbit    FNT0    =   0x86:7;
    
sfr     RBANK   =   0x87;
    sbit    FRBANKS0=   0x87:0;

//=================================================
//0XA0~0XAF
sfr     LDOUT   =   0xA0;   //6625L
    sbit    FP53ANA     =   0xA0:0;
    sbit    FP04ANA     =   0xA0:6;
    sbit    FLDOUTEN    =   0xA0:7;
    
sfr     AINET3  =   0xA1;   //6625L
    sbit    FAINET30        =   0xA1:0;
    sbit    FAINET31        =   0xA1:1;
    sbit    FAINET32        =   0xA1:2; 
    
sfr     ADCLP   =   0xA2;   //6625L
    sbit    FADCLP0     =   0xA2:0;
    sbit    FADCLP1     =   0xA2:1;

    
    
sfr     ADCCN3  =   0xA3;   //6621+
    sbit    FRDBH       =   0xA3:1;


sfr     ADCCN1  =   0xA4;
    sbit    FADGN0  =   0xA4:0;
    sbit    FADGN1  =   0xA4:1;
    sbit    FADGN2  =   0xA4:2; 
    sbit    FENACM  =   0xA4:3;
    
    sbit    FENTEMP =   0xA4:4;
    sbit    FENCHP  =   0xA4:5;
    sbit    FADRST  =   0xA4:6;
    sbit    FENADC  =   0xA4:7;
    
sfr     ADCCN2  =   0xA5;
    sbit    FDCSET0 =   0xA5:0;
    sbit    FDCSET1 =   0xA5:1;
    sbit    FDCSET2 =   0xA5:2; 
    sbit    FVREGN  =   0xA5:3;
    
    sbit    FOSR0   =   0xA5:4;
    sbit    FOSR1   =   0xA5:5;
    sbit    FOSR2   =   0xA5:6;
    sbit    FOSR3   =   0xA5:7;

sfr     ADRES_H =   0xA6;
sfr     ADRESH =   0xA6;

sfr     AINET1  =   0xA7;
    sbit    FINIS   =   0xA7:1;
    sbit    FINL0   =   0xA7:2; 
    sbit    FINL1   =   0xA7:3; 
    sbit    FINL2   =   0xA7:4;
    sbit    FINH0   =   0xA7:5;
    sbit    FINH1   =   0xA7:6;
    sbit    FINH2   =   0xA7:7;

sfr     AINET2  =   0xA8;
    sbit    FLVHSEN =   0xA8:0;
    
    sbit    FVRL0   =   0xA8:1;
    sbit    FVRL1   =   0xA8:2; 
    
    sbit    FINX0   =   0xA8:3; 
    sbit    FINX1   =   0xA8:4;
    
    sbit    FVRH0   =   0xA8:5;
    sbit    FVRH1   =   0xA8:6;
    
    sbit    FADPCON51   =   0xA8:7;
    
sfr     ADRES_M =   0xA9;
sfr     ADRESM =   0xA9;
sfr     ADRES_L =   0xAA;
sfr     ADRESL =   0xAA;

sfr     ADCPCON=   0xAB;

sbit    FP40AD = 0xAB:0;
sbit    FP41AD = 0xAB:1;
sbit    FP02AD = 0xAB:2;
sbit    FP03AD = 0xAB:3;
sbit    FP04AD = 0xAB:4;
sbit    FP05AD = 0xAB:5;
sbit    FP06AD = 0xAB:6;
sbit    FP07AD = 0xAB:7;

sfr     PWRCN   =   0xAC;
    sbit    FDri_CON2   =   0xAC:0;
    sbit    FDri_CON3   =   0xAC:1;
    sbit    FDri_CON4   =   0xAC:2; 
    
    sbit    FVDDAX0     =   0xAC:4;
    sbit    FVDDAX1     =   0xAC:5;
    
    sbit    FLDOEN      =   0xAC:7;
    

sfr     ADCCK   =   0xAE;   //6621+
    sbit    FADCCKS =   0xAE:0; 
    
    sbit    FADCS1  =   0xAE:4;
    sbit    FADCS2  =   0xAE:5;
    
    sbit    FDHS0   =   0xAE:6;
    sbit    FDHS1   =   0xAE:7;

//=================================================
//0XB0~0XBF
sfr     P0W     =   0xB0;
sfr     P4W     =   0xB1;
sfr     P5W     =   0xB2;

sfr     I2CCON1 =   0xB3;
    sbit    FRXAK   =   0xB3:0;

sfr     I2CCON  =   0xB4;
    sbit    FI2CEN  =   0xB4:0;
    sbit    FI2CPU  =   0xB4:1;
    sbit    FCKP    =   0xB4:2; 
    sbit    FTXAK   =   0xB4:3;
    
    sbit    FSRW    =   0xB4:4;
    sbit    FHBB    =   0xB4:5;
    sbit    FHAAS   =   0xB4:6;
    sbit    FHCF    =   0xB4:7;
    
sfr     I2CADD  =   0xB5;
sfr     I2CBUF  =   0xB6;

sfr     I2CTOV  =   0xB7;   //6621+
    sbit    FTOS0   =   0xB7:0;
    sbit    FTOS1   =   0xB7:1;
    sbit    FTOS2   =   0xB7:2;
    sbit    FTOVF   =   0xB7:6;
    sbit    FTOVEN  =   0xB7:7;

sfr     P0M     =   0xB8;

sfr     P4PD    =   0xBC;   //6621+
    sbit    FP40PD0 = 0xBC:0;
    sbit    FP40PD1 = 0xBC:1;
    sbit    FP41PD0 = 0xBC:2;
    sbit    FP41PD1 = 0xBC:3;
    sbit    FP40PDEN    = 0xBC:4;
    sbit    FP41PDEN    = 0xBC:5;

sfr     PEDGE   =   0xBF;
    sbit    FP00G0  =   0xBF:3;
    sbit    FP00G1  =   0xBF:4;
    
    sbit    FINTSEL0    = 0xBF:5;
    sbit    FINTSEL1    = 0xBF:6;
    sbit    FINTSEL2    = 0xBF:7;

//=================================================
//0XC0~0XCF
sfr     P4M     =   0xC4;
sfr     P5M     =   0xC5;

sfr     INTRQ   =   0xC8;
    sbit    FINT0IF =   0xC8:0;

    sbit    FI2CIF  =   0xC8:2;
    
    sbit    FTC0IF  =   0xC8:5;
    sbit    FTC1IF  =   0xC8:6;
    sbit    FADCIF  =   0xC8:7;
    sbit    FADCIRQ =   0xC8:7;
sfr     INTEN   =   0xC9;
    sbit    FP00IEN =   0xC9:0;

    sbit    FI2CIE  =   0xC9:2;
    
    sbit    FTC0IEN =   0xC9:5;
    sbit    FTC1IEN =   0xC9:6;
    sbit    FADCIEN =   0xC9:7;

sfr     OSCM    =   0xCA;
    sbit    FLECS32K    = 0xca:7;

    sbit    FCPUM1      = 0xca:4;   
    sbit    FCPUM0      = 0xca:3;
    sbit    FCLKMD      = 0xca:2;
    sbit    FSTPHX      = 0xca:1;
    

sfr     WDTC    =   0xCB;
    sbit    FWDTS0  = 0XCB:0;
    sbit    FWDTS1  = 0XCB:1;
    sbit    FWDTS2  = 0XCB:2;
    
    sbit    FLFS0   = 0XCB:4;
    sbit    FLFS1   = 0XCB:5;
    sbit    FLFS2   = 0XCB:6;
    
    sbit    FWDTEN  = 0XCB:7;


sfr     WDTR    =   0xCC;
sfr     TC0R    =   0xCD;
sfr     PCL     =   0xCE;
sfr     PCH     =   0xCF;

//=================================================
//0XD0~0XDF
sfr     P0      =   0xD0;
    sbit    FP00 = 0xd0:0;
    sbit    FP01 = 0xd0:1;
    sbit    FP02 = 0xd0:2;
    sbit    FP03 = 0xd0:3;
    
    sbit    FP04 = 0xd0:4;
    sbit    FP05 = 0xd0:5;
    sbit    FP06 = 0xd0:6;
    sbit    FP07 = 0xd0:7;
    
sfr     P4      =   0xD4;
    sbit    FP40 = 0xd4:0;
    sbit    FP41 = 0xd4:1;
    
sfr     P5      =   0xD5;
    sbit    FP51 = 0xd5:1;
    sbit    FP52 = 0xd5:2;
    sbit    FP53 = 0xd5:3;
    sbit    FP54 = 0xd5:4;

sfr     T0M     =   0xD8;
    sbit    FTC1GN = 0xd8:0;
    sbit    FTC0GN = 0xd8:1;
    sbit    FTC0X8 = 0xd8:2;
    sbit    FTC1X8 = 0xd8:3;
    
    sbit    FTC0S16 = 0xd8:4;
    sbit    FTC1S16 = 0xd8:5;
    sbit    FLRCEN = 0xd8:6;

sfr     PWMCON  =   0xD9;
    sbit    FPWM1EN     = 0xd9:0;
    sbit    FPWM2EN     = 0xd9:1;
    sbit    FPWM1_PSEL  = 0xd9:2;
    
    sbit    FPWM1_OSEL  = 0xd9:4;
    sbit    FPWM2_OSEL  = 0xd9:5;
    sbit    FPWM0_OSEL  = 0xd9:6;

sfr     TC0M    =   0xDA;
    sbit    FTC0R       = 0xda:7;
    sbit    FTC0PS2     = 0xda:6;
    sbit    FTC0PS1     = 0xda:5;
    sbit    FTC0PS0     = 0xda:4;
    
    sbit    FTC0CKS     = 0xda:3;
    sbit    FALOAD0     = 0xda:2;
    sbit    FTC0OUT     = 0xda:1;
    sbit    FPWM0OUT    = 0xda:0;
    
sfr     TC0C    =   0xDB;

sfr     TC1M    =   0xDC;
    sbit    FTC1R       = 0xdc:7;
    sbit    FTC1PS2     = 0xdc:6;
    sbit    FTC1PS1     = 0xdc:5;
    sbit    FTC1PS0     = 0xdc:4;
    
    sbit    FTC1CKS     = 0xdc:3;
    sbit    FALOAD1     = 0xdc:2;
    sbit    FTC1OUT     = 0xdc:1;
    sbit    FPWM1OUT    = 0xdc:0;
    
sfr     TC1C    =   0xDD;
sfr     TC1R    =   0xDE;

sfr     STKP    =   0xDF;
    sbit    FGIE    = 0xdf:7;
    sbit    FSTKPB2 = 0xdf:2;
    sbit    FSTKPB1 = 0xdf:1;
    sbit    FSTKPB0 = 0xdf:0;

//=================================================
//0XE0~0XEF
sfr     P0UR    =   0xE0;
sfr     P4UR    =   0xE4;
sfr     P5UR    =   0xE5;
sfr     _YZ     =   0xE7;

sfr     PWM2CON = 0xE8;
    sbit    FPWM2C0 = 0xE8:0;
    sbit    FPWM2C1 = 0xE8:1;
    sbit    FPWM2C2 = 0xE8:2;

sfr     TC0R0   =   0xE9;
sfr     TC0R1   =   0xEA;
sfr     TC0R2   =   0xEB;

//=================================================
//0XF0~0XFF
sfr     STK7L   =   0xF0;
sfr     STK7H   =   0xF1;
sfr     STK6L   =   0xF2;
sfr     STK6H   =   0xF3;
sfr     STK5L   =   0xF4;
sfr     STK5H   =   0xF5;
sfr     STK4L   =   0xF6;
sfr     STK4H   =   0xF7;

sfr     STK3L   =   0xF8;
sfr     STK3H   =   0xF9;
sfr     STK2L   =   0xFA;
sfr     STK2H   =   0xFB;
sfr     STK1L   =   0xFC;
sfr     STK1H   =   0xFD;
sfr     STK0L   =   0xFE;
sfr     STK0H   =   0xFF;

//=================================================
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}


/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
#define HIBYTE(wval)        *(((BYTE*)(&wval))+1)
#define LWBYTE(wval)        *(((BYTE*)(&wval))+0)

#define HIWORD(wval)        *(((WORD*)(&wval))+1)
#define LWWORD(wval)        *(((WORD*)(&wval))+0)


#endif
