#ifndef __SN8F2283__H
#define __SN8F2283__H

void _ClearWatchDogTimer(void);
void _ClrRAM(void);

#define NOP(X)  	__asm{	_NOP X }
#define LOG(X)  	__asm{	LOG CNameToAsmLabel(X) }
sfr	R = 0x82;
sfr	Z = 0x83;
sfr	Y = 0x84;
sfr	PFLAG = 0x86;
sbit	FZ = 0x86:0;
sbit	FDC = 0x86:1;
sbit	FC = 0x86:2;
sbit	FNPD = 0x86:6;
sbit	FNT0 = 0x86:7;
sfr	RBANK = 0x87;
sbit	FRBNKS0 = 0x87:0;
sbit	FRBNKS1 = 0x87:1;
sfr	TC0M = 0x88;
sbit	FTC0ENB = 0x88:7;
sbit	FTC0RATE2 = 0x88:6;
sbit	FTC0RATE1 = 0x88:5;
sbit	FTC0RATE0 = 0x88:4;
sbit	FTC0CKS = 0x88:3;
sbit	FALOAD0 = 0x88:2;
sbit	FTC0OUT = 0x88:1;
sbit	FPWM0OUT = 0x88:0;
sfr	TC0C = 0x89;
sfr	TC0R = 0x8a;
sfr	TC1M = 0x8b;
sbit	FTC1ENB = 0x8b:7;
sbit	FTC1RATE2 = 0x8b:6;
sbit	FTC1RATE1 = 0x8b:5;
sbit	FTC1RATE0 = 0x8b:4;
sbit	FTC1CKS = 0x8b:3;
sbit	FALOAD1 = 0x8b:2;
sbit	FTC1OUT = 0x8b:1;
sbit	FPWM1OUT = 0x8b:0;
sfr	TC1C = 0x8c;
sfr	TC1R = 0x8d;
sfr	TC2M = 0x8e;
sbit	FTC2ENB = 0x8e:7;
sbit	FTC2RATE2 = 0x8e:6;
sbit	FTC2RATE1 = 0x8e:5;
sbit	FTC2RATE0 = 0x8e:4;
sbit	FTC2CKS = 0x8e:3;
sbit	FALOAD2 = 0x8e:2;
sbit	FTC2OUT = 0x8e:1;
sbit	FPWM2OUT = 0x8e:0;
sfr	TC2C = 0x8f;
sfr	TC2R = 0x90;
sfr	UDA = 0x91;
sbit	FUDE = 0x91:7;
sbit	FUDA6 = 0x91:6;
sbit	FUDA5 = 0x91:5;
sbit	FUDA4 = 0x91:4;
sbit	FUDA3 = 0x91:3;
sbit	FUDA2 = 0x91:2;
sbit	FUDA1 = 0x91:1;
sbit	FUDA0 = 0x91:0;
sfr	USTATUS = 0x92;
sbit	FCRCERR = 0x92:7;
sbit	FPKTERR = 0x92:6;
sbit	FSOF = 0x92:5;
sbit	FBUS_RST = 0x92:4;
sbit	FSUSPEND = 0x92:3;
sbit	FEP0SETUP = 0x92:2;
sbit	FEP0IN = 0x92:1;
sbit	FEP0OUT = 0x92:0;
sfr	EP0OUT_CNT = 0x93;
sbit	FUEP0OC4 = 0x93:4;
sbit	FUEP0OC3 = 0x93:3;
sbit	FUEP0OC2 = 0x93:2;
sbit	FUEP0OC1 = 0x93:1;
sbit	FUEP0OC0 = 0x93:0;
sfr	USB_INT_EN = 0x94;
sbit	FREG_EN = 0x94:7;
sbit	FDP_PU_EN = 0x94:6;
sbit	FSOF_INT_EN = 0x94:5;
sbit	FEP4NAK_INT_EN = 0x94:3;
sbit	FEP3NAK_INT_EN = 0x94:2;
sbit	FEP2NAK_INT_EN = 0x94:1;
sbit	FEP1NAK_INT_EN = 0x94:0;
sfr	EP_ACK = 0x95;
sbit	FEP4_ACK = 0x95:3;
sbit	FEP3_ACK = 0x95:2;
sbit	FEP2_ACK = 0x95:1;
sbit	FEP1_ACK = 0x95:0;
sfr	EP_NAK = 0x96;
sbit	FEP4_NAK = 0x96:3;
sbit	FEP3_NAK = 0x96:2;
sbit	FEP2_NAK = 0x96:1;
sbit	FEP1_NAK = 0x96:0;
sfr	UE0R = 0x97;
sbit	FUE0M1 = 0x97:6;
sbit	FUE0M0 = 0x97:5;
sbit	FUE0C3 = 0x97:3;
sbit	FUE0C2 = 0x97:2;
sbit	FUE0C1 = 0x97:1;
sbit	FUE0C0 = 0x97:0;
sfr	UE1R = 0x98;
sbit	FUE1E = 0x98:7;
sbit	FUE1M1 = 0x98:6;
sbit	FUE1M0 = 0x98:5;
sfr	UE1R_C = 0x99;
sbit	FUE1C6 = 0x99:6;
sbit	FUE1C5 = 0x99:5;
sbit	FUE1C4 = 0x99:4;
sbit	FUE1C3 = 0x99:3;
sbit	FUE1C2 = 0x99:2;
sbit	FUE1C1 = 0x99:1;
sbit	FUE1C0 = 0x99:0;
sfr	UE2R = 0x9a;
sbit	FUE2E = 0x9a:7;
sbit	FUE2M1 = 0x9a:6;
sbit	FUE2M0 = 0x9a:5;
sfr	UE2R_C = 0x9b;
sbit	FUE2C6 = 0x9b:6;
sbit	FUE2C5 = 0x9b:5;
sbit	FUE2C4 = 0x9b:4;
sbit	FUE2C3 = 0x9b:3;
sbit	FUE2C2 = 0x9b:2;
sbit	FUE2C1 = 0x9b:1;
sbit	FUE2C0 = 0x9b:0;
sfr	UE3R = 0x9c;
sbit	FUE3E = 0x9c:7;
sbit	FUE3M1 = 0x9c:6;
sbit	FUE3M0 = 0x9c:5;
sfr	UE3R_C = 0x9d;
sbit	FUE3C6 = 0x9d:6;
sbit	FUE3C5 = 0x9d:5;
sbit	FUE3C4 = 0x9d:4;
sbit	FUE3C3 = 0x9d:3;
sbit	FUE3C2 = 0x9d:2;
sbit	FUE3C1 = 0x9d:1;
sbit	FUE3C0 = 0x9d:0;
sfr	UE4R = 0x9e;
sbit	FUE4E = 0x9e:7;
sbit	FUE4M1 = 0x9e:6;
sbit	FUE4M0 = 0x9e:5;
sfr	UE4R_C = 0x9f;
sbit	FUE4C6 = 0x9f:6;
sbit	FUE4C5 = 0x9f:5;
sbit	FUE4C4 = 0x9f:4;
sbit	FUE4C3 = 0x9f:3;
sbit	FUE4C2 = 0x9f:2;
sbit	FUE4C1 = 0x9f:1;
sbit	FUE4C0 = 0x9f:0;
sfr	EP2FIFO_ADDR = 0xa0;
sbit	FEP2FIFO7 = 0xa0:7;
sbit	FEP2FIFO6 = 0xa0:6;
sbit	FEP2FIFO5 = 0xa0:5;
sbit	FEP2FIFO4 = 0xa0:4;
sbit	FEP2FIFO3 = 0xa0:3;
sbit	FEP2FIFO2 = 0xa0:2;
sbit	FEP2FIFO1 = 0xa0:1;
sbit	FEP2FIFO0 = 0xa0:0;
sfr	EP3FIFO_ADDR = 0xa1;
sbit	FEP3FIFO7 = 0xa1:7;
sbit	FEP3FIFO6 = 0xa1:6;
sbit	FEP3FIFO5 = 0xa1:5;
sbit	FEP3FIFO4 = 0xa1:4;
sbit	FEP3FIFO3 = 0xa1:3;
sbit	FEP3FIFO2 = 0xa1:2;
sbit	FEP3FIFO1 = 0xa1:1;
sbit	FEP3FIFO0 = 0xa1:0;
sfr	EP4FIFO_ADDR = 0xa2;
sbit	FEP4FIFO7 = 0xa2:7;
sbit	FEP4FIFO6 = 0xa2:6;
sbit	FEP4FIFO5 = 0xa2:5;
sbit	FEP4FIFO4 = 0xa2:4;
sbit	FEP4FIFO3 = 0xa2:3;
sbit	FEP4FIFO2 = 0xa2:2;
sbit	FEP4FIFO1 = 0xa2:1;
sbit	FEP4FIFO0 = 0xa2:0;
sfr	UDP0 = 0xa3;
sbit	FUDP07 = 0xa3:7;
sbit	FUDP06 = 0xa3:6;
sbit	FUDP05 = 0xa3:5;
sbit	FUDP04 = 0xa3:4;
sbit	FUDP03 = 0xa3:3;
sbit	FUDP02 = 0xa3:2;
sbit	FUDP01 = 0xa3:1;
sbit	FUDP00 = 0xa3:0;
sfr	UDR0_R = 0xa5;
sbit	FUDR0_R7 = 0xa5:7;
sbit	FUDR0_R6 = 0xa5:6;
sbit	FUDR0_R5 = 0xa5:5;
sbit	FUDR0_R4 = 0xa5:4;
sbit	FUDR0_R3 = 0xa5:3;
sbit	FUDR0_R2 = 0xa5:2;
sbit	FUDR0_R1 = 0xa5:1;
sbit	FUDR0_R0 = 0xa5:0;
sfr	UDR0_W = 0xa6;
sbit	FUDR0_W7 = 0xa6:7;
sbit	FUDR0_W6 = 0xa6:6;
sbit	FUDR0_W5 = 0xa6:5;
sbit	FUDR0_W4 = 0xa6:4;
sbit	FUDR0_W3 = 0xa6:3;
sbit	FUDR0_W2 = 0xa6:2;
sbit	FUDR0_W1 = 0xa6:1;
sbit	FUDR0_W0 = 0xa6:0;
sfr	UPID = 0xa7;
sbit	FUBDE = 0xa7:2;
sbit	FDDP = 0xa7:1;
sbit	FDDN = 0xa7:0;
sfr	UTOGGLE = 0xa8;
sbit	FEP4_DATA01 = 0xa8:3;
sbit	FEP3_DATA01 = 0xa8:2;
sbit	FEP2_DATA01 = 0xa8:1;
sbit	FEP1_DATA01 = 0xa8:0;
sfr	URTX = 0xa9;
sbit	FUCLKS = 0xa9:7;
sbit	FUTXEN = 0xa9:4;
sbit	FUTXPEN = 0xa9:3;
sbit	FUTXPS = 0xa9:2;
sbit	FUTXM = 0xa9:1;
sfr	URRX = 0xaa;
sbit	FURXEN = 0xaa:7;
sbit	FURXS1 = 0xaa:6;
sbit	FURXS0 = 0xaa:5;
sbit	FURXPEN = 0xaa:4;
sbit	FURXPS = 0xaa:3;
sbit	FURXPC = 0xaa:2;
sbit	FURXM = 0xaa:1;
sfr	URBRC = 0xab;
sbit	FUDIV4 = 0xab:7;
sbit	FUDIV3 = 0xab:6;
sbit	FUDIV2 = 0xab:5;
sbit	FUDIV1 = 0xab:4;
sbit	FUDIV0 = 0xab:3;
sbit	FUPCS2 = 0xab:2;
sbit	FUPCS1 = 0xab:1;
sbit	FUPCS0 = 0xab:0;
sfr	URTXD1 = 0xac;
sbit	FUTXD17 = 0xac:7;
sbit	FUTXD16 = 0xac:6;
sbit	FUTXD15 = 0xac:5;
sbit	FUTXD14 = 0xac:4;
sbit	FUTXD13 = 0xac:3;
sbit	FUTXD12 = 0xac:2;
sbit	FUTXD11 = 0xac:1;
sbit	FUTXD10 = 0xac:0;
sfr	URTXD2 = 0xad;
sbit	FUTXD27 = 0xad:7;
sbit	FUTXD26 = 0xad:6;
sbit	FUTXD25 = 0xad:5;
sbit	FUTXD24 = 0xad:4;
sbit	FUTXD23 = 0xad:3;
sbit	FUTXD22 = 0xad:2;
sbit	FUTXD21 = 0xad:1;
sbit	FUTXD20 = 0xad:0;
sfr	URRXD1 = 0xae;
sfr	URRXD2 = 0xaf;
sfr	SIOM = 0xb0;
sbit	FSENB = 0xb0:7;
sbit	FSTART = 0xb0:6;
sbit	FSRATE1 = 0xb0:5;
sbit	FSRATE0 = 0xb0:4;
sbit	FMLSB = 0xb0:3;
sbit	FSCKMD = 0xb0:2;
sbit	FCPOL = 0xb0:1;
sbit	FCPHA = 0xb0:0;
sfr	SIOR = 0xb1;
sfr	SIOB = 0xb2;
sbit	FSIOB7 = 0xb2:7;
sbit	FSIOB6 = 0xb2:6;
sbit	FSIOB5 = 0xb2:5;
sbit	FSIOB4 = 0xb2:4;
sbit	FSIOB3 = 0xb2:3;
sbit	FSIOB2 = 0xb2:2;
sbit	FSIOB1 = 0xb2:1;
sbit	FSIOB0 = 0xb2:0;
sfr	P0M = 0xb5;
sbit	FP07M = 0xb5:7;
sbit	FP06M = 0xb5:6;
sbit	FP05M = 0xb5:5;
sbit	FP04M = 0xb5:4;
sbit	FP03M = 0xb5:3;
sbit	FP02M = 0xb5:2;
sbit	FP01M = 0xb5:1;
sbit	FP00M = 0xb5:0;
sfr	ADM = 0xb6;
sbit	FADENB = 0xb6:7;
sbit	FADS = 0xb6:6;
sbit	FEOC = 0xb6:5;
sbit	FGCHS = 0xb6:4;
sbit	FCHS3 = 0xb6:3;
sbit	FCHS2 = 0xb6:2;
sbit	FCHS1 = 0xb6:1;
sbit	FCHS0 = 0xb6:0;
sfr	ADB = 0xb7;
sbit	FADB11 = 0xb7:7;
sbit	FADB10 = 0xb7:6;
sbit	FADB9 = 0xb7:5;
sbit	FADB8 = 0xb7:4;
sbit	FADB7 = 0xb7:3;
sbit	FADB6 = 0xb7:2;
sbit	FADB5 = 0xb7:1;
sbit	FADB4 = 0xb7:0;
sfr	ADR = 0xb8;
sbit	FADCKS2 = 0xb8:7;
sbit	FADCKS1 = 0xb8:6;
sbit	FADCKS0 = 0xb8:5;
sbit	FADLEN = 0xb8:4;
sbit	FADB3 = 0xb8:3;
sbit	FADB2 = 0xb8:2;
sbit	FADB1 = 0xb8:1;
sbit	FADB0 = 0xb8:0;
sfr	P4CON = 0xb9;
sbit	FP4CON7 = 0xb9:7;
sbit	FP4CON6 = 0xb9:6;
sbit	FP4CON5 = 0xb9:5;
sbit	FP4CON4 = 0xb9:4;
sbit	FP4CON3 = 0xb9:3;
sbit	FP4CON2 = 0xb9:2;
sbit	FP4CON1 = 0xb9:1;
sbit	FP4CON0 = 0xb9:0;
sfr	PECMD = 0xba;
sfr	PEROML = 0xbb;
sbit	FPEROML7 = 0xbb:7;
sbit	FPEROML6 = 0xbb:6;
sbit	FPEROML5 = 0xbb:5;
sbit	FPEROML4 = 0xbb:4;
sbit	FPEROML3 = 0xbb:3;
sbit	FPEROML2 = 0xbb:2;
sbit	FPEROML1 = 0xbb:1;
sbit	FPEROML0 = 0xbb:0;
sfr	PEROMH = 0xbc;
sbit	FPEROMH7 = 0xbc:7;
sbit	FPEROMH6 = 0xbc:6;
sbit	FPEROMH5 = 0xbc:5;
sbit	FPEROMH4 = 0xbc:4;
sbit	FPEROMH3 = 0xbc:3;
sbit	FPEROMH2 = 0xbc:2;
sbit	FPEROMH1 = 0xbc:1;
sbit	FPEROMH0 = 0xbc:0;
sfr	PERAML = 0xbd;
sbit	FPERAML7 = 0xbd:7;
sbit	FPERAML6 = 0xbd:6;
sbit	FPERAML5 = 0xbd:5;
sbit	FPERAML4 = 0xbd:4;
sbit	FPERAML3 = 0xbd:3;
sbit	FPERAML2 = 0xbd:2;
sbit	FPERAML1 = 0xbd:1;
sbit	FPERAML0 = 0xbd:0;
sfr	PERAMCNT = 0xbe;
sbit	FPERAMCNT4 = 0xbe:7;
sbit	FPERAMCNT3 = 0xbe:6;
sbit	FPERAMCNT2 = 0xbe:5;
sbit	FPERAMCNT1 = 0xbe:4;
sbit	FPERAMCNT0 = 0xbe:3;
sbit	FPERAML9 = 0xbe:1;
sbit	FPERAML8 = 0xbe:0;
sfr	PEDGE = 0xbf;
sbit	FP01G1 = 0xbf:3;
sbit	FP01G0 = 0xbf:2;
sbit	FP00G1 = 0xbf:1;
sbit	FP00G0 = 0xbf:0;
sfr	P1W = 0xc0;
sbit	FP17W = 0xc0:7;
sbit	FP16W = 0xc0:6;
sbit	FP15W = 0xc0:5;
sbit	FP14W = 0xc0:4;
sbit	FP13W = 0xc0:3;
sbit	FP12W = 0xc0:2;
sbit	FP11W = 0xc0:1;
sbit	FP10W = 0xc0:0;
sfr	P1M = 0xc1;
sbit	FP17M = 0xc1:7;
sbit	FP16M = 0xc1:6;
sbit	FP15M = 0xc1:5;
sbit	FP14M = 0xc1:4;
sbit	FP13M = 0xc1:3;
sbit	FP12M = 0xc1:2;
sbit	FP11M = 0xc1:1;
sbit	FP10M = 0xc1:0;
sfr	P2M = 0xc2;
sbit	FP27M = 0xc2:7;
sbit	FP26M = 0xc2:6;
sbit	FP25M = 0xc2:5;
sbit	FP24M = 0xc2:4;
sbit	FP23M = 0xc2:3;
sbit	FP22M = 0xc2:2;
sbit	FP21M = 0xc2:1;
sbit	FP20M = 0xc2:0;
sfr	P4M = 0xc4;
sbit	FP47M = 0xc4:7;
sbit	FP46M = 0xc4:6;
sbit	FP45M = 0xc4:5;
sbit	FP44M = 0xc4:4;
sbit	FP43M = 0xc4:3;
sbit	FP42M = 0xc4:2;
sbit	FP41M = 0xc4:1;
sbit	FP40M = 0xc4:0;
sfr	P5M = 0xc5;
sbit	FP55M = 0xc5:5;
sbit	FP54M = 0xc5:4;
sbit	FP53M = 0xc5:3;
sbit	FP52M = 0xc5:2;
sbit	FP51M = 0xc5:1;
sbit	FP50M = 0xc5:0;
sfr	INTRQ1 = 0xc6;
sbit	FP1IRQ = 0xc6:7;
sbit	FP0IRQ = 0xc6:6;
sbit	FMSPIRQ = 0xc6:5;
sbit	FUTRXIRQ = 0xc6:4;
sbit	FUTTXIRQ = 0xc6:3;
sbit	FTC2IRQ = 0xc6:2;
sbit	FTC1IRQ = 0xc6:1;
sbit	FTC0IRQ = 0xc6:0;
sfr	INTEN1 = 0xc7;
sbit	FP1IEN = 0xc7:7;
sbit	FP0IEN = 0xc7:6;
sbit	FMSPIEN = 0xc7:5;
sbit	FUTRXIEN = 0xc7:4;
sbit	FUTTXIEN = 0xc7:3;
sbit	FTC2IEN = 0xc7:2;
sbit	FTC1IEN = 0xc7:1;
sbit	FTC0IEN = 0xc7:0;
sfr	INTRQ = 0xc8;
sbit	FADCIRQ = 0xc8:7;
sbit	FUSBIRQ = 0xc8:6;
sbit	FT1IRQ = 0xc8:5;
sbit	FT0IRQ = 0xc8:4;
sbit	FSIOIRQ = 0xc8:3;
sbit	FWAKEIRQ = 0xc8:2;
sbit	FP01IRQ = 0xc8:1;
sbit	FP00IRQ = 0xc8:0;
sfr	INTEN = 0xc9;
sbit	FADCIEN = 0xc9:7;
sbit	FUSBIEN = 0xc9:6;
sbit	FT1IEN = 0xc9:5;
sbit	FT0IEN = 0xc9:4;
sbit	FSIOIEN = 0xc9:3;
sbit	FWAKEIEN = 0xc9:2;
sbit	FP01IEN = 0xc9:1;
sbit	FP00IEN = 0xc9:0;
sfr	OSCM = 0xca;
sbit	FCPUM1 = 0xca:4;
sbit	FCPUM0 = 0xca:3;
sbit	FCLKMD = 0xca:2;
sbit	FSTPHX = 0xca:1;
sfr	WDTR = 0xcc;
sfr	PCL = 0xce;
sbit	FPC7 = 0xce:7;
sbit	FPC6 = 0xce:6;
sbit	FPC5 = 0xce:5;
sbit	FPC4 = 0xce:4;
sbit	FPC3 = 0xce:3;
sbit	FPC2 = 0xce:2;
sbit	FPC1 = 0xce:1;
sbit	FPC0 = 0xce:0;
sfr	PCH = 0xcf;
sbit	FPC13 = 0xcf:5;
sbit	FPC12 = 0xcf:4;
sbit	FPC11 = 0xcf:3;
sbit	FPC10 = 0xcf:2;
sbit	FPC9 = 0xcf:1;
sbit	FPC8 = 0xcf:0;
sfr	P0 = 0xd0;
sbit	FP07 = 0xd0:7;
sbit	FP06 = 0xd0:6;
sbit	FP05 = 0xd0:5;
sbit	FP04 = 0xd0:4;
sbit	FP03 = 0xd0:3;
sbit	FP02 = 0xd0:2;
sbit	FP01 = 0xd0:1;
sbit	FP00 = 0xd0:0;
sfr	P1 = 0xd1;
sbit	FP17 = 0xd1:7;
sbit	FP16 = 0xd1:6;
sbit	FP15 = 0xd1:5;
sbit	FP14 = 0xd1:4;
sbit	FP13 = 0xd1:3;
sbit	FP12 = 0xd1:2;
sbit	FP11 = 0xd1:1;
sbit	FP10 = 0xd1:0;
sfr	P2 = 0xd2;
sbit	FP27 = 0xd2:7;
sbit	FP26 = 0xd2:6;
sbit	FP25 = 0xd2:5;
sbit	FP24 = 0xd2:4;
sbit	FP23 = 0xd2:3;
sbit	FP22 = 0xd2:2;
sbit	FP21 = 0xd2:1;
sbit	FP20 = 0xd2:0;
sfr	P4 = 0xd4;
sbit	FP47 = 0xd4:7;
sbit	FP46 = 0xd4:6;
sbit	FP45 = 0xd4:5;
sbit	FP44 = 0xd4:4;
sbit	FP43 = 0xd4:3;
sbit	FP42 = 0xd4:2;
sbit	FP41 = 0xd4:1;
sbit	FP40 = 0xd4:0;
sfr	P5 = 0xd5;
sbit	FP55 = 0xd5:5;
sbit	FP54 = 0xd5:4;
sbit	FP53 = 0xd5:3;
sbit	FP52 = 0xd5:2;
sbit	FP51 = 0xd5:1;
sbit	FP50 = 0xd5:0;
sfr	T0M = 0xd8;
sbit	FT0ENB = 0xd8:7;
sbit	FT0RATE2 = 0xd8:6;
sbit	FT0RATE1 = 0xd8:5;
sbit	FT0RATE0 = 0xd8:4;
sfr	T0C = 0xd9;
sbit	FT0C7 = 0xd9:7;
sbit	FT0C6 = 0xd9:6;
sbit	FT0C5 = 0xd9:5;
sbit	FT0C4 = 0xd9:4;
sbit	FT0C3 = 0xd9:3;
sbit	FT0C2 = 0xd9:2;
sbit	FT0C1 = 0xd9:1;
sbit	FT0C0 = 0xd9:0;
sfr	T1M = 0xda;
sbit	FT1ENB = 0xda:7;
sbit	FT1RATE2 = 0xda:6;
sbit	FT1RATE1 = 0xda:5;
sbit	FT1RATE0 = 0xda:4;
sfr	T1CL = 0xdb;
sbit	FT1C7 = 0xdb:7;
sbit	FT1C6 = 0xdb:6;
sbit	FT1C5 = 0xdb:5;
sbit	FT1C4 = 0xdb:4;
sbit	FT1C3 = 0xdb:3;
sbit	FT1C2 = 0xdb:2;
sbit	FT1C1 = 0xdb:1;
sbit	FT1C0 = 0xdb:0;
sfr	T1CH = 0xdc;
sbit	FT1C15 = 0xdc:7;
sbit	FT1C14 = 0xdc:6;
sbit	FT1C13 = 0xdc:5;
sbit	FT1C12 = 0xdc:4;
sbit	FT1C11 = 0xdc:3;
sbit	FT1C10 = 0xdc:2;
sbit	FT1C9 = 0xdc:1;
sbit	FT1C8 = 0xdc:0;
sfr	STKP = 0xdf;
sbit	FGIE = 0xdf:7;
sbit	FSTKPB2 = 0xdf:2;
sbit	FSTKPB1 = 0xdf:1;
sbit	FSTKPB0 = 0xdf:0;
sfr	P0UR = 0xe0;
sfr	P1UR = 0xe1;
sfr	P2UR = 0xe2;
sfr	P4UR = 0xe4;
sfr	P5UR = 0xe5;
sfr	_YZ = 0xe7;
sfr	P1OC = 0xe9;
sbit	FP06OC = 0xe9:3;
sbit	FP05OC = 0xe9:2;
sbit	FP11OC = 0xe9:1;
sbit	FP10OC = 0xe9:0;
sfr	MSPSTAT = 0xea;
sbit	FCKE = 0xea:6;
sbit	FD_A = 0xea:5;
sbit	FP = 0xea:4;
sbit	FS = 0xea:3;
sbit	FRED_WRT = 0xea:2;
sbit	FBF = 0xea:0;
sfr	MSPM1 = 0xeb;
sbit	FWCOL = 0xeb:7;
sbit	FMSPOV = 0xeb:6;
sbit	FMSPENB = 0xeb:5;
sbit	FCKP = 0xeb:4;
sbit	FSLRXCKP = 0xeb:3;
sbit	FMSPWK = 0xeb:2;
sbit	FMSPC = 0xeb:0;
sfr	MSPM2 = 0xec;
sbit	FGCEN = 0xec:7;
sbit	FACKSTAT = 0xec:6;
sbit	FACKDT = 0xec:5;
sbit	FACKEN = 0xec:4;
sbit	FRCEN = 0xec:3;
sbit	FPEN = 0xec:2;
sbit	FRSEN = 0xec:1;
sbit	FSEN = 0xec:0;
sfr	MSPBUF = 0xed;
sbit	FMSPBUF7 = 0xed:7;
sbit	FMSPBUF6 = 0xed:6;
sbit	FMSPBUF5 = 0xed:5;
sbit	FMSPBUF4 = 0xed:4;
sbit	FMSPBUF3 = 0xed:3;
sbit	FMSPBUF2 = 0xed:2;
sbit	FMSPBUF1 = 0xed:1;
sbit	FMSPBUF0 = 0xed:0;
sfr	MSPADR = 0xee;
sbit	FMSPADR7 = 0xee:7;
sbit	FMSPADR6 = 0xee:6;
sbit	FMSPADR5 = 0xee:5;
sbit	FMSPADR4 = 0xee:4;
sbit	FMSPADR3 = 0xee:3;
sbit	FMSPADR2 = 0xee:2;
sbit	FMSPADR1 = 0xee:1;
sbit	FMSPADR0 = 0xee:0;
sfr	STK7L = 0xf0;
sbit	FS7PC7 = 0xf0:7;
sbit	FS7PC6 = 0xf0:6;
sbit	FS7PC5 = 0xf0:5;
sbit	FS7PC4 = 0xf0:4;
sbit	FS7PC3 = 0xf0:3;
sbit	FS7PC2 = 0xf0:2;
sbit	FS7PC1 = 0xf0:1;
sbit	FS7PC0 = 0xf0:0;
sfr	STK7H = 0xf1;
sbit	FS7PC13 = 0xf1:5;
sbit	FS7PC12 = 0xf1:4;
sbit	FS7PC11 = 0xf1:3;
sbit	FS7PC10 = 0xf1:2;
sbit	FS7PC9 = 0xf1:1;
sbit	FS7PC8 = 0xf1:0;
sfr	STK6L = 0xf2;
sbit	FS6PC7 = 0xf2:7;
sbit	FS6PC6 = 0xf2:6;
sbit	FS6PC5 = 0xf2:5;
sbit	FS6PC4 = 0xf2:4;
sbit	FS6PC3 = 0xf2:3;
sbit	FS6PC2 = 0xf2:2;
sbit	FS6PC1 = 0xf2:1;
sbit	FS6PC0 = 0xf2:0;
sfr	STK6H = 0xf3;
sbit	FS6PC13 = 0xf3:5;
sbit	FS6PC12 = 0xf3:4;
sbit	FS6PC11 = 0xf3:3;
sbit	FS6PC10 = 0xf3:2;
sbit	FS6PC9 = 0xf3:1;
sbit	FS6PC8 = 0xf3:0;
sfr	STK5L = 0xf4;
sbit	FS5PC7 = 0xf4:7;
sbit	FS5PC6 = 0xf4:6;
sbit	FS5PC5 = 0xf4:5;
sbit	FS5PC4 = 0xf4:4;
sbit	FS5PC3 = 0xf4:3;
sbit	FS5PC2 = 0xf4:2;
sbit	FS5PC1 = 0xf4:1;
sbit	FS5PC0 = 0xf4:0;
sfr	STK5H = 0xf5;
sbit	FS5PC13 = 0xf5:5;
sbit	FS5PC12 = 0xf5:4;
sbit	FS5PC11 = 0xf5:3;
sbit	FS5PC10 = 0xf5:2;
sbit	FS5PC9 = 0xf5:1;
sbit	FS5PC8 = 0xf5:0;
sfr	STK4L = 0xf6;
sbit	FS4PC7 = 0xf6:7;
sbit	FS4PC6 = 0xf6:6;
sbit	FS4PC5 = 0xf6:5;
sbit	FS4PC4 = 0xf6:4;
sbit	FS4PC3 = 0xf6:3;
sbit	FS4PC2 = 0xf6:2;
sbit	FS4PC1 = 0xf6:1;
sbit	FS4PC0 = 0xf6:0;
sfr	STK4H = 0xf7;
sbit	FS4PC13 = 0xf7:5;
sbit	FS4PC12 = 0xf7:4;
sbit	FS4PC11 = 0xf7:3;
sbit	FS4PC10 = 0xf7:2;
sbit	FS4PC9 = 0xf7:1;
sbit	FS4PC8 = 0xf7:0;
sfr	STK3L = 0xf8;
sbit	FS3PC7 = 0xf8:7;
sbit	FS3PC6 = 0xf8:6;
sbit	FS3PC5 = 0xf8:5;
sbit	FS3PC4 = 0xf8:4;
sbit	FS3PC3 = 0xf8:3;
sbit	FS3PC2 = 0xf8:2;
sbit	FS3PC1 = 0xf8:1;
sbit	FS3PC0 = 0xf8:0;
sfr	STK3H = 0xf9;
sbit	FS3PC13 = 0xf9:5;
sbit	FS3PC12 = 0xf9:4;
sbit	FS3PC11 = 0xf9:3;
sbit	FS3PC10 = 0xf9:2;
sbit	FS3PC9 = 0xf9:1;
sbit	FS3PC8 = 0xf9:0;
sfr	STK2L = 0xfa;
sbit	FS2PC7 = 0xfa:7;
sbit	FS2PC6 = 0xfa:6;
sbit	FS2PC5 = 0xfa:5;
sbit	FS2PC4 = 0xfa:4;
sbit	FS2PC3 = 0xfa:3;
sbit	FS2PC2 = 0xfa:2;
sbit	FS2PC1 = 0xfa:1;
sbit	FS2PC0 = 0xfa:0;
sfr	STK2H = 0xfb;
sbit	FS2PC13 = 0xfb:5;
sbit	FS2PC12 = 0xfb:4;
sbit	FS2PC11 = 0xfb:3;
sbit	FS2PC10 = 0xfb:2;
sbit	FS2PC9 = 0xfb:1;
sbit	FS2PC8 = 0xfb:0;
sfr	STK1L = 0xfc;
sbit	FS1PC7 = 0xfc:7;
sbit	FS1PC6 = 0xfc:6;
sbit	FS1PC5 = 0xfc:5;
sbit	FS1PC4 = 0xfc:4;
sbit	FS1PC3 = 0xfc:3;
sbit	FS1PC2 = 0xfc:2;
sbit	FS1PC1 = 0xfc:1;
sbit	FS1PC0 = 0xfc:0;
sfr	STK1H = 0xfd;
sbit	FS1PC13 = 0xfd:5;
sbit	FS1PC12 = 0xfd:4;
sbit	FS1PC11 = 0xfd:3;
sbit	FS1PC10 = 0xfd:2;
sbit	FS1PC9 = 0xfd:1;
sbit	FS1PC8 = 0xfd:0;
sfr	STK0L = 0xfe;
sbit	FS0PC7 = 0xfe:7;
sbit	FS0PC6 = 0xfe:6;
sbit	FS0PC5 = 0xfe:5;
sbit	FS0PC4 = 0xfe:4;
sbit	FS0PC3 = 0xfe:3;
sbit	FS0PC2 = 0xfe:2;
sbit	FS0PC1 = 0xfe:1;
sbit	FS0PC0 = 0xfe:0;
sfr	STK0H = 0xff;
sbit	FS0PC13 = 0xff:5;
sbit	FS0PC12 = 0xff:4;
sbit	FS0PC11 = 0xff:3;
sbit	FS0PC10 = 0xff:2;
sbit	FS0PC9 = 0xff:1;
sbit	FS0PC8 = 0xff:0;
#define SLEEPMODE __asm{SleepMode}
#define GREENMODE __asm{GreenMode}
#define SLOWMODE __asm{SlowMode}
#define SLOW2NORMAL __asm{Slow2Normal}
#define SET_P3_INPUT_PULLUP __asm{Set_P3_Input_Pullup}
#endif
