/**
******************************************************************************************************************************************************************************************
*@file                       cpu_i2c.h
*@author         
*@data                       
*@version                    v1.0
*@par Copyright(c):
*
*@par History:
*     version:author,date,desc
*     v1.0   :create this file
*
*******************************************************************************************************************************************************************************************
*/
#ifndef CPU_I2C
#define CPU_I2C


#ifdef __cplusplus
 extern "C" {
#endif

#include "cpu.h"


/** @defgroup i2c_mode 
  * @{
  */

typedef enum
{
	I2C_Mode_Master					=((uint32_t)0x0001),
	I2C_Mode_Slave					=((uint32_t)0x0002)
}i2c_mode_type_def;

#define IS_I2C_MODE(MODE)						(((MODE) == I2C_Mode_Master) || \
											    ((MODE) == I2C_Mode_Slave))
/**
  * @}
  */	 
	 
typedef struct
{
	
	uint32_t i2c_clock_speed;			/*!< Specifies the clock frequency. */

	i2c_mode_type_def i2c_mode;          

	uint32_t i2c_duty_cycle;				/*!< Specifies the I2C fast mode duty cycle.
                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
	uint32_t i2c_sda_setup_time;

	uint32_t i2c_sda_hold_time;

	uint32_t i2c_target_address;

	uint32_t i2c_target_address_mode;

	uint32_t i2c_own_address;			/*!< Specifies the slave mode own address.
                                         This parameter can be a 7-bit or 10-bit address. */

	uint32_t i2c_acknowledged_address;	/*!< Specifies if 7-bit or 10-bit address is acknowledged.
                                         This parameter can be a value of @ref I2C_acknowledged_address */

	uint32_t i2c_rx_fifo_full_threshold;

	uint32_t i2c_tx_fifo_empty_threshold;

	functional_state_t i2c_generate_restart_enable;
}i2c_init_type_def;


typedef struct
{
	uint32_t i2c_dma_req;
	uint32_t i2c_dma_receive_level;
	uint32_t i2c_dma_transmit_level;
	functional_state_t i2c_dma_encmd;
}i2c_dma_init_type_def;


/** @defgroup I2C_Exported_Constants
  * @{
  */

#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C))


#define I2C_ClockSpeed_100KHz					(100000)
#define I2C_ClockSpeed_200KHz					(200000)
#define I2C_ClockSpeed_300KHz					(300000)
#define I2C_ClockSpeed_400KHz					(400000)


/** @defgroup I2C_duty_cycle_in_fast_mode 
  * @{
  */
/*Tlow/Thigh = ((I2C_DutyCycle_x_y & 0xFF00) >> 8) / (I2C_DutyCycle_x_y & 0x00FF)*/
#define I2C_DutyCycle_1					((uint16_t)0x0101) /*!< I2C standard mode Tlow/Thigh = 1 */
#define I2C_DutyCycle_16_9              ((uint16_t)0x1009) /*!< I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2                 ((uint16_t)0x0201) /*!< I2C fast mode Tlow/Thigh = 2 */
#define I2C_DutyCycle_8_3               ((uint16_t)0x0803) /*!< I2C high mode Tlow/Thigh = 8/3 */
#define IS_I2C_DUTY_CYCLE(CYCLE)		(((CYCLE) == I2C_DutyCycle_16_9) || \
										((CYCLE) == I2C_DutyCycle_2))
/**
  * @}
  */ 


#define IS_I2C_SDA_SETUP_TIME(TIME)		((TIME) <= 0x000000FF)
#define IS_I2C_SDA_HOLD_TIME(TIME)		((TIME) <= 0x0000FFFF)

/** @defgroup I2C_acknowledged_address 
  * @{
  */
#define I2C_AcknowledgedAddress_7bit			((uint16_t)0x0001)
#define I2C_AcknowledgedAddress_10bit			((uint16_t)0x0002)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS)		(((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
												((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/**
  * @}
  */ 
	 
/** @defgroup Target_Address_Bit
  * @{
  */
#define I2C_TargetAddressMode_7bit				((uint16_t)0x0001)
#define I2C_TargetAddressMode_10bit				((uint16_t)0x0002)
#define IS_I2C_TARGET_ADDRESS_MODE(ADDRESS)		(((ADDRESS) == I2C_TargetAddressMode_7bit) || \
												((ADDRESS) == I2C_TargetAddressMode_10bit))

/**
  * @}
  */ 


/** @defgroup spi_rx_fifo_full_threshold 
  * @{
  */
#define I2C_RXFIFOFullThreshold_1				((uint32_t)0x0000)
#define I2C_RXFIFOFullThreshold_2				((uint32_t)0x0001)
#define I2C_RXFIFOFullThreshold_3				((uint32_t)0x0002)
#define I2C_RXFIFOFullThreshold_4		        ((uint32_t)0x0003)
#define I2C_RXFIFOFullThreshold_5				((uint32_t)0x0004)
#define I2C_RXFIFOFullThreshold_6				((uint32_t)0x0005)
#define I2C_RXFIFOFullThreshold_7				((uint32_t)0x0006)
#define I2C_RXFIFOFullThreshold_8				((uint32_t)0x0007)

#define IS_I2C_RX_FIFO_FULL_THRESHOLD(THRESHOLD)	((((int32_t)(THRESHOLD)) >= I2C_RXFIFOFullThreshold_1) && \
													  (((int32_t)(THRESHOLD)) <= I2C_RXFIFOFullThreshold_8))
/**
  * @}
  */ 

/** @defgroup spi_rx_fifo_empty_threshold
  * @{
  */
#define I2C_TXFIFOEmptyThreshold_0				((uint32_t)0x0000)
#define I2C_TXFIFOEmptyThreshold_1				((uint32_t)0x0001)
#define I2C_TXFIFOEmptyThreshold_2				((uint32_t)0x0002)
#define I2C_TXFIFOEmptyThreshold_3				((uint32_t)0x0003)
#define I2C_TXFIFOEmptyThreshold_4				((uint32_t)0x0004)
#define I2C_TXFIFOEmptyThreshold_5				((uint32_t)0x0005)
#define I2C_TXFIFOEmptyThreshold_6				((uint32_t)0x0006)
#define I2C_TXFIFOEmptyThreshold_7				((uint32_t)0x0007)
#define I2C_TXFIFOEmptyThreshold_8				((uint32_t)0x0008)

#define IS_I2C_TX_FIFO_EMPTY_THRESHOLD(THRESHOLD)	((((int32_t)(THRESHOLD)) >= I2C_TXFIFOEmptyThreshold_0) && \
													(((int32_t)(THRESHOLD)) <= I2C_TXFIFOEmptyThreshold_8))
/**
  * @}
  */ 


/** @defgroup i2c_dma_receive_level 
  * @{
  */

#define I2C_DMAReceiveLevel_1				    ((uint32_t)0x0000)
#define I2C_DMAReceiveLevel_2			        ((uint32_t)0x0001)
#define I2C_DMAReceiveLevel_3					((uint32_t)0x0002)
#define I2C_DMAReceiveLevel_4					((uint32_t)0x0003)
#define I2C_DMAReceiveLevel_5					((uint32_t)0x0004)
#define I2C_DMAReceiveLevel_6					((uint32_t)0x0005)
#define I2C_DMAReceiveLevel_7					((uint32_t)0x0006)
#define I2C_DMAReceiveLevel_8					((uint32_t)0x0007)

#define IS_I2C_DMA_RECEIVE_LEVEL(LEVEL)			((((int32_t)(LEVEL)) >= I2C_DMAReceiveLevel_1) && \
												(((int32_t)(LEVEL)) <= I2C_DMAReceiveLevel_8))
/**
  * @}
  */ 

/** @defgroup i2c_dma_transmit_level 
  * @{
  */
#define I2C_DMATransmitLevel_0					((uint32_t)0x0000)
#define I2C_DMATransmitLevel_1					((uint32_t)0x0001)
#define I2C_DMATransmitLevel_2					((uint32_t)0x0002)
#define I2C_DMATransmitLevel_3					((uint32_t)0x0003)
#define I2C_DMATransmitLevel_4					((uint32_t)0x0004)
#define I2C_DMATransmitLevel_5					((uint32_t)0x0005)
#define I2C_DMATransmitLevel_6					((uint32_t)0x0006)
#define I2C_DMATransmitLevel_7					((uint32_t)0x0007)

#define IS_I2C_DMA_TRANSMIT_LEVEL(LEVEL)	((((int32_t)(LEVEL)) >= I2C_DMATransmitLevel_0) && \
											(((int32_t)(LEVEL)) <= I2C_DMATransmitLevel_7))
/**
  * @}
  */ 

/** @defgroup I2C_DMA_transfer_requests 
  * @{
  */

#define I2C_DMAReq_Rx               ((uint32_t)0x0001)
#define I2C_DMAReq_Tx               ((uint32_t)0x0002)
#define IS_I2C_DMAREQ(DMAREQ)		(((DMAREQ) & I2C_DMAReq_Tx) || \
									((DMAREQ) & I2C_DMAReq_Rx))
/**
  * @}
  */


#define I2C_IT_RXUDF					((uint32_t)0x0001)				//clear by hardware
#define I2C_IT_RXOVF					((uint32_t)0x0002)				//clear by read 
#define I2C_IT_RXF						((uint32_t)0x0004)				//clear by read
#define I2C_IT_TXOVF					((uint32_t)0x0008)				//clear by read  
#define I2C_IT_TXE						((uint32_t)0x0010)				//clear by hardware
#define I2C_IT_RD_REQ					((uint32_t)0x0020)				//clear by read
#define I2C_IT_TX_ABRT					((uint32_t)0x0040)				//clear by read  
#define I2C_IT_RX_DONE					((uint32_t)0x0080)				//clear by read 
#define I2C_IT_ACTIVITY					((uint32_t)0x0100)				//clear by read 
#define I2C_IT_STOP_DET					((uint32_t)0x0200)				//clear by read 
#define I2C_IT_START_DET				((uint32_t)0x0400)
#define I2C_IT_GEN_CALL					((uint32_t)0x0800)
#define I2C_IT_ALL						((uint32_t)0x0FFF)

#define IS_I2C_CONFIG_IT(IT)			((((IT) & (~(uint32_t)0x0FFF)) == 0x00) && ((IT) != 0x00))
#define IS_I2C_CLEAR_IT(IT)				((((IT) & (~(uint32_t)0x0FFF)) == 0x00) && ((IT) != 0x00))
#define IS_I2C_GET_IT(IT)				(((IT) == I2C_IT_RXUDF) || \
										((IT) == I2C_IT_RXOVF) || \
										((IT) == I2C_IT_RXF) || \
										((IT) == I2C_IT_TXOVF) || \
										((IT) == I2C_IT_TXE) || \
										((IT) == I2C_IT_RD_REQ) || \
										((IT) == I2C_IT_TX_ABRT) || \
										((IT) == I2C_IT_RX_DONE) || \
										((IT) == I2C_IT_ACTIVITY) || \
										((IT) == I2C_IT_STOP_DET) || \
										((IT) == I2C_IT_START_DET) || \
										((IT) == I2C_IT_GEN_CALL) || \
										((IT) == I2C_IT_ALL))


#define I2C_FLAG_ACTIVITY				((uint32_t)0x0001)
#define I2C_FLAG_TXNF					((uint32_t)0x0002)
#define I2C_FLAG_TXE					((uint32_t)0x0004)
#define I2C_FLAG_RXNE					((uint32_t)0x0008)
#define I2C_FLAG_RXF					((uint32_t)0x0010)
#define I2C_FLAG_MST_ACTIVITY			((uint32_t)0x0020)
#define I2C_FLAG_SLV_ACTIVITY			((uint32_t)0x0040)
#define I2C_FLAG_ALL					((uint32_t)0x007F)
#define IS_I2C_GET_FLAG(FLAG)			(((FLAG) == I2C_FLAG_ACTIVITY) || \
										((FLAG) == I2C_FLAG_TXNF) || \
										((FLAG) == I2C_FLAG_TXE) || \
										((FLAG) == I2C_FLAG_RXNE) || \
										((FLAG) == I2C_FLAG_RXF) || \
										((FLAG) == I2C_FLAG_MST_ACTIVITY) || \
										((FLAG) == I2C_FLAG_SLV_ACTIVITY) || \
										((FLAG) == I2C_FLAG_ALL))

#define I2C_TX_ABRT_7BIT_ADDR_NOACK					((uint32_t)0x00000001)
#define I2C_TX_ABRT_10BIT_ADDR1_NOACK				((uint32_t)0x00000002)
#define I2C_TX_ABRT_10BIT_ADDR2_NOACK				((uint32_t)0x00000004)
#define I2C_TX_ABRT_TXDATA_NOACK					((uint32_t)0x00000008)
#define I2C_TX_ABRT_GEN_CALL_NOACK					((uint32_t)0x00000010)
#define I2C_TX_ABRT_GEN_CALL_READ					((uint32_t)0x00000020)
#define I2C_TX_ABRT_HIGH_SPEED_ACKDET				((uint32_t)0x00000040)
#define I2C_TX_ABRT_START_BYTE_ACKDET				((uint32_t)0x00000080)
#define I2C_TX_ABRT_HIGH_SPEED_NORSTRT				((uint32_t)0x00000100)
#define I2C_TX_ABRT_START_BYTE_NORSTRT				((uint32_t)0x00000200)
#define I2C_TX_ABRT_10BIT_RD_NORSTRT				((uint32_t)0x00000400)
#define I2C_TX_ABRT_LOST_ARB						((uint32_t)0x00000800)
#define I2C_TX_ABRT_SLVFLUSH_TXFIFO					((uint32_t)0x00001000)
#define I2C_TX_ABRT_SLV_LOST_ARB					((uint32_t)0x00002000)
#define I2C_TX_ABRT_SLV_RD_INTX						((uint32_t)0x00004000)
#define I2C_TX_ABRT_MASTER_DISABLE					((uint32_t)0x00008000)
#define I2C_TX_ABRT_USER_ABRT						((uint32_t)0x00010000)
#define I2C_TX_ABRT_TX_FLUSH_CNT					((uint32_t)0x00020000)
#define IS_I2C_TX_ABRT(ABRT)						(((ABRT) == I2C_TX_ABRT_7BIT_ADDR_NOACK) || \
													((ABRT) == I2C_TX_ABRT_10BIT_ADDR1_NOACK) || \
													((FLAG) == I2C_TX_ABRT_10BIT_ADDR2_NOACK) || \
													((FLAG) == I2C_TX_ABRT_TXDATA_NOACK) || \
													((FLAG) == I2C_TX_ABRT_GEN_CALL_NOACK) || \
													((FLAG) == I2C_TX_ABRT_GEN_CALL_READ) || \
													((FLAG) == I2C_TX_ABRT_HIGH_SPEED_ACKDET) || \
													((FLAG) == I2C_TX_ABRT_START_BYTE_ACKDET) || \
													((FLAG) == I2C_TX_ABRT_HIGH_SPEED_NORSTRT) || \
													((FLAG) == I2C_TX_ABRT_START_BYTE_NORSTRT) || \
													((FLAG) == I2C_TX_ABRT_10BIT_RD_NORSTRT) || \
													((FLAG) == I2C_TX_ABRT_LOST_ARB) || \
													((FLAG) == I2C_TX_ABRT_SLVFLUSH_TXFIFO) || \
													((FLAG) == I2C_TX_ABRT_SLV_LOST_ARB) || \
													((FLAG) == I2C_TX_ABRT_SLV_RD_INTX) || \
													((FLAG) == I2C_TX_ABRT_MASTER_DISABLE) || \
													((FLAG) == I2C_TX_ABRT_USER_ABRT) || \
													((FLAG) == I2C_TX_ABRT_TX_FLUSH_CNT))

typedef enum
{
	I2C_DataCMD_Write					= (uint32_t)0x01,
	I2C_DataCMD_Read					= (uint32_t)0x02
}i2c_data_cmd_type_def;
#define IS_I2C_DATA_CMD(CMD)			(((CMD) == I2C_DataCMD_Write) || \
										((CMD) == I2C_DataCMD_Read))

typedef enum
{
	I2C_DataEndCondition_None			= (uint32_t)0x01,
	I2C_DataEndCondition_Stop			= (uint32_t)0x02,
	I2C_DataEndCondition_Restart		= (uint32_t)0x03
}i2c_data_end_condition_type_def;
#define IS_I2C_DATA_END_CONDITION(CONDITION)	(((CONDITION) == I2C_DataEndCondition_None) || \
												((CONDITION) == I2C_DataEndCondition_Stop) || \
												((CONDITION) == I2C_DataEndCondition_Restart))


void i2c_init(i2c_type_def* i2cx,i2c_init_type_def* i2c_init_struct);
void i2c_struct_init(i2c_init_type_def* i2c_init_struct);
void i2c_cmd(i2c_type_def* i2cx, functional_state_t new_state);
void i2c_set_target_address(i2c_type_def* i2cx, uint32_t target_address, uint32_t target_address_mode);
void i2c_dma_init(i2c_type_def* i2cx, i2c_dma_init_type_def* i2c_dma_init_struct);
void i2c_dma_struct_init(i2c_dma_init_type_def* i2c_dma_init_struct);
void i2c_dma_cmd(i2c_type_def* i2cx, uint32_t i2c_dma_req, functional_state_t new_state);
void i2c_set_sda_setup_time(i2c_type_def* i2cx,uint32_t pclk_cycles);
void i2c_set_sda_hold_time(i2c_type_def* i2cx,uint32_t pclk_cycles);

void i2c_it_config(i2c_type_def* i2cx,uint32_t i2c_it, functional_state_t new_state);
itstatus i2c_get_it_status(i2c_type_def* i2cx,uint32_t i2c_it);
itstatus i2c_get_raw_it_status(i2c_type_def* i2cx,uint32_t i2c_it);
void i2c_clear_it_pending_bit(i2c_type_def* i2cx,uint32_t i2c_it);
flag_status i2c_get_flag_status(i2c_type_def* i2cx,uint32_t I2C_FLAG);
uint32_t i2c_get_flag_status_reg(i2c_type_def* i2cx);
flag_status i2c_get_tx_abort_source(i2c_type_def* i2cx,uint32_t i2c_tx_abrt);
uint32_t i2c_get_tx_abort_source_reg(i2c_type_def* i2cx);
i2c_mode_type_def i2c_get_i2c_mode(i2c_type_def* i2cx);

void i2c_master_generate_receive_scl(i2c_type_def* i2cx, i2c_data_end_condition_type_def data_condition);
uint16_t i2c_extend_data(uint8_t data, i2c_data_cmd_type_def data_cmd, i2c_data_end_condition_type_def data_condition);
void i2c_write_data_to_dr(i2c_type_def* i2cx, uint16_t ExtendData);
uint8_t i2c_read_data_from_dr(i2c_type_def* i2cx);
void i2c_send_data(i2c_type_def* i2cx, uint8_t data, i2c_data_end_condition_type_def data_condition);
uint8_t i2c_receive_data(i2c_type_def* i2cx, i2c_data_end_condition_type_def data_condition);
void i2c_send_bytes(i2c_type_def* i2cx, uint8_t* data, uint32_t data_len, i2c_data_end_condition_type_def data_condition);
void i2c_receive_bytes(i2c_type_def* i2cx, uint8_t* data, uint32_t data_len, i2c_data_end_condition_type_def data_condition);

void i2c_slave_general_nack_only_cmd(i2c_type_def* i2cx, functional_state_t new_state);

flag_status i2c_is_enable(i2c_type_def* i2cx);



#ifdef __cplusplus
}
#endif

#endif
