/**
******************************************************************************************************************************************************************************************
*@file                       cpu.h
*@author         
*@data                       
*@version                    v1.0
*@par Copyright(c):
*
*@par History:
*     version:author,date,desc
*     v1.0   :create this file
*
*******************************************************************************************************************************************************************************************
*/
#ifndef CPU_H      /* ToDo: replace '<Device>' with your device name */
#define CPU_H

#ifdef __cplusplus
 extern "C" {
#endif

typedef enum IRQn
{
    /* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device       */
    NonMaskableInt_IRQn           = -14,      /*!<  2 Non Maskable Interrupt                        */
    MemoryManagement_IRQn         = -12,      /*!<  4 Memory Management Interrupt                   */
    BusFault_IRQn                 = -11,      /*!<  5 Bus Fault Interrupt                           */
    UsageFault_IRQn               = -10,      /*!<  6 Usage Fault Interrupt                         */
    SVCall_IRQn                   = -5,       /*!< 11 SV Call Interrupt                             */
    DebugMonitor_IRQn             = -4,       /*!< 12 Debug Monitor Interrupt                       */
    PendSV_IRQn                   = -2,       /*!< 14 Pend SV Interrupt                             */
    SysTick_IRQn                  = -1,       /*!< 15 System Tick Interrupt                         */

    /******  Device Specific Interrupt Numbers ********************************************************/
    /* ToDo: add here your device specific external interrupt numbers
         according the interrupt handlers defined in startup_Device.s
         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn                        */
    DMA_IRQn                                        = 0,
    I2C_IRQn                                        = 1,
    UART0_IRQn                                      = 2,
    UART1_IRQn                                      = 3,
    SPI0_IRQn                                       = 4,
    SPI1_IRQn                                       = 5,
    QDEC_IRQn                                       = 6,
    GPADC_IRQn                                      = 7,
    Timer0_IRQn                                     = 8,
    Timer1_IRQn                                     = 9,
    Timer2_IRQn                                     = 10,
    Timer3_IRQn                                     = 11,
    Keyboard_IRQn                                   = 12,
    RTC_IRQn                                        = 13,
    RNG_IRQn                                        = 15,
    GPIO_INT0_IRQn                                  = 16,
    GPIO_INT1_IRQn                                  = 17,
    GPIO_INT2_IRQn                                  = 18,
    GPIO_INT3_IRQn                                  = 19,
    ROM_LIB_8_IRQN                                  = 20,
    ROM_LIB_9_IRQN                                  = 21,
    ROM_LIB_10_IRQN                                 = 22,
    ROM_LIB_11_IRQN                                 = 23,
    ROM_LIB_0_IRQN                                  = 24,
    ROM_LIB_1_IRQN                                  = 25,
    ROM_LIB_2_IRQN                                  = 26,
    ROM_LIB_3_IRQN                                  = 27,
    ROM_LIB_4_IRQN                                  = 28,
    ROM_LIB_5_IRQN                                  = 29,
    ROM_LIB_6_IRQN                                  = 30,
    ROM_LIB_7_IRQN                                  = 31,
    ROM_LIB_12_IRQN                                 = 32,
    ROM_LIB_13_IRQN                                 = 33
} IRQn_Type;

#define __CM3_REV                 0x0200    /// Core Revision r2p0                               */
#define __NVIC_PRIO_BITS          3         /// Number of Bits used for Priority Levels          */
#define __Vendor_SysTickConfig    0         /// Set to 1 if different SysTick Config is used     */
#define __MPU_PRESENT             0         /// MPU present or not                               */
/// ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4                                       */
#define __FPU_PRESENT             0         /// FPU present or not 


#include "core_cm3.h"                       /// Cortex-M# processor and core peripherals           */
#include "system_cpu.h"                     /// <Device> System  include file                      */
#include <stdint.h>

#undef TRUE
#undef FALSE
typedef enum {FALSE   = 0, TRUE    = !FALSE  } boolean;
typedef enum {LOW     = 0, HIGHT    = 1       } level;
typedef enum {RESET   = 0, SET     = !RESET  } flag_status, itstatus;
typedef enum {DISABLE = 0, ENABLE  = !DISABLE} functional_state_t;
typedef enum {ERROR   = 0, SUCCESS = !ERROR  } error_status;
typedef enum {OFF   = 0, ON = !OFF  } swt_status;

#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

/* ToDo: add here your device specific peripheral access structure typedefs
         following is an example for a timer                                  */
#define BIT0        (0x00000001U)
#define BIT1        (0x00000002U)
#define BIT2        (0x00000004U)
#define BIT3        (0x00000008U)
#define BIT4        (0x00000010U)
#define BIT5        (0x00000020U)
#define BIT6        (0x00000040U)
#define BIT7        (0x00000080U)
#define BIT8        (0x00000100U)
#define BIT9        (0x00000200U)
#define BIT10       (0x00000400U)
#define BIT11       (0x00000800U)
#define BIT12       (0x00001000U)
#define BIT13       (0x00002000U)
#define BIT14       (0x00004000U)
#define BIT15       (0x00008000U)
#define BIT16       (0x00010000U)
#define BIT17       (0x00020000U)
#define BIT18       (0x00040000U)
#define BIT19       (0x00080000U)
#define BIT20       (0x00100000U)
#define BIT21       (0x00200000U)
#define BIT22       (0x00400000U)
#define BIT23       (0x00800000U)
#define BIT24       (0x01000000U)
#define BIT25       (0x02000000U)
#define BIT26       (0x04000000U)
#define BIT27       (0x08000000U)
#define BIT28       (0x10000000U)
#define BIT29       (0x20000000U)
#define BIT30       (0x40000000U)
#define BIT31       (0x80000000U)
#define TEST_BIT(v,n) (v & (0x00000001U << n))



/******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/

/* Peripheral and SRAM base address */
#define CPU_FLASH_BASE           (0x00000000UL)                              /*!< (FLASH     ) Base Address */
#define CPU_SRAM_BASE            (0x20000000UL)                              /*!< (SRAM      ) Base Address */
#define CPU_PERIPH_BASE          (0x40000000UL)                              /*!< (Peripheral) Base Address */

/* Peripheral memory map */
#define CPU_AHB_BASE                (CPU_PERIPH_BASE)
#define CPU_APB0_BASE               (0x50000000UL)

#define CRM_BASE                    (CPU_AHB_BASE + 0x6000)
#define FCU_BASE                    (CPU_AHB_BASE + 0x5000)
#define QSPI_BASE                   (CPU_AHB_BASE + 0x9000)
#define CACHE_BASE                  (CPU_AHB_BASE + 0x5020)
#define DMA_BASE             (CPU_AHB_BASE + 0x4000)

#define I2C_BASE                    (CPU_APB0_BASE)
#define UART0_BASE                  (CPU_APB0_BASE + 0x1000)
#define UART1_BASE                  (CPU_APB0_BASE + 0x2000)
#define SPI0_BASE                   (CPU_APB0_BASE + 0x3000)
#define SPI1_BASE                   (CPU_APB0_BASE + 0x4000)
#define QDEC_BASE                   (CPU_APB0_BASE + 0x6000)
#define KEYBOARD_BASE               (CPU_APB0_BASE + 0x7000)
#define SYSCFG_BASE                 (CPU_APB0_BASE + 0x8000)
#define TIMER01_BASE                (CPU_APB0_BASE + 0xA000)
#define TIMER23_BASE                (CPU_APB0_BASE + 0xB000)
#define WATCHDOG_BASE               (CPU_APB0_BASE + 0xC000)
#define RTC_BASE                    (CPU_APB0_BASE + 0xD000)
#define GPIO_BASE                   (CPU_APB0_BASE + 0xE000)

#define DMA0_BASE                   (DMA_MODULE_BASE)
#define DMA1_BASE                   (DMA_MODULE_BASE + 0x58)
#define DMA2_BASE                   (DMA_MODULE_BASE + 0xB0)
#define DMA3_BASE                   (DMA_MODULE_BASE + 0x108)

#define GPIOA_INOUT_BASE            (GPIO_BASE)
#define GPIOB_INOUT_BASE            (GPIO_BASE + 0x10)
#define GPIOC_INOUT_BASE            (GPIO_BASE + 0x20)
#define GPIOD_INOUT_BASE            (GPIO_BASE + 0x30)
#define GPIOA_MAP_BASE              (GPIO_BASE + 0x40)
#define GPIOB_MAP_BASE              (GPIO_BASE + 0x48)
#define GPIOC_MAP_BASE              (GPIO_BASE + 0x50)
#define GPIOD_MAP_BASE              (GPIO_BASE + 0x58)

/*
* @brief: peripheral
* 1. CRM
* 2. SYSCTRL
* 3. GPIO
* 4. RTC
* 5. WDT 
* 6. TIMER
* 7. UART
* 8. SPI
* 9. IIC
* 10.GPADC
* 11.QUADDEC
* 12.KEYBOARD
* 13.DMA
* 14 FASTCRC
*/

/********************************************** CRM **************************************************/

#define CRM_CG_CTRL_BT                      (BIT16)
#define CRM_CG_CTRL_DMA					    (BIT15)
#define CRM_CG_CTRL_GPADC                   (BIT14)
#define CRM_CG_CTRL_QDEC                    (BIT13)
#define CRM_CG_CTRL_GPIO                    (BIT12)
#define CRM_CG_CTRL_RTC                     (BIT11)
#define CRM_CG_CTRL_WDT                     (BIT10)
#define CRM_CG_CTRL_TIMER23                 (BIT9)
#define CRM_CG_CTRL_TIMER01                 (BIT8)
#define CRM_CG_CTRL_RNG                     (BIT7)  
#define CRM_CG_CTRL_SYSCFG                  (BIT6)
#define CRM_CG_CTRL_KPC                     (BIT5)
#define CRM_CG_CTRL_SPI1                    (BIT4)
#define CRM_CG_CTRL_SPI0                    (BIT3)
#define CRM_CG_CTRL_UART1                   (BIT2)
#define CRM_CG_CTRL_UART0                   (BIT1)
#define CRM_CG_CTRL_I2C                     (BIT0)

#define CRM_SOFT_RST_GLB                    (BIT24)
#define CRM_SOFT_RST_CM3                    (BIT18)
#define CRM_SOFT_RST_CRM                    (BIT17)
#define CRM_SOFT_RST_BT                     (BIT16)
#define CRM_SOFT_RST_DMA 				    (BIT15)
#define CRM_SOFT_RST_GPADC                  (BIT14)
#define CRM_SOFT_RST_QDEC                   (BIT13)
#define CRM_SOFT_RST_GPIO                   (BIT12)
#define CRM_SOFT_RST_RTC                    (BIT11)
#define CRM_SOFT_RST_WDT                    (BIT10)
#define CRM_SOFT_RST_TIMER23                (BIT9)
#define CRM_SOFT_RST_TIMER01                (BIT8)
#define CRM_SOFT_RST_RNG                    (BIT7)
#define CRM_SOFT_RST_SYSCFG                 (BIT6)
#define CRM_SOFT_RST_KPC                    (BIT5)
#define CRM_SOFT_RST_SPI1                   (BIT4)
#define CRM_SOFT_RST_SPI0                   (BIT3)
#define CRM_SOFT_RST_UART1                  (BIT2)
#define CRM_SOFT_RST_UART0                  (BIT1)
#define CRM_SOFT_RST_I2C                    (BIT0)

typedef struct
{
    __IO uint32_t CG_CTRL;
    __IO uint32_t SOFT_RST;
} crm_type_def;

typedef struct 
{
	volatile unsigned int PATSTATGEN;
	volatile unsigned int RESERVED0[7];
	volatile unsigned int BRKMSK1;
	volatile unsigned int BRKMSK2;
	volatile unsigned int RESERVED1[6];
	volatile unsigned int PATSTAT1;
	volatile unsigned int PATSTAT2;
	volatile unsigned int RESERVED2[46];
	volatile unsigned int BRKPNT[48];
	volatile unsigned int RESERVED3[208];
	volatile unsigned int PATADR;
} patch_type_def;
#define PATCH							    	((patch_type_def *)(CPU_AHB_BASE+0xA000))
#define CRM                                     ((crm_type_def    *)CRM_BASE)


/********************************************** SYSCTRL**************************************************/

#define SYSCFG_SPI_SLAVE_SEL_SPI1_SLV_SEL               (BIT1)
#define SYSCFG_SPI_SLAVE_SEL_SPI0_SLV_SEL               (BIT0)

//=======浅睡眠低功耗唤醒源==============================================
typedef enum _wakeup_mcu_type{
	 src_all_wakeup_mcu     =                  	(BIT18),
	 src_dma_wakeup_mcu     =                  	(BIT17),
	 src_qdec_wakeup_mcu    =                   (BIT16),
	 src_bt_wakeup_mcu      =                   (BIT15),
	 src_int3_wakeup_mcu    =              		(BIT14),
	 src_int2_wakeup_mcu    =             	 	(BIT13),
	 src_int1_wakeup_mcu    =             		(BIT12),
	 src_int0_wakeup_mcu    =              		(BIT11),
	 src_rtc_wakeup_mcu     =                   (BIT10),
	 src_timer3_wakeup_mcu  =                   (BIT9),
	 src_timer2_wakeup_mcu  =                   (BIT8),
	 src_timer1_wakeup_mcu  =                   (BIT7),
	 src_timer0_wakeup_mcu  =                   (BIT6),
	 src_kpc_wakeup_mcu     =                   (BIT5),
	 src_spi1_wakeup_mcu    =                   (BIT4),
	 src_spi0_wakeup_mcu    =                   (BIT3),
	 src_uart1_wakeup_mcu   =                   (BIT2),
	 src_uart0_wakeup_mcu   =                   (BIT1),
	 src_i2c_wakeup_mcu     =                   (BIT0)
}wakeup_mcu_type;



//=======深度睡眠保留内存==============================================
#define SYSCFG_SLEEP_CTRL_sram_ret_sel                  (BIT16|BIT17)


//=======深度睡眠低功耗唤醒源==========================================

typedef enum _deepsleep_wakeup{
	src_deep_sleep_ctrl_jtag               = 				(BIT12),
	src_deep_sleep_ctrl_ble_extwkupdsb     =           		(BIT11),
	src_deep_sleep_ctrl_gpio_wk_en         =           		(BIT10),
	src_deep_sleep_kpc_wk_en               =      			(BIT9),
	src_deep_sleep_rtc_wk_en               =      			(BIT8)
}deepsleep_wakeup;



//=======低功耗类型寄存器==============================================
#define SYSCFG_SLEEP_CTRL_deep_slp_sel                  (BIT0|BIT1)

typedef struct
{
    __IO uint32_t   HFCLK_SEL   ;		// 0
    __IO uint32_t   LFCLK_SEL   ;		// 4
    __IO uint32_t   FREQ_SEL    ;		// 8
    __IO uint32_t   CALIB_EN    ;		// C
    __IO uint32_t   CALIB_VAL   ;		// 10
    __IO uint32_t   CNT32K_VAL  ;		// 14
    __IO uint32_t   RESERVED0[2]    ;	// 18
    __IO uint32_t   SLEEP_CTRL  ;		// 20
    __IO uint32_t   WKUP_TYPE   ;		// 24
    __IO uint32_t   WKUP_SRC    ;		// 28
    __IO uint32_t   RESERVED1[5]    ;	// 
    __IO uint32_t   WAKE_MCU_CTRL   ;
    __IO uint32_t  	RESERVED2[3]	;
    __IO uint32_t   DMA_CH_HS;	//0x50
    __IO uint32_t  	RESERVED3[3]    ;
    __IO uint32_t   TIMER_PAUSE ;
    __IO uint32_t   SPI_SLAVE_SEL   ;
    __IO uint32_t   RESERVED4[2]    ;
    __IO uint32_t   RTC_DIV_VAL ;
    __IO uint32_t   RTC_DIV_CNT ;
    __IO uint32_t   RESERVED5[2]    ;
    __IO uint32_t   AFC[5];
    __IO uint32_t   RESERVED6[3]   ;
    __IO uint32_t   DEV_PARAM;
    __IO uint32_t   DEVTEMP_N0;
    __IO uint32_t   DEV_TEMP_N1;
    __IO uint32_t   DEV_CUR_VAL;
    __IO uint32_t   RSSI_TEM_CAL;
    __IO uint32_t   RSSI_RFGAIN_ERR1;
    __IO uint32_t   RSSI_RFGAIN_ERR2;
    __IO uint32_t   RESERVED7[1];  
    __IO uint32_t   TEST1;
    __IO uint32_t   TEST2;
    __IO uint32_t   TEST3;
    __IO uint32_t   TEST4;
    __IO uint32_t   JTAG_DIS;
    __IO uint32_t   RESET_FLAG;
}syscfg_type_def;

#define SYSCFG                                  ((syscfg_type_def *) SYSCFG_BASE)

/********************************************** GPIO **************************************************/
#define GPIO_INTP_TYPE_EN_INTP0_Pos             (0)
#define GPIO_INTP_TYPE_EN_INTP0_Mask            (0x03U<<GPIO_INTP_TYPE_EN_INTP0_Pos)

#define GPIO_INTP_TYPE_EN_INTP1_Pos             (2)
#define GPIO_INTP_TYPE_EN_INTP1_Mask            (0x03U<<GPIO_INTP_TYPE_EN_INTP1_Pos)

#define GPIO_INTP_TYPE_EN_INTP2_Pos             (4)
#define GPIO_INTP_TYPE_EN_INTP2_Mask            (0x03U<<GPIO_INTP_TYPE_EN_INTP2_Pos)

#define GPIO_INTP_TYPE_EN_INTP3_Pos             (6)
#define GPIO_INTP_TYPE_EN_INTP3_Mask            (0x03U<<GPIO_INTP_TYPE_EN_INTP3_Pos)

#define GPIO_INTP_TYPE_EN_INTP4_Pos             (8)
#define GPIO_INTP_TYPE_EN_INTP4_Mask            (0x03U<<GPIO_INTP_TYPE_EN_INTP4_Pos)

#define GPIO_INTP_TYPE_EN_INTP5_Pos             (10)
#define GPIO_INTP_TYPE_EN_INTP5_Mask            (0x03U<<GPIO_INTP_TYPE_EN_INTP5_Pos)

#define GPIO_INTP_TYPE_EN_INTP6_Pos             (12)
#define GPIO_INTP_TYPE_EN_INTP6_Mask            (0x03U<<GPIO_INTP_TYPE_EN_INTP6_Pos)

#define GPIO_INTP_TYPE_EN_INTP7_Pos             (14)
#define GPIO_INTP_TYPE_EN_INTP7_Mask            (0x03U<<GPIO_INTP_TYPE_EN_INTP7_Pos)

#define GPIO_INTP_SRC_H_INTP4_Pos               (0)
#define GPIO_INTP_SRC_H_INTP4_Mask              (0xFFU<<GPIO_INTP_SRC_H_INTP4_Pos)

#define GPIO_INTP_SRC_H_INTP5_Pos               (8)
#define GPIO_INTP_SRC_H_INTP5_Mask              (0xFFU<<GPIO_INTP_SRC_H_INTP5_Pos)

#define GPIO_INTP_SRC_H_INTP6_Pos               (16)
#define GPIO_INTP_SRC_H_INTP6_Mask              (0xFFU<<GPIO_INTP_SRC_H_INTP6_Pos)

#define GPIO_INTP_SRC_H_INTP7_Pos               (24)
#define GPIO_INTP_SRC_H_INTP7_Mask              (0xFFU<<GPIO_INTP_SRC_H_INTP7_Pos)

#define GPIO_INTP_SRC_L_INTP0_Pos               (0)
#define GPIO_INTP_SRC_L_INTP0_Mask              (0xFFU<<GPIO_INTP_SRC_L_INTP0_Pos)

#define GPIO_INTP_SRC_L_INTP1_Pos               (0)
#define GPIO_INTP_SRC_L_INTP1_Mask              (0xFFU<<GPIO_INTP_SRC_L_INTP1_Pos)

#define GPIO_INTP_SRC_L_INTP2_Pos               (0)
#define GPIO_INTP_SRC_L_INTP2_Mask              (0xFFU<<GPIO_INTP_SRC_L_INTP2_Pos)

#define GPIO_INTP_SRC_L_INTP3_Pos               (0)
#define GPIO_INTP_SRC_L_INTP3_Mask              (0xFFU<<GPIO_INTP_SRC_L_INTP3_Pos)

#define GPIO_INTP_CLR_INTP0_Pos                 (0)
#define GPIO_INTP_CLR_INTP0_Mask                (0x01U<<GPIO_INTP_CLR_INTP0_Pos)

#define GPIO_INTP_CLR_INTP1_Pos                 (1)
#define GPIO_INTP_CLR_INTP1_Mask                (0x01U<<GPIO_INTP_CLR_INTP1_Pos)

#define GPIO_INTP_CLR_INTP2_Pos                 (2)
#define GPIO_INTP_CLR_INTP2_Mask                (0x01U<<GPIO_INTP_CLR_INTP2_Pos)

#define GPIO_INTP_CLR_INTP3_Pos                 (3)
#define GPIO_INTP_CLR_INTP3_Mask                (0x01U<<GPIO_INTP_CLR_INTP3_Pos)

#define GPIO_INTP_CLR_INTP4_Pos                 (4)
#define GPIO_INTP_CLR_INTP4_Mask                (0x01U<<GPIO_INTP_CLR_INTP4_Pos)

#define GPIO_INTP_CLR_INTP5_Pos                 (5)
#define GPIO_INTP_CLR_INTP5_Mask                (0x01U<<GPIO_INTP_CLR_INTP5_Pos)

#define GPIO_INTP_CLR_INTP6_Pos                 (6)
#define GPIO_INTP_CLR_INTP6_Mask                (0x01U<<GPIO_INTP_CLR_INTP6_Pos)

#define GPIO_INTP_CLR_INTP7_Pos                 (7)
#define GPIO_INTP_CLR_INTP7_Mask                (0x01U<<GPIO_INTP_CLR_INTP7_Pos)

typedef struct
{
    __IO uint32_t IOD;
    __IO uint32_t BSR;
    __IO uint32_t CON;
} gpio_inout_type_def;

typedef struct
{
    __IO uint32_t map_mode[2];
} gpio_map_type_def;

typedef struct
{
    gpio_inout_type_def * inout_ctrl;
    gpio_map_type_def * map_ctrl;
}gpio_type_def;

typedef struct
{
    __IO uint32_t   PA_IOD;
    __IO uint32_t   PA_BSR;
    __IO uint32_t   PA_CON;
    __IO uint32_t   RESERVED0;
    __IO uint32_t   PB_IOD;
    __IO uint32_t   PB_BSR;
    __IO uint32_t   PB_CON;
    __IO uint32_t   RESERVED1;
    __IO uint32_t   PC_IOD;
    __IO uint32_t   PC_BSR;
    __IO uint32_t   PC_CON;
    __IO uint32_t   RESERVED2;
    __IO uint32_t   PD_IOD;
    __IO uint32_t   PD_BSR;
    __IO uint32_t   PD_CON;
    __IO uint32_t   RESERVED3;
    __IO uint32_t   PA_L_MODE;
    __IO uint32_t   PA_H_MODE;
    __IO uint32_t   PB_L_MODE;
    __IO uint32_t   PB_H_MODE;
    __IO uint32_t   PC_L_MODE;
    __IO uint32_t   PC_H_MODE;
    __IO uint32_t   PD_L_MODE;
    __IO uint32_t   PD_H_MODE;
    __IO uint32_t   RESERVED4[8];
    __IO uint32_t   INTP_TYPE;
    __IO uint32_t   INTP_SRC;
    __IO uint32_t   INTP_STAT;
}gpio_module_type_def;

#define GPIO_MODULE              ((gpio_module_type_def*)GPIO_BASE)
#define GPIOA_INOUT_CTRL         ((gpio_inout_type_def *)(GPIOA_INOUT_BASE))
#define GPIOB_INOUT_CTRL         ((gpio_inout_type_def *)(GPIOB_INOUT_BASE))
#define GPIOC_INOUT_CTRL         ((gpio_inout_type_def *)(GPIOC_INOUT_BASE))
#define GPIOD_INOUT_CTRL         ((gpio_inout_type_def *)(GPIOD_INOUT_BASE))
#define GPIOA_MAP_CTRL           ((gpio_map_type_def   *)(GPIOA_MAP_BASE))
#define GPIOB_MAP_CTRL           ((gpio_map_type_def   *)(GPIOB_MAP_BASE))
#define GPIOC_MAP_CTRL           ((gpio_map_type_def   *)(GPIOC_MAP_BASE))
#define GPIOD_MAP_CTRL           ((gpio_map_type_def   *)(GPIOD_MAP_BASE))

extern gpio_type_def *GPIOA;
extern gpio_type_def *GPIOB;
extern gpio_type_def *GPIOC;
extern gpio_type_def *GPIOD;

/********************************************** RTC **************************************************/
/************ bit definition for RTC  RTC_CCR REGISTER ************/
#define RTC_RTC_CCR_RTC_WEN                             (BIT3)
#define RTC_RTC_CCR_RTC_EN                              (BIT2)
#define RTC_RTC_CCR_RTC_Mask                            (BIT1)
#define RTC_RTC_CCR_RTC_ien                             (BIT0)

typedef struct{
    __IO uint32_t       RTC_CCVR;
    __IO uint32_t       RTC_CMR;
    __IO uint32_t       RTC_CLR;
    __IO uint32_t       RTC_CCR;
    __IO uint32_t       RTC_STAT;
    __IO uint32_t       RTC_RSTAT;
    __IO uint32_t       RTC_EOI;
    __IO uint32_t       RTC_COMP_VERSION;
} rtc_type_def;
#define RTC                                     ((rtc_type_def *)(RTC_BASE))

/********************************************** DMA **************************************************/


typedef struct
{
    __IO uint32_t SAR_L;
    __IO uint32_t SAR_H;
    __IO uint32_t DAR_L;
    __IO uint32_t DAR_H;
    __IO uint32_t LLP_L;
    __IO uint32_t LLP_H;
    __IO uint32_t CTL_L;
    __IO uint32_t CTL_H;
    __IO uint32_t SSTAT_L;
    __IO uint32_t SSTAT_H;
    __IO uint32_t DSTAT_L;
    __IO uint32_t DSTAT_H;
    __IO uint32_t SSTATAR_L;
    __IO uint32_t SSTATAR_H;
    __IO uint32_t DSTATAR_L;
    __IO uint32_t DSTATAR_H;
    __IO uint32_t CFG_L;
    __IO uint32_t CFG_H;
    __IO uint32_t SGR_L;
    __IO uint32_t SGR_H;
    __IO uint32_t DSR_L;
    __IO uint32_t DSR_H;
} dma_type_def;

#define DMA_CHANNEL_NUM     4
typedef struct
{
    dma_type_def DMA_Channel[DMA_CHANNEL_NUM];
    __IO uint32_t RESERVEDChannel[88];
    
    __I  uint32_t RawTfr_L;
    __I  uint32_t RawTfr_H;
    __I  uint32_t RawBlock_L;
    __I  uint32_t RawBlock_H;
    __I  uint32_t RawSrcTran_L;
    __I  uint32_t RawSrcTran_H;
    __I  uint32_t RawDstTran_L;
    __I  uint32_t RawDstTran_H;
    __I  uint32_t RawErr_L;
    __I  uint32_t RawErr_H;
    
    __I  uint32_t StatusTfr_L;
    __I  uint32_t StatusTfr_H;
    __I  uint32_t StatusBlock_L;
    __I  uint32_t StatusBlock_H;
    __I  uint32_t StatusSrcTran_L;
    __I  uint32_t StatusSrcTran_H;
    __I  uint32_t StatusDstTran_L;
    __I  uint32_t StatusDstTran_H;
    __I  uint32_t StatusErr_L;
    __I  uint32_t StatusErr_H;

    __IO uint32_t MaskTfr_L;
    __IO uint32_t MaskTfr_H;
    __IO uint32_t MaskBlock_L;
    __IO uint32_t MaskBlock_H;
    __IO uint32_t MaskSrcTran_L;
    __IO uint32_t MaskSrcTran_H;
    __IO uint32_t MaskDstTran_L;
    __IO uint32_t MaskDstTran_H;
    __IO uint32_t MaskErr_L;
    __IO uint32_t MaskErr_H;
    
    __O  uint32_t ClearTfr_L;
    __O  uint32_t ClearTfr_H;
    __O  uint32_t ClearBlock_L;
    __O  uint32_t ClearBlock_H;
    __O  uint32_t ClearSrcTran_L;
    __O  uint32_t ClearSrcTran_H;
    __O  uint32_t ClearDstTran_L;
    __O  uint32_t ClearDstTran_H;
    __O  uint32_t ClearErr_L;
    __O  uint32_t ClearErr_H;
    
    __I  uint32_t StatusInt_L;
    __I  uint32_t StatusInt_H;
    
    __IO uint32_t ReqSrcReg_L;
    __IO uint32_t ReqSrcReg_H;
    __IO uint32_t ReqDstReg_L;
    __IO uint32_t ReqDstReg_H;
    __IO uint32_t SglReqSrcReg_L;
    __IO uint32_t SglReqSrcReg_H;
    __IO uint32_t SglReqDstReg_L;
    __IO uint32_t SglReqDstReg_H;
    __IO uint32_t LstSrcReg_L;
    __IO uint32_t LstSrcReg_H;
    __IO uint32_t LstDstReg_L;
    __IO uint32_t LstDstReg_H;
    
    __IO uint32_t DmaCfgReg_L;
    __IO uint32_t DmaCfgReg_H;
    __IO uint32_t ChEnReg_L;
    __IO uint32_t ChEnReg_H;
    __I  uint32_t DmaIdReg_L;
    __I  uint32_t DmaIdReg_H;
    __IO uint32_t DmaTestReg_L;
    __IO uint32_t DmaTestReg_H;
    
    __IO uint32_t RESERVED2[4];
    
    __I  uint32_t DMA_COMP_PARAMS_6_L;
    __I  uint32_t DMA_COMP_PARAMS_6_H;
    __I  uint32_t DMA_COMP_PARAMS_5_L;
    __I  uint32_t DMA_COMP_PARAMS_5_H;
    __I  uint32_t DMA_COMP_PARAMS_4_L;
    __I  uint32_t DMA_COMP_PARAMS_4_H;
    __I  uint32_t DMA_COMP_PARAMS_3_L;
    __I  uint32_t DMA_COMP_PARAMS_3_H;
    __I  uint32_t DMA_COMP_PARAMS_2_L;
    __I  uint32_t DMA_COMP_PARAMS_2_H;
    __I  uint32_t DMA_COMP_PARAMS_1_L;
    __I  uint32_t DMA_COMP_PARAMS_1_H;
    __I  uint32_t DMA_Component_ID_Register_L;
    __I  uint32_t DMA_Component_ID_Register_H;
} dma_module_type_def;

#define DMA                     ((dma_module_type_def *)DMA_BASE)
#define DMA_Channel_0           ((dma_type_def *)DMA_BASE)
#define DMA_Channel_1           ((dma_type_def *)(DMA_BASE + 0x58))
#define DMA_Channel_2           ((dma_type_def *)(DMA_BASE + 0x58*2))
#define DMA_Channel_3           ((dma_type_def *)(DMA_BASE + 0x58*3))

/********************************************** WDT **************************************************/

#define WDT_WDT_CR_WDT_EN           (BIT0)
#define WDT_WDT_CR_RMOD             (BIT1)

#define WDT_WDT_STATE           (BIT0)

typedef struct
{
    __IO uint32_t WDT_CR;
    __IO uint32_t RESERVED0;
    __I  uint32_t WDT_CCVR;
    __O  uint32_t WDT_CRR;
    __I  uint32_t WDT_STAT;
    __I  uint32_t WDT_EOI;  
    __I  uint32_t RESERVED1;
    __IO uint32_t WDT_RLD;
    __I  uint32_t RESERVED[53];
    __I  uint32_t WDT_COMP_PARAMS_1;
    __I  uint32_t WDT_COMP_VERSION;
    __I  uint32_t WDT_COMP_TYPE;
} wdt_type_def;
#define WDT                                     ((wdt_type_def    *) WATCHDOG_BASE)

/********************************************** CRM **************************************************/
/************ bit definition for TIMER CONTROL_REG REGISTER ************/
#define TIMER_CONTROL_REG_TIMER_ENABLE_Pos                              (0)
#define TIMER_CONTROL_REG_TIMER_ENABLE_Mask                             (0x01U<<TIMER_CONTROL_REG_TIMER_ENABLE_Pos) 

#define TIMER_CONTROL_REG_TIMER_MODE_Pos                                (1)
#define TIMER_CONTROL_REG_TIMER_MODE_Mask                               (0x01U<<TIMER_CONTROL_REG_TIMER_MODE_Pos) //1 fixed, timed interrupt;0 

#define TIMER_CONTROL_REG_TIMER_INTERRUPT_MASK_Pos              (2)
#define TIMER_CONTROL_REG_TIMER_INTERRUPT_MASK_Mask             (0x01U<<TIMER_CONTROL_REG_TIMER_INTERRUPT_MASK_Pos) 

/************ bit definition for TIMER CONTROL_REG REGISTER ************/
#define TIMER_INT_STATUS_INTSTATUS_Pos                              (0)
#define TIMER_INT_STATUS_INTSTATUS_Mask                             (0x01U<<TIMER_INT_STATUS_INTSTATUS_Pos) 

typedef struct
{
    __IO uint32_t LoadCount;
    __I  uint32_t CurrentValue;
    __IO uint32_t ControlReg;
    __I  uint32_t EOI;
    __I  uint32_t IntStatus;
} timer_type_def;

typedef struct
{
    __IO uint32_t Timer1LoadCount;
    __I  uint32_t Timer1CurrentValue;
    __IO uint32_t Timer1ControlReg;
    __I  uint32_t Timer1EOI;
    __I  uint32_t Timer1IntStatus;
    __IO uint32_t Timer2LoadCount;
    __I  uint32_t Timer2CurrentValue;
    __IO uint32_t Timer2ControlReg;
    __I  uint32_t Timer2EOI;
    __I  uint32_t Timer2IntStatus;
    __I  uint32_t RESERVED[30];
    __I  uint32_t TimersIntStatus;
    __I  uint32_t TimersEOI;
    __I  uint32_t TimersRawIntStatus;
    __I  uint32_t TIMERS_COMP;
    __IO uint32_t Timer1LoadCount2;
    __IO uint32_t Timer2LoadCount2;
} timer_module_type_def;

#define TIMER0_1                            ((timer_module_type_def *) TIMER01_BASE)
#define TIMER2_3                            ((timer_module_type_def *) TIMER23_BASE)

#define TIMER0_M                            ((timer_module_type_def *) TIMER01_BASE)
#define TIMER0                              ((timer_type_def        *) TIMER01_BASE)
#define TIMER1                              ((timer_type_def        *) (TIMER01_BASE + 0x14))
#define TIMER1_M                            ((timer_module_type_def *) TIMER23_BASE)
#define TIMER2                              ((timer_type_def        *) TIMER23_BASE)
#define TIMER3                              ((timer_type_def        *) (TIMER23_BASE + 0x14))

/********************************************** UART **************************************************/

#define UART_LCR_DLAB                               (BIT7)
#define UART_LSR_DR                                 (BIT0)
#define UART_LSR_TEMT                               (BIT6)
#define UART_SFE_SHADOW_FIFO_ENABLE                 (BIT0)
#define UART_MCR_DTR                                (BIT0)
#define UART_MCR_RTS                                (BIT1)
#define UART_MCR_AFCE                               (BIT5)
#define UART_USR_TFNF                               (BIT1)

typedef struct
{
    union
    {
        __I     uint32_t    RBR; // LCR[7] bit = 0;
        __O     uint32_t    THR; // LCR[7] bit = 0;
        __IO    uint32_t    DLL; // LCR[7] bit = 1;
    }SEL0;
    union
    {
        __IO    uint32_t    DLH; // LCR[7] bit = 0;
        __IO    uint32_t    IER; // LCR[7] bit = 1;
    }SEL1;
    union
    {
        __I uint32_t    IIR;
        __O uint32_t    FCR;
    }SEL2;
    __IO    uint32_t    LCR;
    __IO    uint32_t    MCR;
    __I     uint32_t    LSR;
    __I     uint32_t    MSR;
    __IO    uint32_t    SCR;
    __IO    uint32_t    LPDLL;
    __IO    uint32_t    LPDLH;
    uint32_t    RESERVED0[2];
    union
    {
        __I uint32_t    SRBR[16];
        __O uint32_t    STHR[16];
    }SEL3;
    __IO    uint32_t    FAR;
    __I     uint32_t    TFR;
    __O     uint32_t    RFW;
    __I     uint32_t    USR;
    __I     uint32_t    TFL;
    __I     uint32_t    RFL;
    __O     uint32_t    SRR;
    __IO    uint32_t    SRTS;
    __IO    uint32_t    SBCR;
    __IO    uint32_t    SDMAM;
    __IO    uint32_t    SFE;
    __IO    uint32_t    SRT;
    __IO    uint32_t    STET;
    __IO    uint32_t    HTX;
    __O     uint32_t    DMASA;
    __I     uint32_t    RESERVED1[18];
    __I     uint32_t    CPR;
    __I     uint32_t    UCV;
    __I     uint32_t    CTR;
} uart_typedef_t;
#define UART0                                   ((uart_typedef_t   *) UART0_BASE)
#define UART1                                   ((uart_typedef_t   *) UART1_BASE)

/********************************************** SPI **************************************************/
#define SPI_SR_RFNE         (BIT3)  
#define SPI_SR_TFE          (BIT2)

typedef struct
{
    __IO uint16_t CTRLR0;
    uint16_t RESERVED0;
    __IO uint16_t CTRLR1;
    uint16_t RESERVED1;
    __IO uint32_t SSIENR;
    __IO uint32_t MWCR;
    __IO uint32_t SER;
    __IO uint32_t BAUDR;
    __IO uint32_t TXFTLR;
    __IO uint32_t RXFTLR;
    __IO uint32_t TXFLR;
    __I  uint32_t RXFLR;
    __I  uint32_t SR;
    __IO uint32_t IMR;
    __I  uint32_t ISR;
    __I  uint32_t RISR;
    __I  uint32_t TXOICR;
    __I  uint32_t RXOICR;
    __I  uint32_t RXUICR;
    __I  uint32_t MSTICR;
    __I  uint32_t ICR;
    __IO uint32_t DMACR;
    __IO uint32_t DMATDLR;
    __IO uint32_t DMARDLR;
    __I  uint32_t IDR;
    __I  uint32_t SSI_COMP_VERSION;
    __IO uint32_t DR;
    __IO uint32_t DR_Array[35];
    __IO uint32_t RX_SAMPLE_DLY;    
} spi_type_def;
#define SPI0                                    ((spi_type_def    *) SPI0_BASE)
#define SPI1                                    ((spi_type_def    *) SPI1_BASE)

/*******************  Bit definition for IC_CON register  *********************/
#define I2C_IC_CON_MASTER_MODE					((uint32_t)0x0001)
#define I2C_IC_CON_SPEED						((uint32_t)0x0006)
#define I2C_IC_CON_SPEED_0						((uint32_t)0x0002)
#define I2C_IC_CON_SPEED_1						((uint32_t)0x0004)
#define I2C_IC_CON_10BITADDR_SLAVE				((uint32_t)0x0008)
#define I2C_IC_CON_10BITADDR_MASTER				((uint32_t)0x0010)
#define I2C_IC_CON_RESTART_EN					((uint32_t)0x0020)
#define I2C_IC_CON_SLAVE_DISABLE				((uint32_t)0x0040)

/*******************  Bit definition for IC_TAR register  *********************/
#define I2C_IC_TAR_TAR							((uint32_t)0x03FF)
#define I2C_IC_TAR_GC_OR_START					((uint32_t)0x0400)
#define I2C_IC_TAR_SPECIAL						((uint32_t)0x0800)
#define I2C_IC_TAR_10BITADDR_MASTER				((uint32_t)0x1000)

/*******************  Bit definition for IC_SAR register  *********************/
#define I2C_IC_SAR_SAR							((uint32_t)0x03FF)

/*******************  Bit definition for IC_HS_MADDR register  ****************/
#define I2C_IC_HS_MADDR_MAR						((uint32_t)0x0007)
#define I2C_IC_HS_MADDR_MAR_0					((uint32_t)0x0001)
#define I2C_IC_HS_MADDR_MAR_1					((uint32_t)0x0002)
#define I2C_IC_HS_MADDR_MAR_2					((uint32_t)0x0004)

/*******************  Bit definition for IC_DATA_CMD register  ****************/
#define I2C_IC_DATA_CMD_DAT						((uint32_t)0x00FF)
#define I2C_IC_DATA_CMD_CMD						((uint32_t)0x0100)
#define I2C_IC_DATA_CMD_STOP					((uint32_t)0x0200)
#define I2C_IC_DATA_CMD_RESTART					((uint32_t)0x0400)

/*******************  Bit definition for IC_SS_SCL_HCNT register  *************/
#define I2C_IC_SS_SCL_HCNT_HCNT						((uint32_t)0xFFFF)

/*******************  Bit definition for IC_SS_SCL_LCNT register  *************/
#define I2C_IC_SS_SCL_LCNT_LCNT						((uint32_t)0xFFFF)

/*******************  Bit definition for IC_FS_SCL_HCNT register  *************/
#define I2C_IC_FS_SCL_HCNT_HCNT						((uint32_t)0xFFFF)

/*******************  Bit definition for IC_FS_SCL_LCNT register  *************/
#define I2C_IC_FS_SCL_LCNT_LCNT						((uint32_t)0xFFFF)

/*******************  Bit definition for IC_HS_SCL_HCNT register  *************/
#define I2C_IC_HS_SCL_HCNT_HCNT						((uint32_t)0xFFFF)

/*******************  Bit definition for IC_HS_SCL_LCNT register  *************/
#define I2C_IC_HS_SCL_LCNT_LCNT						((uint32_t)0xFFFF)

/*******************  Bit definition for IC_INTR_STAT register  ***************/
#define I2C_IC_INTR_STAT_R_RX_UNDER					((uint32_t)0x0001)
#define I2C_IC_INTR_STAT_R_RX_OVER					((uint32_t)0x0002)
#define I2C_IC_INTR_STAT_R_RX_FULL					((uint32_t)0x0004)
#define I2C_IC_INTR_STAT_R_TX_OVER					((uint32_t)0x0008)
#define I2C_IC_INTR_STAT_R_TX_EMPTY					((uint32_t)0x0010)
#define I2C_IC_INTR_STAT_R_RD_REQ					((uint32_t)0x0020)
#define I2C_IC_INTR_STAT_R_TX_ABRT					((uint32_t)0x0040)
#define I2C_IC_INTR_STAT_R_RX_DONE					((uint32_t)0x0080)
#define I2C_IC_INTR_STAT_R_ACTIVITY					((uint32_t)0x0100)
#define I2C_IC_INTR_STAT_R_STOP_DET					((uint32_t)0x0200)
#define I2C_IC_INTR_STAT_R_START_DET				((uint32_t)0x0400)
#define I2C_IC_INTR_STAT_R_GEN_CALL					((uint32_t)0x0800)

/*******************  Bit definition for IC_INTR_MASK register  ***************/
#define I2C_IC_INTR_MASK_M_RX_UNDER					((uint32_t)0x0001)
#define I2C_IC_INTR_MASK_M_RX_OVER					((uint32_t)0x0002)
#define I2C_IC_INTR_MASK_M_RX_FULL					((uint32_t)0x0004)
#define I2C_IC_INTR_MASK_M_TX_OVER					((uint32_t)0x0008)
#define I2C_IC_INTR_MASK_M_TX_EMPTY					((uint32_t)0x0010)
#define I2C_IC_INTR_MASK_M_RD_REQ					((uint32_t)0x0020)
#define I2C_IC_INTR_MASK_M_TX_ABRT					((uint32_t)0x0040)
#define I2C_IC_INTR_MASK_M_RX_DONE					((uint32_t)0x0080)
#define I2C_IC_INTR_MASK_M_ACTIVITY					((uint32_t)0x0100)
#define I2C_IC_INTR_MASK_M_STOP_DET					((uint32_t)0x0200)
#define I2C_IC_INTR_MASK_M_START_DET				((uint32_t)0x0400)
#define I2C_IC_INTR_MASK_M_GEN_CALL					((uint32_t)0x0800)

/*******************  Bit definition for IC_RAW_INTR_STAT register  ***********/
#define I2C_IC_RAW_INTR_STAT_RX_UNDER				((uint32_t)0x0001)
#define I2C_IC_RAW_INTR_STAT_RX_OVER				((uint32_t)0x0002)
#define I2C_IC_RAW_INTR_STAT_RX_FULL				((uint32_t)0x0004)
#define I2C_IC_RAW_INTR_STAT_TX_OVER				((uint32_t)0x0008)
#define I2C_IC_RAW_INTR_STAT_TX_EMPTY				((uint32_t)0x0010)
#define I2C_IC_RAW_INTR_STAT_RD_REQ					((uint32_t)0x0020)
#define I2C_IC_RAW_INTR_STAT_TX_ABRT				((uint32_t)0x0040)
#define I2C_IC_RAW_INTR_STAT_RX_DONE				((uint32_t)0x0080)
#define I2C_IC_RAW_INTR_STAT_ACTIVITY				((uint32_t)0x0100)
#define I2C_IC_RAW_INTR_STAT_STOP_DET				((uint32_t)0x0200)
#define I2C_IC_RAW_INTR_STAT_START_DET				((uint32_t)0x0400)
#define I2C_IC_RAW_INTR_STAT_GEN_CALL				((uint32_t)0x0800)

/*******************  Bit definition for IC_RX_TL register  *******************/
#define I2C_IC_RX_TL_TL								((uint32_t)0x00FF)

/*******************  Bit definition for IC_TX_TL register  *******************/
#define I2C_IC_TX_TL_TL								((uint32_t)0x00FF)

/*******************  Bit definition for IC_CLR_INTR register  ****************/
#define I2C_IC_CLR_INTR								((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_RX_UNDER register  ************/
#define I2C_IC_CLR_RX_UNDER							((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_RX_OVER register  *************/
#define I2C_IC_CLR_RX_OVER							((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_TX_OVER register  *************/
#define I2C_IC_CLR_TX_OVER							((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_RD_REQ register  **************/
#define I2C_IC_CLR_RD_REQ							((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_TX_ABRT register  *************/
#define I2C_IC_CLR_TX_ABRT							((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_RX_DONE register  *************/
#define I2C_IC_CLR_RX_DONE							((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_ACTIVITY register  ************/
#define I2C_IC_CLR_ACTIVITY							((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_STOP_DET register  ************/
#define I2C_IC_CLR_STOP_DET							((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_START_DET register  ***********/
#define I2C_IC_CLR_START_DET						((uint32_t)0x0001)

/*******************  Bit definition for IC_CLR_GEN_CALL register  ************/
#define I2C_IC_CLR_GEN_CALL							((uint32_t)0x0001)

/*******************  Bit definition for IC_ENABLE  register  *****************/
#define I2C_IC_ENABLE_ENABLE 						((uint32_t)0x0001)
#define I2C_IC_ENABLE_ABORT 						((uint32_t)0x0002)

/*******************  Bit definition for IC_STATUS  register  *****************/
#define I2C_IC_STATUS_ACTIVITY						((uint32_t)0x0001)
#define I2C_IC_STATUS_TFNF							((uint32_t)0x0002)
#define I2C_IC_STATUS_TFE							((uint32_t)0x0004)
#define I2C_IC_STATUS_RFNE							((uint32_t)0x0008)
#define I2C_IC_STATUS_RFF							((uint32_t)0x0010)
#define I2C_IC_STATUS_MST_ACTIVITY					((uint32_t)0x0020)
#define I2C_IC_STATUS_SLV_ACTIVITY					((uint32_t)0x0040)
/*******************  Bit definition for IC_TXFLR  register  ******************/
#define I2C_IC_TXFLR_TXFLR							(8)

/*******************  Bit definition for IC_RXFLR  register  ******************/
#define I2C_IC_RXFLR_RXFLR							(8)

/*******************  Bit definition for IC_SDA_HOLD  register  ***************/
#define I2C_IC_SDA_HOLD								((uint32_t)0xFFFF)

/*******************  Bit definition for IC_TX_ABRT_SOURCE  register  *********/
#define I2C_IC_TX_ABRT_SOURCE_7B_ADDR_NOACK			((uint32_t)0x00000001)
#define I2C_IC_TX_ABRT_SOURCE_10ADDR1_NOACK			((uint32_t)0x00000002)
#define I2C_IC_TX_ABRT_SOURCE_10ADDR2_NOACK			((uint32_t)0x00000004)
#define I2C_IC_TX_ABRT_SOURCE_TXDATA_NOACK			((uint32_t)0x00000008)
#define I2C_IC_TX_ABRT_SOURCE_GCALL_NOACK			((uint32_t)0x00000010)
#define I2C_IC_TX_ABRT_SOURCE_GCALL_READ			((uint32_t)0x00000020)
#define I2C_IC_TX_ABRT_SOURCE_HS_ACKDET				((uint32_t)0x00000040)
#define I2C_IC_TX_ABRT_SOURCE_SBYTE_ACKDET			((uint32_t)0x00000080)
#define I2C_IC_TX_ABRT_SOURCE_HS_NORSTRT			((uint32_t)0x00000100)
#define I2C_IC_TX_ABRT_SOURCE_SBYTE_NORSTRT			((uint32_t)0x00000200)
#define I2C_IC_TX_ABRT_SOURCE_10B_RD_NORSTRT		((uint32_t)0x00000400)
#define I2C_IC_TX_ABRT_SOURCE_MASTER_DIS			((uint32_t)0x00000800)
#define I2C_IC_TX_ABRT_SOURCE_LOST					((uint32_t)0x00001000)
#define I2C_IC_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO		((uint32_t)0x00002000)
#define I2C_IC_TX_ABRT_SOURCE_SLV_ARBLOST			((uint32_t)0x00004000)
#define I2C_IC_TX_ABRT_SOURCE_SLVRD_INTX			((uint32_t)0x00008000)
#define I2C_IC_TX_ABRT_SOURCE_USER_ABRT				((uint32_t)0x00010000)
#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT			((uint32_t)0xFF000000)

/*******************  Bit definition for IC_SLV_DATA_NACK_ONLY  register  *****/
#define I2C_IC_SLV_DATA_NACK_ONLY					((uint32_t)0x0001)

/*******************  Bit definition for IC_DMA_TDLR  register  ***************/
#define I2C_IC_DMA_TDLR_TDLR						((uint32_t)0x000F)

/*******************  Bit definition for IC_DMA_RDLR  register  ***************/
#define I2C_IC_DMA_TDLR_TDLR						((uint32_t)0x000F)

/*******************  Bit definition for IC_SDA_SETUP  register  **************/
#define I2C_IC_SDA_SETUP							((uint32_t)0x00FF)

/*******************  Bit definition for IC_ACK_GENERAL_CALL  register  *******/
#define I2C_IC_ACK_GENERAL_CALL						((uint32_t)0x0001)

/*******************  Bit definition for IC_ENABLE_STATUS  register  **********/
#define I2C_IC_ENABLE_STATUS_IC_EN					((uint32_t)0x0001)
#define I2C_IC_ENABLE_STATUS_SLV_RX_ABORTED			((uint32_t)0x0001)
#define I2C_IC_ENABLE_STATUS_SLV_FIFO_FILLED_AND_FLUSHED		((uint32_t)0x0001)

/*******************  Bit definition for IC_FS_SPKLEN  register  **************/
#define I2C_IC_FS_SPKLEN_SPKLEN						((uint32_t)0x00FF)

/*******************  Bit definition for IC_HS_SPKLEN  register  **************/
#define I2C_IC_HS_SPKLEN_SPKLEN						((uint32_t)0x00FF)

/*******************  Bit definition for IC_COMP_PARAM_1  register  ***********/
#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH			((uint32_t)0x0003)
#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_0		((uint32_t)0x0001)
#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_1		((uint32_t)0x0002)
#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE			((uint32_t)0x000C)
#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_0		((uint32_t)0x0004)
#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_1		((uint32_t)0x0008)
#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES			((uint32_t)0x0010)
#define I2C_IC_COMP_PARAM_1_INTR_IO					((uint32_t)0x0020)
#define I2C_IC_COMP_PARAM_1_HAS_DMA					((uint32_t)0x0040)
#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS		((uint32_t)0x0080)
#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH			((uint32_t)0x0000FF)
#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH			((uint32_t)0x00FF00)

/*******************  Bit definition for IC_COMP_VERSION  register  ***********/
#define I2C_IC_COMP_VERSION							((uint32_t)0xFFFFFFFF)

/*******************  Bit definition for IC_COMP_TYPE  register  **************/
#define I2C_IC_COMP_TYPE							((uint32_t)0xFFFFFFFF)

typedef struct
{
    __IO uint32_t IC_CON;
    __IO uint32_t IC_TAR;
    __IO uint32_t IC_SAR;
    __IO uint32_t IC_HS_MADDR;
    __IO uint32_t IC_DATA_CMD;
    __IO uint32_t IC_SS_SCL_HCNT;
    __IO uint32_t IC_SS_SCL_LCNT;
    __IO uint32_t IC_FS_SCL_HCNT;
    __IO uint32_t IC_FS_SCL_LCNT;
    __IO uint32_t IC_HS_SCL_HCNT;
    __IO uint32_t IC_HS_SCL_LCNT;
    __I  uint32_t IC_INTR_STAT;
    __IO uint32_t IC_INTR_MASK;
    __I  uint32_t IC_RAW_INTR_STAT;
    __IO uint32_t IC_RX_TL;
    __IO uint32_t IC_TX_TL;
    __I  uint32_t IC_CLR_INTR;
    __I  uint32_t IC_CLR_RX_UNDER;
    __I  uint32_t IC_CLR_RX_OVER;
    __I  uint32_t IC_CLR_TX_OVER;
    __I  uint32_t IC_CLR_RD_REQ;
    __I  uint32_t IC_CLR_TX_ABRT;
    __I  uint32_t IC_CLR_RX_DONE;
    __I  uint32_t IC_CLR_ACTIVITY;
    __I  uint32_t IC_CLR_STOP_DET;
    __I  uint32_t IC_CLR_START_DET;
    __I  uint32_t IC_CLR_GEN_CALL;
    __IO uint32_t IC_ENABLE;
    __I  uint32_t IC_STATUS;
    __I  uint32_t IC_TXFLR;
    __I  uint32_t IC_RXFLR;
    __IO uint32_t IC_SDA_HOLD;
    __I  uint32_t IC_TX_ABRT_SOURCE;
    __IO uint32_t IC_SLV_DATA_NACK_ONLY;
    __IO uint32_t IC_DMA_CR;
    __IO uint32_t IC_DMA_TDLR;
    __IO uint32_t IC_DMA_RDLR;
    __IO uint32_t IC_SDA_SETUP;
    __IO uint32_t IC_ACK_GENERAL_CALL;
    __I  uint32_t IC_ENABLE_STATUS;
    __IO uint32_t IC_FS_SPKLEN;
    __IO uint32_t IC_HS_SPKLEN; 
} i2c_type_def;
#define I2C                                     ((i2c_type_def *)I2C_BASE)


/********************************************** KEYBOARD **********************************************/
typedef struct
{
	__IO uint32_t kpc_ctrl;
	__IO uint32_t kpc_cfg1;
	__IO uint32_t kpc_cfg2;
	__IO  uint32_t kpc_stat;	
	__IO uint32_t kpc_int_ctrl;
	__I  uint32_t kpc_data;	
} kcu_type_def;
#define KEYBOARD		((kcu_type_def *)KEYBOARD_BASE)


/********************************************** QDEC **************************************************/

typedef struct
{
    __IO uint32_t QCR;
    __IO uint32_t QSR;
    __IO uint32_t QIR;
    __IO int32_t QRW;
    __IO uint32_t QCK;
} qdec_type_def;
#define QDEC                                    ((qdec_type_def *)QDEC_BASE)

/********************************************** GPADC **************************************************/
typedef struct
{
    __IO uint32_t GPADC_CONF;
    __IO uint32_t GPADC_CTRL;
    __I  uint32_t GPADC_FIFOLEVEL;
    __IO uint32_t GPADC_THRESHOLD;
    __O  uint32_t GPADC_FIFOFLUSH;
    __I  uint32_t GPADC_FIFODATA;
    __IO uint32_t GPADC_STAT;
    __IO uint32_t GPADC_INT_CTRL;
    __I  uint32_t GPADC_DATA;
    __IO uint32_t DMA_CR;
    __IO uint32_t DMA_RDLR;
} gpadc_type_def;

#define GPADC_BASE                          (CPU_APB0_BASE + 0xF000)
#define GPADC                               ((gpadc_type_def *)GPADC_BASE)

/********************************************** QUADDEC **************************************************/
#define QDEC_QCR_INRC               (BIT9)              
#define QDEC_QCR_IDXL               (BIT8)        
#define QDEC_QCR_ICHB               (BIT7)        
#define QDEC_QCR_ICHA               (BIT6)        
#define QDEC_QCR_QLAT               (BIT5)        
#define QDEC_QCR_PLCT               (BIT4)        
#define QDEC_QCR_INZC               (BIT3)        
#define QDEC_QCR_INEN               (BIT2)        
#define QDEC_QCR_CTDR               (BIT1)        
#define QDEC_QCR_ECNT               (BIT0)        

#define QDEC_QSR_CMI                (BIT4)
#define QDEC_QSR_INI                (BIT3)
#define QDEC_QSR_UNI                (BIT2)
#define QDEC_QSR_OVI                (BIT1)
#define QDEC_QSR_QEI                (BIT0)

#define QDEC_QIR_CMIE               (BIT4)
#define QDEC_QIR_INIE               (BIT3)
#define QDEC_QIR_UNIE               (BIT2)
#define QDEC_QIR_OVIE               (BIT1)
#define QDEC_QIR_QEIE               (BIT0)

#define QDEC_QCK_QCK_Mask           (0x1FU)

/********************************************** KEYBOARD **************************************************/

typedef struct
{
    __IO uint32_t kpc_ctrl;
    __IO uint32_t kpc_cfg1;
    __IO uint32_t kpc_cfg2;
    __IO uint32_t kpc_stat;
    __IO uint32_t kpc_int_ctrl;
    __I  uint32_t kpc_data;
} kpc_type_def;

/********************************************** BLE MODLUE **************************************************/

typedef struct
{
    __IO uint32_t   BTLECNTL  ;
    __IO uint32_t   VERSION ;
    __IO uint32_t   BLECONF   ;
    __IO uint32_t   INTCNTL ;
    __IO uint32_t   INTSTAT ;
    __IO uint32_t   INTRAWSTAT  ;
    __IO uint32_t   INTACK  ;
    __IO uint32_t   BASETIMECNT ;
    __IO uint32_t   FINETIMECNT ;
    __IO uint32_t   BDADDRL ;
    __IO uint32_t   BDADDRU ;
    __IO uint32_t   CURRENTRXDESCPTR    ;
    __IO uint32_t   DEEPSLCNTL  ;
    __IO uint32_t   DEEPSLWKUP  ;
    __IO uint32_t   DEEPSLSTAT  ;
    __IO uint32_t   ENBPRESET   ;
    __IO uint32_t   FINECNTCORR ;
    __IO uint32_t   BASETIMECNTCORR ;
    __IO uint32_t   reg_4_18    ;
    __IO uint32_t   reg_4_19    ;
    __IO uint32_t   DIAGCNTL    ;
    __IO uint32_t   DIAGSTAT    ;
    __IO uint32_t   DEBUGADDMAX ;
    __IO uint32_t   DEBUGADDMIN ;
    __IO uint32_t   ERRORTYPESTAT   ;
    __IO uint32_t   SWPROFILING ;
    __IO uint32_t   reg_4_26    ;
    __IO uint32_t   reg_4_27    ;
    __IO uint32_t   RADIOCNTL0  ;
    __IO uint32_t   RADIOCNTL1  ;
    __IO uint32_t   RADIOCNTL2  ;
    __IO uint32_t   RADIOCNTL3  ;
    __IO uint32_t   RADIOPWRUPDN    ;
    __IO uint32_t   SPIPTRCNTL0 ;
    __IO uint32_t   SPIPTRCNTL1 ;
    __IO uint32_t   SPIPTRCNTL2 ;
    __IO uint32_t   ADVCHMAP    ;
    __IO uint32_t   reg_4_37    ;
    __IO uint32_t   reg_4_38    ;
    __IO uint32_t   reg_4_39    ;
    __IO uint32_t   ADVTIM  ;
    __IO uint32_t   ACTSCANSTAT ;
    __IO uint32_t   reg_4_42    ;
    __IO uint32_t   reg_4_43    ;
    __IO uint32_t   WLPUBADDPTR ;
    __IO uint32_t   WLPRIVADDPTR    ;
    __IO uint32_t   WLNBDEV ;
    __IO uint32_t   reg_4_47    ;
    __IO uint32_t   AESCNTL ;
    __IO uint32_t   AESKEY31_0  ;
    __IO uint32_t   AESKEY63_32 ;
    __IO uint32_t   AESKEY95_64 ;
    __IO uint32_t   AESKEY127_96    ;
    __IO uint32_t   AESPTR  ;
    __IO uint32_t   TXMICVAL    ;
    __IO uint32_t   RXMICVAL    ;
    __IO uint32_t   RFTESTCNTL  ;
    __IO uint32_t   RFTESTTXSTAT    ;
    __IO uint32_t   RFTESTRXSTAT    ;
    __IO uint32_t   reg_4_59    ;
    __IO uint32_t   TIMGENCNTL  ;
    __IO uint32_t   GROSSTIMTGT ;
    __IO uint32_t   FINETIMTGT  ;
    __IO uint32_t   reg_4_fc    ;
    __IO uint32_t   COEXIFCNTL0 ;
    __IO uint32_t   COEXIFCNTL1 ;
    __IO uint32_t   COEXIFCNTL2 ;
    __IO uint32_t   BLEMPRIO0   ;
    __IO uint32_t   BLEMPRIO1   ;
    __IO uint32_t   reg_4_114   ;
    __IO uint32_t   reg_4_118   ;
    __IO uint32_t   reg_4_11c   ;
    __IO uint32_t   RALPTR  ;
    __IO uint32_t   RALNBDEV    ;
    __IO uint32_t   RAL_LOCAL_RND   ;
    __IO uint32_t   RAL_PEER_RND    ;
    __IO uint32_t   BLEPRIOSCHARB   ;
   
} ble_type_def;
#define BLE                                     ((ble_type_def *) (CPU_PERIPH_BASE))

/********************************************** RF MODLUE **************************************************/

typedef struct{
    __IO uint32_t   modemcfg1;
    __IO uint32_t   modemcfg2;
    __IO uint32_t   modemcfg3;
    __IO uint32_t   modemcfg4;
    __IO uint32_t   modemcfg5;
    __IO uint32_t   modemcfg6;
    __IO uint32_t   modemrdst1;
    __IO uint32_t   modemrdst2;
    __IO uint32_t   rfcfg1;
    __IO uint32_t   rfcfg2;
    __IO uint32_t   rfcfg3;
    __IO uint32_t   rfcfg4;
    __IO uint32_t   rfcfg5;
    __IO uint32_t   rfcfg6;
    __IO uint32_t   rfcfg7;
    __IO uint32_t   rfcfg8;
    __IO uint32_t   rfrdst1;
    __IO uint32_t   rfrdst2;
    __IO uint32_t reserved[22];
    __IO uint32_t modecfg7;

} rfmodem_type_def;
#define RFMODEM                             ((rfmodem_type_def *) (CPU_PERIPH_BASE + 0x200))

/********************************************** QSPI **************************************************/
#define QSPI_FCU_CMD_ACCESS_REQ         (BIT0)

typedef struct
{
    __IO uint32_t FCU_CMD;
    __O  uint32_t ADDRESS;
    __IO uint32_t BYTE_NUM;
    __O  uint32_t WR_FIFO;
    __I  uint32_t RD_FIFO;
    __IO uint32_t DEVICE_PARA;
    __IO uint32_t REG_WDATA;
    __O  uint32_t REG_RDATA;
    __I  uint32_t INT_MASK;
    __IO uint32_t INT_UMSAK;
    __IO uint32_t INT_MASK_STATUS;
    __IO uint32_t INI_STATUS;
    __IO uint32_t INT_RAWSTATUS;
    __IO uint32_t INT_CLEAR;
    __IO uint32_t CACHE_INTF_CMD;
    __IO uint32_t DMA_CNTL;
    __IO uint32_t FIFO_CNTL;
} qspi_type_def;

#define QSPI                        ((qspi_type_def *) QSPI_BASE)

/********************************************** CHCHE **************************************************/
typedef struct
{
    volatile uint32_t CACHE_CS;
    volatile uint32_t CACHE_REF;
    volatile uint32_t RESERVED[6];
    volatile uint32_t CACHE_BACK_DOOR;
} cache_type_def;


#define CACHE                       ((cache_type_def *)CACHE_BASE)


/********************************************** RNG **************************************************/

#define TRNG_RNG_AMA_PD_TRNG_Pos                                (5)
#define TRNG_RNG_AMA_PD_TRNG_Mask                               (0x01U<<TRNG_RNG_AMA_PD_TRNG_Pos) 
#define TRNG_RNG_CSR_S128_Pos                                   (0)
#define TRNG_RNG_CSR_S128_Mask                                  (0x01U<<TRNG_RNG_CSR_S128_Pos) 
#define TRNG_RNG_CSR_INTP_EN_Pos                                (1)
#define TRNG_RNG_CSR_INTP_EN_Mask                               (0x01U<<TRNG_RNG_CSR_INTP_EN_Pos) 

typedef struct
{
    __IO uint32_t  RNG_CSR;
    __IO uint32_t  RNG0_DATA;
    __IO uint32_t  RESERVED0;
    __IO uint32_t  RNG_ANA;
    __IO uint32_t  RNG_PN;
    __IO uint32_t  RNG_INDEX;
} rng_type_def;
#define RNG_BASE                          (CPU_APB0_BASE + 0x9000)
#define RNG                               ((rng_type_def *)RNG_BASE)

#include "cpu_gpio.h"
#include "cpu_uart.h"
#include "cpu_sysctrl.h"
#include "cpu_spi.h"
#include "cpu_timer.h"
#include "cpu_flash.h"
#include "cpu_nvic.h"
#include "cpu_dma.h"
#include "cpu_i2c.h"
#include "cpu_qdec.h"
#include "cpu_wdt.h"
#include "system_cpu.h"
#include "cpu_gpadc.h"


/* Exported macro ------------------------------------------------------------*/
#ifdef  USE_FULL_ASSERT

/**
  * @brief  The assert_param macro is used for function's parameters check.
  * @param  expr: If expr is false, it calls assert_failed function
  *   which reports the name of the source file and the source
  *   line number of the call that failed. 
  *   If expr is true, it returns no value.
  * @retval None
  */
  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
  void assert_failed(uint8_t* file, uint32_t line);
#else
  #define assert_param(expr) //((void)0)
#endif /* USE_FULL_ASSERT */

#ifdef __cplusplus
}
#endif

/*define to no reation ram*/
#define NO_REATION_RAM(a) a __attribute__((section("no_reation_ram")))

#endif  /* <Device>_H */
