/************************************************************************************************/
/**
* @file               ciu32f032.h
* @author             MCU Ecosystem Development Team
* @brief              CMSIS Core Peripheral Access Layer Header File.
*                      
*
*
**************************************************************************************************
* @attention
* Copyright (c) CEC Huada Electronic Design Co.,Ltd. All rights reserved.
*
**************************************************************************************************
*/

#ifndef CIU32F032_H
#define CIU32F032_H


/************************************************************************************************/
/**
* @addtogroup CMSIS
* @{
*/

/** 
* @defgroup CIU32F032 CIU32F032
* @{
*/
/************************************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */



/*-----------------------------------------type define------------------------------------------*/
/************************************************************************************************/
/** 
* @defgroup CIU32F032_Types CIU32F032 Types
* @brief CIU32F032 data type definition
* @{
*/
/************************************************************************************************/ 

/**
* @brief Interrupt Number Definition
*/
typedef enum IRQn
{
    /* -------------------------------Cortex-M0+ Processor Exceptions Numbers  -------------------------------------- */
    
    NonMaskableInt_IRQn              = -14,    /**< 2 Non Maskable Interrupt                                          */
    HardFault_IRQn                   = -13,    /**< 3 Cortex-M Hard Fault Interrupt                                   */
    SVC_IRQn                         = -5,     /**< 11 Cortex-M SV Call Interrupt                                     */
    PendSV_IRQn                      = -2,     /**< 14 Cortex-M Pend SV Interrupt                                     */
    SysTick_IRQn                     = -1,     /**< 15 Cortex-M System Tick Interrupt                                 */
    
    /* -------------------------------CIU32F032 Interrupt Numbers---------------------------------------------------- */

    PVD_IRQn                         = 1,      /**< PVD global interrupt                                              */
    RTC_IRQn                         = 2,      /**< RTC global interrupt                                              */
    FLASH_IRQn                       = 3,      /**< FLASH global interrupt                                            */
    RCC_IRQn                         = 4,      /**< RCC global interrupt                                              */
    EXTI0_1_IRQn                     = 5,      /**< EXTI line 0 & 1 interrupts                                        */
    EXTI2_3_IRQn                     = 6,      /**< EXTI line 2 & 3 interrupts                                        */
    EXTI4_9_IRQn                     = 7,      /**< EXTI line 4 to 9 interrupts                                       */
    DMA_Channel0_IRQn                = 9,      /**< DMA channel 0 interrupt                                           */
    DMA_Channel1_IRQn                = 10,     /**< DMA channel 1 interrupt                                           */
    DMA_Channel2_IRQn                = 11,     /**< DMA channel 2 interrupt                                           */
    ADC_COMP_IRQn                    = 12,     /**< ADC, COMP1 and COMP2 interrupts                                   */
    TIM1_BRK_UP_TRIG_COM_IRQn        = 13,     /**< TIM1 break, update, trigger and commutation interrupts            */
    TIM1_CC_IRQn                     = 14,     /**< TIM1 capture compare interrupt                                    */
    TIM3_IRQn                        = 15,     /**< TIM3 global interrupt                                             */
    TIM8_IRQn                        = 18,     /**< TIM8 global interrupt                                             */
    LPTIM1_IRQn                      = 20,     /**< LPTIM1 global interrupt                                           */
    I2C1_IRQn                        = 21,     /**< I2C1 global interrupt                                             */
    SPI1_IRQn                        = 23,     /**< SPI1 global interrupt                                             */
    SPI2_IRQn                        = 24,     /**< SPI2 global interrupt                                             */
    UART1_IRQn                       = 25,     /**< UART1 globlal interrupt                                           */
    UART2_IRQn                       = 26,     /**< UART2 globlal interrupt                                           */
    LPUART1_IRQn                     = 28,     /**< LPUART1 globlal interrupt                                         */
} IRQn_Type;

/** 
* @} 
*/

/*--------------------------------------------define--------------------------------------------*/

/************************************************************************************************/
/**
* @defgroup CIU32F032_Constants CIU32F032 Constants
* @brief CIU32F032 constants definition
* @{
*
*/
/************************************************************************************************/    
/**
* @brief Configuration of Core Peripherals
*/
#define __CM0PLUS_REV             0x0001U /**< core revision r0p1                            */
#define __MPU_PRESENT             0U      /**< MPU not defined                               */
#define __VTOR_PRESENT            1U      /**< VTOR present                                  */
#define __NVIC_PRIO_BITS          2U      /**< number of bits used for priority levels       */
#define __Vendor_SysTickConfig    0U      /**< set to 1 if different SysTick Config is used  */

/**
* @brief  NVIC interrupt priority
*/
#define NVIC_PRIO_0         (0x00U)
#define NVIC_PRIO_1         (0x01U)    
#define NVIC_PRIO_2         (0x02U)    
#define NVIC_PRIO_3         (0x03U)

/** 
* @} 
*/

/*------------------------------------------includes--------------------------------------------*/
#include "core_cm0plus.h"                /* Cortex-M0+ processor and core peripherals */
#include "system.h"                      /* System Header */
#include <stdint.h>

/*-----------------------------------------type define------------------------------------------*/
/************************************************************************************************/
/** 
* @addtogroup  CIU32F032_Types
* @{
*/
/************************************************************************************************/
/**
* @brief registers of ADC 
*/
typedef struct  
{
    __IO uint32_t CR;                      /**< ADC controlregister,                            Address offset: 0x00         */
    __IO uint32_t CFG1;                    /**< ADC configuration register 1,                   Address offset: 0x04         */
    __IO uint32_t CFG2;                    /**< ADC configuration register 2,                   Address offset: 0x08         */
    __IO uint32_t RESERVED_0[1];           /**< Reserved,                                       Address offset: 0x0C         */
    __IO uint32_t ISR;                     /**< ADC interrupt and status register,              Address offset: 0x10         */
    __IO uint32_t IER;                     /**< ADC interrupt enable register,                  Address offset: 0x14         */
    __IO uint32_t SAMPT;                   /**< ADC sampling time register,                     Address offset: 0x18         */
    __IO uint32_t CHCFG;                   /**< ADC group regular sequencer register,           Address offset: 0x1C         */
    __IO uint32_t AWDGCR;                  /**< ADC analog watchdog configuration register,     Address offset: 0x20         */
    __IO uint32_t RESERVED_1[1];           /**< Reserved,                                       Address offset: 0x24         */
    __IO uint32_t AWDGTR;                  /**< ADC analog watchdog threshold register,         Address offset: 0x28         */
    __IO uint32_t RESERVED_2[1];           /**< Reserved,                                       Address offset: 0x2C         */
    __IO uint32_t CALFACT;                 /**< ADC calibration factor register,                Address offset: 0x30         */
    __IO uint32_t RESERVED_3[3];           /**< Reserved,                                       Address offset: 0x34 - 0x3C  */
    __IO uint32_t DR;                      /**< ADC register,                                   Address offset: 0x40         */
    __IO uint32_t RESERVED_4[111];         /**< Reserved,                                       Address offset: 0x44 - 0x1FC */
    __IO uint32_t CFG3;                    /**< ADC configuration register 3,                   Address offset: 0x200         */
} ADC_t;

/**
* @brief registers of COMP
*/
typedef struct
{
    __IO uint32_t CR;                      /**< COMP common control regigster,           Address offset: 0x00 */
} COMP_COMMON_t;

typedef struct
{
    __IO uint32_t CSR1;                     /**< COMP control and status register 1,        Address offset: 0x00 */
    __IO uint32_t CSR2;                     /**< COMP control and status register 2,        Address offset: 0x04 */
    __IO uint32_t SR;                       /**< COMP status register,                      Address offset: 0x08 */
} COMP_t;


/**
* @brief registers of CRC 
*/
typedef struct  
{
    __IO uint32_t CSR;                     /**< CRC control and status register, Address offset: 0x00        */
    __IO uint32_t RDR;                     /**< CRC result data register,        Address offset: 0x04        */
    __IO uint32_t RESERVED_0[30];          /**< Reserved,                        Address offset: 0x08 - 0x7C */
    __IO uint32_t DR;                      /**< CRC data register,               Address offset: 0x80        */
} CRC_t;

/**
* @brief registers of DBG 
*/
typedef struct  
{
    __IO uint32_t CR;                      /**< DBG control register,     Address offset: 0x00         */
    __IO uint32_t APB_FZ1;                 /**< DBG APB freeze register1, Address offset: 0x04         */
    __IO uint32_t APB_FZ2;                 /**< DBG APB freeze register2, Address offset: 0x08         */
} DBG_t;

/**
* @brief registers of DMA
*/
typedef struct
{
    __IO uint32_t CC;                     /**< DMA channel x configuration register,        Address offset: 0x00        */
    __IO uint32_t CNDTR;                  /**< DMA channel x number of data register,       Address offset: 0x04        */
    __IO uint32_t CSAR;                   /**< DMA channel x source address register,       Address offset: 0x08        */
    __IO uint32_t CDAR;                   /**< DMA channel x destination address register,  Address offset: 0x0C        */
    __IO uint32_t RESERVED_0[1];          /**< Reserved,                                    Address offset: 0x10        */
} DMA_Channel_t;

typedef struct
{
    __IO uint32_t ISR;                    /**< DMA interrupt status register,               Address offset: 0x00        */
    __IO uint32_t ICR;                    /**< DMA interrupt flag clear register,           Address offset: 0x04        */
    DMA_Channel_t channel[3];             /**< DMA channel registers,                       Address offset: 0x08 - 0x30 */
} DMA_t;


/**
* @brief registers of EXTI 
*/
typedef struct  
{
    __IO uint32_t RTSR;                    /**< EXTI rising trigger selection register,                Address offset: 0x00         */
    __IO uint32_t FTSR;                    /**< EXTI falling trigger selection register,               Address offset: 0x04         */
    __IO uint32_t PIR;                     /**< EXTI Rising or Falling pending register,               Address offset: 0x08         */
    __IO uint32_t RESERVED_0[17];          /**< Reserved,                                              Address offset: 0x0C - 0x4C  */
    __IO uint32_t EXTICR[2];               /**< EXTI external interrupt configuration register,        Address offset: 0x50         */
    __IO uint32_t RESERVED_1[2];           /**< Reserved,                                              Address offset: 0x58 - 0x5C  */
    __IO uint32_t FILTER;                  /**< EXTI filter clock configuration register,              Address offset: 0x60         */
    __IO uint32_t RESERVED_2[3];           /**< Reserved,                                              Address offset: 0x64 - 0x6C  */
    __IO uint32_t IMR;                     /**< EXTI interrupt mask register,                          Address offset: 0x70         */
    __IO uint32_t EMR;                     /**< EXTI event mask register,                              Address offset: 0x74         */
} EXTI_t;

/**
* @brief registers of Flash 
*/
typedef struct  
{
    __IO uint32_t ACR;                     /**< FLASH access configuration register, Address offset: 0x00         */
    __IO uint32_t RESERVED_0[1];           /**< Reserved,                            Address offset: 0x04         */
    __IO uint32_t CRKEY;                   /**< FLASH CR key register,               Address offset: 0x08         */
    __IO uint32_t OPTKEY;                  /**< FLASH OB key register,               Address offset: 0x0C         */
    __IO uint32_t SR;                      /**< FLASH status register,               Address offset: 0x10         */
    __IO uint32_t CR;                      /**< FLASH control register,              Address offset: 0x14         */
    __IO uint32_t RESERVED_1[2];           /**< Reserved,                            Address offset: 0x18 - 0x1C  */
    __IO uint32_t OPTR1;                   /**< FLASH option register 1,             Address offset: 0x20         */
    __IO uint32_t OPTR2;                   /**< FLASH option register 2,             Address offset: 0x24         */
    __IO uint32_t RESERVED_2[4];           /**< Reserved,                            Address offset: 0x28 - 0x34  */
    __IO uint32_t WRP;                     /**< FLASH write protection register,     Address offset: 0x38         */
} FLASH_t;

/**
* @brief registers of GPIO 
*/
typedef struct  
{
    __IO uint32_t MODE;                    /**< GPIO port mode register,                 Address offset: 0x00         */
    __IO uint32_t OTYPE;                   /**< GPIO port output type register,          Address offset: 0x04         */
    __IO uint32_t RESERVED_0[1];           /**< Reserved,                                Address offset: 0x08         */
    __IO uint32_t PUPD;                    /**< GPIO port pull-up/pull-down register,    Address offset: 0x0C         */
    __IO uint32_t IDR;                     /**< GPIO port input data register,           Address offset: 0x10         */
    __IO uint32_t ODR;                     /**< GPIO port output data register,          Address offset: 0x14         */
    __IO uint32_t BSR;                     /**< GPIO port bit set/reset register,        Address offset: 0x18         */
    __IO uint32_t RESERVED_1[1];           /**< Reserved,                                Address offset: 0x1C         */
    __IO uint32_t AFL;                     /**< GPIO alternate function register 1,      Address offset: 0x20         */
    __IO uint32_t AFH;                     /**< GPIO alternate function register 2,      Address offset: 0x24         */
    __IO uint32_t BR;                      /**< GPIO bit reset register,                 Address offset: 0x28         */
    __IO uint32_t HDCFG1;                  /**< GPIO drive configuration register 1,     Address offset: 0x2C         */
    __IO uint32_t HDCFG2;                  /**< GPIO drive configuration register 2,     Address offset: 0x30         */
} GPIO_t;

/**
* @brief registers of I2C 
*/
typedef struct  
{
    __IO uint32_t CR1;                     /**< I2C control register 1,         Address offset: 0x00         */
    __IO uint32_t CR2;                     /**< I2C control register 2,         Address offset: 0x04         */
    __IO uint32_t ADDR1;                   /**< I2C address 1 register,         Address offset: 0x08         */
    __IO uint32_t ADDR2;                   /**< I2C address 2 register,         Address offset: 0x0C         */
    __IO uint32_t RESERVED_0[2];           /**< Reserved,                       Address offset: 0x10 - 0x14  */
    __IO uint32_t ISR;                     /**< I2C interrupt status register,  Address offset: 0x18         */
    __IO uint32_t ICR;                     /**< I2C interrupt clear register,   Address offset: 0x1C         */
    __IO uint32_t RESERVED_1[1];           /**< Reserved,                       Address offset: 0x20         */
    __IO uint32_t RDR;                     /**< I2C reception data register,    Address offset: 0x24         */
    __IO uint32_t TDR;                     /**< I2C transmission data register, Address offset: 0x28         */
} I2C_t;

/**
* @brief registers of IRTIM 
*/
typedef struct  
{
    __IO uint32_t CR;                      /**< IRTIM control register,      Address offset: 0x00            */
} IRTIM_t;

/**
* @brief registers of IWDG 
*/
typedef struct  
{
    __IO uint32_t CR;                      /**< IWDG control register,       Address offset: 0x00         */
    __IO uint32_t CFG;                     /**< IWDG configuration register, Address offset: 0x04         */
    __IO uint32_t RESERVED_0[3];           /**< Reserved,                    Address offset: 0x08 - 0x10  */
    __IO uint32_t CNT;                     /**< IWDG counter register,       Address offset: 0x14         */
} IWDG_t;

/**
* @brief registers of LPTIM 
*/
typedef struct  
{
    __IO uint32_t ISR;                     /**< LPTIM interrupt and status register, Address offset: 0x00    */
    __IO uint32_t ICR;                     /**< LPTIM interrupt clear register,      Address offset: 0x04    */
    __IO uint32_t IER;                     /**< LPTIM interrupt enable register,     Address offset: 0x08    */
    __IO uint32_t CFG;                     /**< LPTIM configuration register,        Address offset: 0x0C    */
    __IO uint32_t CR;                      /**< LPTIM control register,              Address offset: 0x10    */
    __IO uint32_t RESERVED_0[1];           /**< Reserved,                            Address offset: 0x14    */
    __IO uint32_t ARR;                     /**< LPTIM autoreload register,           Address offset: 0x18    */
    __IO uint32_t CNT;                     /**< LPTIM counter register,              Address offset: 0x1C    */
} LPTIM_t;

/**
* @brief registers of PMU 
*/
typedef struct  
{
    __IO uint32_t CR1;                     /**< PMU control register 1,          Address offset: 0x00         */
    __IO uint32_t CR2;                     /**< PMU control register 2,          Address offset: 0x04         */
    __IO uint32_t RESERVED_0[3];           /**< Reserved,                        Address offset: 0x08 - 0x10  */
    __IO uint32_t SR;                      /**< PMU status register,             Address offset: 0x14         */
    __IO uint32_t CLR;                     /**< PMU clear register,              Address offset: 0x18         */
} PMU_t;

/**
* @brief registers of RCC 
*/
typedef struct  
{
    __IO uint32_t CSR1;                    /**< RCC control and status register 1,                        Address offset: 0x00                */
    __IO uint32_t RESERVED_0[1];           /**< Reserved,                                                 Address offset: 0x04                */
    __IO uint32_t CFG;                     /**< RCC configuration register,                               Address offset: 0x08                */
    __IO uint32_t RESERVED_1[1];           /**< Reserved,                                                 Address offset: 0x0C - 0x10         */
    __IO uint32_t IER;                     /**< RCC interrupt enable register,                            Address offset: 0x10                */
    __IO uint32_t ISR;                     /**< RCC interrupt and status register,                        Address offset: 0x14                */
    __IO uint32_t ICR;                     /**< RCC interrupt clear register,                             Address offset: 0x18                */
    __IO uint32_t IOPRST;                  /**< RCC I/O port reset register,                              Address offset: 0x1C                */
    __IO uint32_t AHBRST;                  /**< RCC AHB peripheral reset register,                        Address offset: 0x20                */
    __IO uint32_t APBRST1;                 /**< RCC APB peripheral reset register 1,                      Address offset: 0x24                */
    __IO uint32_t APBRST2;                 /**< RCC APB peripheral reset register 2,                      Address offset: 0x28                */
    __IO uint32_t IOPEN;                   /**< RCC I/O port clock enable register,                       Address offset: 0x2C                */
    __IO uint32_t AHBEN;                   /**< RCC AHB peripheral clock enable register,                 Address offset: 0x30                */
    __IO uint32_t APBEN1;                  /**< RCC APB peripheral clock enable register 1,               Address offset: 0x34                */
    __IO uint32_t APBEN2;                  /**< RCC APB peripheral clock enable register 2,               Address offset: 0x38                */
    __IO uint32_t CLKSEL;                  /**< RCC peripherals independent clock source select register, Address offset: 0x3C                */
    __IO uint32_t AWCR;                    /**< RCC AWON domain control register,                         Address offset: 0x40                */
    __IO uint32_t CSR2;                    /**< RCC control and status register 2,                        Address offset: 0x44                */
    __IO uint32_t RESERVED_2[2];           /**< Reserved,                                                 Address offset: 0x48 - 0x4C         */
    __IO uint32_t RCLCAL;                  /**< RCC RCL calibration register,                             Address offset: 0x50                */
    __IO uint32_t RCHCAL;                  /**< RCC RCH calibration register,                             Address offset: 0x54                */
} RCC_t;

/**
* @brief registers of RTC 
*/
typedef struct  
{
    __IO uint32_t TR;                      /**< RTC time register,                               Address offset: 0x00         */
    __IO uint32_t DR;                      /**< RTC date register,                               Address offset: 0x04         */
    __IO uint32_t SSR;                     /**< RTC sbu second register,                         Address offset: 0x08         */
    __IO uint32_t CSR;                     /**< RTC control and status register,                 Address offset: 0x0C         */
    __IO uint32_t RESERVED_0[2];           /**< Reserved,                                        Address offset: 0x10 - 0x14  */
    __IO uint32_t CR;                      /**< RTC control register,                            Address offset: 0x18         */
    __IO uint32_t WUTIM1;                  /**< RTC wakeup timer register 1,                     Address offset: 0x1C         */
    __IO uint32_t WUTIM2;                  /**< RTC wakeup timer register 2,                     Address offset: 0x20         */
    __IO uint32_t WPR;                     /**< RTC write protection register,                   Address offset: 0x24         */
    __IO uint32_t CALR;                    /**< RTC calibration register,                        Address offset: 0x28         */
    __IO uint32_t RESERVED_1[5];           /**< Reserved,                                        Address offset: 0x2C - 0x3C  */
    __IO uint32_t ALARMR;                  /**< RTC alarm register,                              Address offset: 0x40         */
    __IO uint32_t RESERVED_2[3];           /**< Reserved,                                        Address offset: 0x44 - 0x4C  */
    __IO uint32_t SR;                      /**< RTC status register,                             Address offset: 0x50         */
    __IO uint32_t ISR;                     /**< RTC interrupt status register,                   Address offset: 0x54         */
    __IO uint32_t RESERVED_3[1];           /**< Reserved,                                        Address offset: 0x58         */
    __IO uint32_t CLR;                     /**< RTC clear register,                              Address offset: 0x5C         */
} RTC_t;

/**
* @brief registers of SPI 
*/
typedef struct  
{
    __IO uint32_t CR1;                     /**< SPI control register 1,        Address offset: 0x00         */
    __IO uint32_t CR2;                     /**< SPI control register 2,        Address offset: 0x04         */
    __IO uint32_t RESERVED_0[1];           /**< Reserved,                      Address offset: 0x08         */
    __IO uint32_t ISR;                     /**< SPI interrupt status register, Address offset: 0x0C         */
    __IO uint32_t ICR;                     /**< SPI interrupt clear register,  Address offset: 0x10         */
    __IO uint32_t DR;                      /**< SPI data register,             Address offset: 0x14         */
} SPI_t;

/**
* @brief registers of TIM 
*/
typedef struct  
{
    __IO uint32_t CR1;                     /**< TIM control register 1,                     Address offset: 0x00         */
    __IO uint32_t CR2;                     /**< TIM control register 2,                     Address offset: 0x04         */
    __IO uint32_t SMC;                     /**< TIM slave mode control register,            Address offset: 0x08         */
    __IO uint32_t DIER;                    /**< TIM interrupt and DMA enable register,      Address offset: 0x0C         */
    __IO uint32_t SR;                      /**< TIM status register,                        Address offset: 0x10         */
    __IO uint32_t EVTG;                    /**< TIM event generation register,              Address offset: 0x14         */
    __IO uint32_t CCM1;                    /**< TIM capture/compare mode register 1,        Address offset: 0x18         */
    __IO uint32_t CCM2;                    /**< TIM capture/compare mode register 2,        Address offset: 0x1C         */
    __IO uint32_t CCEN;                    /**< TIM capture/compare enable register,        Address offset: 0x20         */
    __IO uint32_t CNT;                     /**< TIM counter register,                       Address offset: 0x24         */
    __IO uint32_t PSC;                     /**< TIM prescaler register,                     Address offset: 0x28         */
    __IO uint32_t ARR;                     /**< TIM auto-reload register,                   Address offset: 0x2C         */
    __IO uint32_t RCR;                     /**< TIM repetition counter register,            Address offset: 0x30         */
    __IO uint32_t CC1;                     /**< TIM capture/compare register 1,             Address offset: 0x34         */
    __IO uint32_t CC2;                     /**< TIM capture/compare register 2,             Address offset: 0x38         */
    __IO uint32_t CC3;                     /**< TIM capture/compare register 3,             Address offset: 0x3C         */
    __IO uint32_t CC4;                     /**< TIM capture/compare register 4,             Address offset: 0x40         */
    __IO uint32_t BDT;                     /**< TIM break and dead-time register,           Address offset: 0x44         */
    __IO uint32_t RESERVED_0[2];           /**< Reserved,                                   Address offset: 0x48 - 0x4C  */
    __IO uint32_t CFG;                     /**< TIM configuration register,                 Address offset: 0x50         */
    __IO uint32_t RESERVED_1[3];           /**< Reserved,                                   Address offset: 0x54 - 0x5C  */    
    __IO uint32_t AF1;                     /**< TIM alternate function register,            Address offset: 0x60         */
    __IO uint32_t RESERVED_2[1];           /**< Reserved,                                   Address offset: 0x64         */
    __IO uint32_t TISEL;                   /**< TIM input selection register,               Address offset: 0x68         */
} TIM_t;

/**
* @brief registers of UART 
*/
typedef struct  
{
    __IO uint32_t CR1;                     /**< UART control register 1,                    Address offset: 0x00         */
    __IO uint32_t CR2;                     /**< UART control register 2,                    Address offset: 0x04         */
    __IO uint32_t CR3;                     /**< UART control register 3,                    Address offset: 0x08         */
    __IO uint32_t BRR;                     /**< UART baud rate register,                    Address offset: 0x0C         */
    __IO uint32_t RESERVED_0[3];           /**< Reserved,                                   Address offset: 0x10 - 0x18  */
    __IO uint32_t ISR;                     /**< UART interrupt and status register,         Address offset: 0x1C         */
    __IO uint32_t ICR;                     /**< UART interrupt flag clear register,         Address offset: 0x20         */
    __IO uint32_t RDR;                     /**< UART receive data register,                 Address offset: 0x24         */
    __IO uint32_t TDR;                     /**< UART transmit data register,                Address offset: 0x28         */
    __IO uint32_t PRESC;                   /**< UART prescaler register,                    Address offset: 0x2C         */
} UART_t;


/**
* @}
*/

/*--------------------------------------------define--------------------------------------------*/
/************************************************************************************************/
/** 
* @addtogroup CIU32F032_Constants
* @{
*/
/************************************************************************************************/
/* Memory Map */
#define FLASH_MEM_BASE        (0x08000000UL)  /**< FLASH base address */
#define SRAM_BASE             (0x20000000UL)  /**< SRAM base address  */
#define APB_BASE              (0x40000000UL)  /**< APB base address   */
#define AHB_BASE              (0x40020000UL)  /**< AHB base address   */
#define GPIO_BASE             (0x50000000UL)  /**< GPIO base address  */

/* Option Bytes */
#define FLASH_OB_OPTR1_ADDR   (0x1FFF0000UL)  /**< Option Bytes1 base address                   */
#define FLASH_OB_OPTR2_ADDR   (0x1FFF0004UL)  /**< Option Bytes2 base address                   */

/* Engineer */
#define UID_BASE              (0x1FFF0220UL)  /**< Unique device ID register base address       */
#define USERFLASH_SIZE        (0x1FFF0264UL)  /**< Size of user flash                           */
#define SRAM_SIZE             (0x1FFF0268UL)  /**< Size of sram                                 */
#define RCH16M_CAL            (0x1FFF0208UL)  /**< RCH16M calibration value address             */
#define RCH48M_CAL            (0x1FFF020CUL)  /**< RCH48M calibration value address             */
#define RCL_CAL               (0x1FFF0210UL)  /**< RCL calibration value address                */
#define BGR_CAL               (0x1FFF026CUL)  /**< BGR calibration value address                */
#define TS_CAL_25             (0x1FFF0270UL)  /**< TS calibration value address for 25¡æ        */
#define TS_CAL_85             (0x1FFF0274UL)  /**< TS calibration value address for 85¡æ        */

/* APB Peripherals */
#define ADC_BASE              (APB_BASE + 0x00012400UL)
#define COMP_COMMON_BASE      (APB_BASE + 0x00010200UL)
#define COMP1_BASE            (COMP_COMMON_BASE + 0x00000010UL)
#define COMP2_BASE            (COMP_COMMON_BASE + 0x00000020UL)
#define DBG_BASE              (APB_BASE + 0x00015800UL)
#define I2C1_BASE             (APB_BASE + 0x00005400UL)
#define IRTIM_BASE            (APB_BASE + 0x00010000UL)
#define IWDG_BASE             (APB_BASE + 0x00003000UL)
#define LPTIM1_BASE           (APB_BASE + 0x00007C00UL)
#define LPUART1_BASE          (APB_BASE + 0x00008000UL)
#define PMU_BASE              (APB_BASE + 0x00007000UL)
#define RTC_BASE              (APB_BASE + 0x00002800UL)
#define SPI1_BASE             (APB_BASE + 0x00013000UL)
#define SPI2_BASE             (APB_BASE + 0x00003800UL)
#define TIM1_BASE             (APB_BASE + 0x00012C00UL)
#define TIM3_BASE             (APB_BASE + 0x00000400UL)
#define TIM8_BASE             (APB_BASE + 0x00001000UL)
#define UART1_BASE            (APB_BASE + 0x00013800UL)
#define UART2_BASE            (APB_BASE + 0x00004400UL)

/* AHB Peripherals */
#define CRC_BASE              (AHB_BASE + 0x00003000UL)
#define DMA_BASE              (AHB_BASE + 0x00000000UL)
#define EXTI_BASE             (AHB_BASE + 0x00001800UL)
#define FLASH_REGISTERS_BASE  (AHB_BASE + 0x00002000UL)
#define RCC_BASE              (AHB_BASE + 0x00001000UL)

/* GPIO */
#define GPIOA_BASE            (GPIO_BASE + 0x00000000UL)
#define GPIOB_BASE            (GPIO_BASE + 0x00000400UL)
#define GPIOF_BASE            (GPIO_BASE + 0x00001400UL)

/* APB Peripherals instance */
#define ADC                   ((ADC_t *) ADC_BASE)
#define COMP_COMMON           ((COMP_COMMON_t *) COMP_COMMON_BASE)
#define COMP1                 ((COMP_t *) COMP1_BASE)
#define COMP2                 ((COMP_t *) COMP2_BASE)
#define DBG                   ((DBG_t *) DBG_BASE)
#define I2C1                  ((I2C_t *) I2C1_BASE)
#define IRTIM                 ((IRTIM_t *) IRTIM_BASE)
#define IWDG                  ((IWDG_t *) IWDG_BASE)
#define LPTIM1                ((LPTIM_t *) LPTIM1_BASE)
#define LPUART1               ((UART_t *) LPUART1_BASE)
#define PMU                   ((PMU_t *) PMU_BASE)
#define RTC                   ((RTC_t *) RTC_BASE)
#define SPI1                  ((SPI_t *) SPI1_BASE)
#define SPI2                  ((SPI_t *) SPI2_BASE)
#define TIM1                  ((TIM_t *) TIM1_BASE)
#define TIM3                  ((TIM_t *) TIM3_BASE)
#define TIM8                  ((TIM_t *) TIM8_BASE)
#define UART1                 ((UART_t *) UART1_BASE)
#define UART2                 ((UART_t *) UART2_BASE)

/* AHB Peripherals instance */
#define CRC                   ((CRC_t *) CRC_BASE)
#define DMA                   ((DMA_t *) DMA_BASE)
#define EXTI                  ((EXTI_t *) EXTI_BASE)
#define FLASH                 ((FLASH_t *) FLASH_REGISTERS_BASE)
#define RCC                   ((RCC_t *) RCC_BASE)

/* GPIO instance */
#define GPIOA                 ((GPIO_t *) GPIOA_BASE)
#define GPIOB                 ((GPIO_t *) GPIOB_BASE)
#define GPIOF                 ((GPIO_t *) GPIOF_BASE)


/*---------------------------Peripheral Registers Bits Definition-------------------------------*/

/*-----------------------------------------------------------------------------------------------
                                       ADC  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for ADC_CR */
#define ADC_CR_ADEN_POS                          (0U)
#define ADC_CR_ADEN_MASK                         (0x1UL << ADC_CR_ADEN_POS)                         /**< 0x00000001 */
#define ADC_CR_ADEN                              ADC_CR_ADEN_MASK                                   /**< ADC enable                         */
#define ADC_CR_ADDIS_POS                         (1U)
#define ADC_CR_ADDIS_MASK                        (0x1UL << ADC_CR_ADDIS_POS)                        /**< 0x00000002  */
#define ADC_CR_ADDIS                             ADC_CR_ADDIS_MASK                                  /**< ADC disable                        */
#define ADC_CR_START_POS                         (2U)
#define ADC_CR_START_MASK                        (0x1UL << ADC_CR_START_POS)                        /**< 0x00000004 */
#define ADC_CR_START                             ADC_CR_START_MASK                                  /**< ADC group regular conversion start */
#define ADC_CR_STOP_POS                          (4U)
#define ADC_CR_STOP_MASK                         (0x1UL << ADC_CR_STOP_POS)                         /**< 0x00000010 */
#define ADC_CR_STOP                              ADC_CR_STOP_MASK                                   /**< ADC group regular conversion stop  */
#define ADC_CR_CALEN_POS                         (31U)
#define ADC_CR_CALEN_MASK                        (0x1UL << ADC_CR_CALEN_POS)                        /**< 0x80000000      */
#define ADC_CR_CALEN                             ADC_CR_CALEN_MASK                                  /**< ADC calibration                    */

/* Bits for ADC_CFG1 */
#define ADC_CFG1_DMAEN_POS                       (0U)
#define ADC_CFG1_DMAEN_MASK                      (0x1UL << ADC_CFG1_DMAEN_POS)                      /**< 0x00000001     */
#define ADC_CFG1_DMAEN                           ADC_CFG1_DMAEN_MASK                                /**< ADC DMA enable                     */
#define ADC_CFG1_SDIR_POS                        (2U)
#define ADC_CFG1_SDIR_MASK                       (0x1UL << ADC_CFG1_SDIR_POS)                       /**< 0x00000004 */
#define ADC_CFG1_SDIR                            ADC_CFG1_SDIR_MASK                                 /**< ADC group regular sequencer scan direction    */
#define ADC_CFG1_TRIGEN_POS                      (9U)
#define ADC_CFG1_TRIGEN_MASK                     (0x3UL << ADC_CFG1_TRIGEN_POS)                     /**< 0x00000600 */
#define ADC_CFG1_TRIGEN                          ADC_CFG1_TRIGEN_MASK                               /**< ADC group regular external trigger polarity   */
#define ADC_CFG1_TRIGEN_SW                       (0x0UL << ADC_CFG1_TRIGEN_POS)                     /**< 0x00000000 */
#define ADC_CFG1_TRIGEN_HW_EDGE_RISING           (0x1UL << ADC_CFG1_TRIGEN_POS)                     /**< 0x00000200 */
#define ADC_CFG1_TRIGEN_HW_EDGE_FALLING          (0x2UL << ADC_CFG1_TRIGEN_POS)                     /**< 0x00000400 */
#define ADC_CFG1_TRIGEN_HW_EDGE_BOTH             (0x3UL << ADC_CFG1_TRIGEN_POS)                     /**< 0x00000600 */
#define ADC_CFG1_OVRN_MOD_POS                    (11U)
#define ADC_CFG1_OVRN_MOD_MASK                   (0x1UL << ADC_CFG1_OVRN_MOD_POS)                   /**< 0x00000800 */
#define ADC_CFG1_OVRN_MOD                        ADC_CFG1_OVRN_MOD_MASK                             /**< ADC group regular overrun configuration       */
#define ADC_CFG1_CONV_MOD_POS                    (12U)
#define ADC_CFG1_CONV_MOD_MASK                   (0x3UL << ADC_CFG1_CONV_MOD_POS)                   /**< 0x00003000 */
#define ADC_CFG1_CONV_MOD                        ADC_CFG1_CONV_MOD_MASK                             /**< ADC group regular sequencer conversion mode   */
#define ADC_CFG1_CONV_MOD_SINGLE                 (0x0UL << ADC_CFG1_CONV_MOD_POS)                   /**< 0x00000000 */
#define ADC_CFG1_CONV_MOD_CONTINUOUS             (0x1UL << ADC_CFG1_CONV_MOD_POS)                   /**< 0x00001000 */
#define ADC_CFG1_CONV_MOD_DISCONTINUOUS          (0x2UL << ADC_CFG1_CONV_MOD_POS)                   /**< 0x00002000 */
#define ADC_CFG1_WAIT_MOD_POS                    (14U)
#define ADC_CFG1_WAIT_MOD_MASK                   (0x1UL << ADC_CFG1_WAIT_MOD_POS)                   /**< 0x00004000    */
#define ADC_CFG1_WAIT_MOD                        ADC_CFG1_WAIT_MOD_MASK                             /**< ADC auto wait */
#define ADC_CFG1_TRIG_SEL_POS                    (16U)
#define ADC_CFG1_TRIG_SEL_MASK                   (0x7UL << ADC_CFG1_TRIG_SEL_POS)                   /**< 0x00070000 */
#define ADC_CFG1_TRIG_SEL                        ADC_CFG1_TRIG_SEL_MASK                             /**< ADC group regular external trigger source     */
#define ADC_CFG1_TRIG_TIM1_TRGO                  (0x0UL << ADC_CFG1_TRIG_SEL_POS)                   /**< 0x00000000 */
#define ADC_CFG1_TRIG_TIM1_OC4_ADC               (0x1UL << ADC_CFG1_TRIG_SEL_POS)                   /**< 0x00010000 */
#define ADC_CFG1_TRIG_TIM3_TRGO                  (0x2UL << ADC_CFG1_TRIG_SEL_POS)                   /**< 0x00020000 */
#define ADC_CFG1_TRIG_TIM8_TRGO                  (0x3UL << ADC_CFG1_TRIG_SEL_POS)                   /**< 0x00030000 */
#define ADC_CFG1_TRIG_EXTI7                      (0x6UL << ADC_CFG1_TRIG_SEL_POS)                   /**< 0x00060000 */
#define ADC_CFG1_TRIG_EXTI9                      (0x7UL << ADC_CFG1_TRIG_SEL_POS)                   /**< 0x00070000 */

/* Bits for ADC_CFG2 */
#define ADC_CFG2_VBGREN_POS                      (16U)
#define ADC_CFG2_VBGREN_MASK                     (0x1UL << ADC_CFG2_VBGREN_POS)                     /**< 0x00010000 */
#define ADC_CFG2_VBGREN                          ADC_CFG2_VBGREN_MASK                               /**< ADC internal path to VBGR enable */
#define ADC_CFG2_VTSEN_POS                       (17U)
#define ADC_CFG2_VTSEN_MASK                      (0x1UL << ADC_CFG2_VTSEN_POS)                      /**< 0x00020000 */
#define ADC_CFG2_VTSEN                           ADC_CFG2_VTSEN_MASK                                /**< ADC internal path to VTS enable  */
#define ADC_CFG2_PRESC_POS                       (24U)
#define ADC_CFG2_PRESC_MASK                      (0x7UL << ADC_CFG2_PRESC_POS)                      /**< 0x07000000 */
#define ADC_CFG2_PRESC                           ADC_CFG2_PRESC_MASK                                /**< ADC clock prescaler              */
#define ADC_CFG2_PRESC_DIV1                      (0x0UL << ADC_CFG2_PRESC_POS)                      /**< 0x00000000 */
#define ADC_CFG2_PRESC_DIV2                      (0x1UL << ADC_CFG2_PRESC_POS)                      /**< 0x01000000 */
#define ADC_CFG2_PRESC_DIV3                      (0x2UL << ADC_CFG2_PRESC_POS)                      /**< 0x02000000 */
#define ADC_CFG2_PRESC_DIV4                      (0x3UL << ADC_CFG2_PRESC_POS)                      /**< 0x03000000 */
#define ADC_CFG2_PRESC_DIV8                      (0x4UL << ADC_CFG2_PRESC_POS)                      /**< 0x04000000 */
#define ADC_CFG2_PRESC_DIV16                     (0x5UL << ADC_CFG2_PRESC_POS)                      /**< 0x05000000 */
#define ADC_CFG2_PRESC_DIV32                     (0x6UL << ADC_CFG2_PRESC_POS)                      /**< 0x06000000 */
#define ADC_CFG2_PRESC_DIV64                     (0x7UL << ADC_CFG2_PRESC_POS)                      /**< 0x07000000 */

/* Bits for ADC_ISR */
#define ADC_ISR_EOSAMP_POS                       (1U)
#define ADC_ISR_EOSAMP_MASK                      (0x1UL << ADC_ISR_EOSAMP_POS)                      /**< 0x00000002 */
#define ADC_ISR_EOSAMP                           ADC_ISR_EOSAMP_MASK                                /**< ADC group regular end of sampling flag             */
#define ADC_ISR_EOC_POS                          (2U)
#define ADC_ISR_EOC_MASK                         (0x1UL << ADC_ISR_EOC_POS)                         /**< 0x00000004 */
#define ADC_ISR_EOC                              ADC_ISR_EOC_MASK                                   /**< ADC group regular end of unitary conversion flag   */
#define ADC_ISR_EOS_POS                          (3U)
#define ADC_ISR_EOS_MASK                         (0x1UL << ADC_ISR_EOS_POS)                         /**< 0x00000008 */
#define ADC_ISR_EOS                              ADC_ISR_EOS_MASK                                   /**< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVRN_POS                         (4U)
#define ADC_ISR_OVRN_MASK                        (0x1UL << ADC_ISR_OVRN_POS)                        /**< 0x00000010 */
#define ADC_ISR_OVRN                             ADC_ISR_OVRN_MASK                                  /**< ADC group regular overrun flag                     */
#define ADC_ISR_AWDG_POS                         (7U)
#define ADC_ISR_AWDG_MASK                        (0x1UL << ADC_ISR_AWDG_POS)                        /**< 0x00000080 */
#define ADC_ISR_AWDG                             ADC_ISR_AWDG_MASK                                  /**< ADC analog watchdog flag                           */

/* Bits for ADC_IER */
#define ADC_IER_EOSAMPIE_POS                     (1U)
#define ADC_IER_EOSAMPIE_MASK                    (0x1UL << ADC_IER_EOSAMPIE_POS)                    /**< 0x00000002 */
#define ADC_IER_EOSAMPIE                         ADC_IER_EOSAMPIE_MASK                              /**< ADC group regular end of sampling interrupt             */
#define ADC_IER_EOCIE_POS                        (2U)
#define ADC_IER_EOCIE_MASK                       (0x1UL << ADC_IER_EOCIE_POS)                       /**< 0x00000004 */
#define ADC_IER_EOCIE                            ADC_IER_EOCIE_MASK                                 /**< ADC group regular end of unitary conversion interrupt   */
#define ADC_IER_EOSIE_POS                        (3U)
#define ADC_IER_EOSIE_MASK                       (0x1UL << ADC_IER_EOSIE_POS)                       /**< 0x00000008 */
#define ADC_IER_EOSIE                            ADC_IER_EOSIE_MASK                                 /**< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRNIE_POS                       (4U)
#define ADC_IER_OVRNIE_MASK                      (0x1UL << ADC_IER_OVRNIE_POS)                      /**< 0x00000010 */
#define ADC_IER_OVRNIE                           ADC_IER_OVRNIE_MASK                                /**< ADC group regular overrun interrupt                     */
#define ADC_IER_AWDGIE_POS                       (7U)
#define ADC_IER_AWDGIE_MASK                      (0x1UL << ADC_IER_AWDGIE_POS)                      /**< 0x00000080 */
#define ADC_IER_AWDGIE                           ADC_IER_AWDGIE_MASK                                /**< ADC analog watchdog interrupt                           */

/* Bits for ADC_SAMPT */
#define ADC_SAMPT_SAMPT_POS                      (0U)
#define ADC_SAMPT_SAMPT_MASK                     (0xFUL << ADC_SAMPT_SAMPT_POS)                     /**< 0x0000000F */
#define ADC_SAMPT_SAMPT                          ADC_SAMPT_SAMPT_MASK                               /**< ADC group of channels sampling time */
#define ADC_SAMPT_SAMPT_3CYCLES                  (0x1UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000001 */
#define ADC_SAMPT_SAMPT_7CYCLES                  (0x2UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000002 */
#define ADC_SAMPT_SAMPT_12CYCLES                 (0x3UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000003 */
#define ADC_SAMPT_SAMPT_19CYCLES                 (0x4UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000004 */
#define ADC_SAMPT_SAMPT_39CYCLES                 (0x5UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000005 */
#define ADC_SAMPT_SAMPT_79CYCLES                 (0x6UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000006 */
#define ADC_SAMPT_SAMPT_119CYCLES                (0x7UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000007 */
#define ADC_SAMPT_SAMPT_159CYCLES                (0x8UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000008 */
#define ADC_SAMPT_SAMPT_239CYCLES                (0x9UL << ADC_SAMPT_SAMPT_POS)                     /**< 0x00000009 */
#define ADC_SAMPT_SAMPT_319CYCLES                (0xAUL << ADC_SAMPT_SAMPT_POS)                     /**< 0x0000000A */
#define ADC_SAMPT_SAMPT_479CYCLES                (0xBUL << ADC_SAMPT_SAMPT_POS)                     /**< 0x0000000B */
#define ADC_SAMPT_SAMPT_639CYCLES                (0xCUL << ADC_SAMPT_SAMPT_POS)                     /**< 0x0000000C */
#define ADC_SAMPT_SAMPT_959CYCLES                (0xDUL << ADC_SAMPT_SAMPT_POS)                     /**< 0x0000000D */
#define ADC_SAMPT_SAMPT_1279CYCLES               (0xEUL << ADC_SAMPT_SAMPT_POS)                     /**< 0x0000000E */
#define ADC_SAMPT_SAMPT_1919CYCLES               (0xFUL << ADC_SAMPT_SAMPT_POS)                     /**< 0x0000000F */

/* Bits for ADC_CHCFG */
#define ADC_CHCFG_CHN_POS                        (0U)
#define ADC_CHCFG_CHN_MASK                       (0x7FFUL << ADC_CHCFG_CHN_POS)                     /**< 0x000007FF */
#define ADC_CHCFG_CHN                            ADC_CHCFG_CHN_MASK                                 /**< ADC group regular sequencer channels */
#define ADC_CHCFG_CHN0_POS                       (0U)
#define ADC_CHCFG_CHN0_MASK                      (0x1UL << ADC_CHCFG_CHN0_POS)                      /**< 0x00000001 */
#define ADC_CHCFG_CHN0                           ADC_CHCFG_CHN0_MASK                                /**< ADC group regular sequencer channel 0 */
#define ADC_CHCFG_CHN1_POS                       (1U)
#define ADC_CHCFG_CHN1_MASK                      (0x1UL << ADC_CHCFG_CHN1_POS)                      /**< 0x00000002 */
#define ADC_CHCFG_CHN1                           ADC_CHCFG_CHN1_MASK                                /**< ADC group regular sequencer channel 1 */
#define ADC_CHCFG_CHN2_POS                       (2U)
#define ADC_CHCFG_CHN2_MASK                      (0x1UL << ADC_CHCFG_CHN2_POS)                      /**< 0x00000004 */
#define ADC_CHCFG_CHN2                           ADC_CHCFG_CHN2_MASK                                /**< ADC group regular sequencer channel 2 */
#define ADC_CHCFG_CHN3_POS                       (3U)
#define ADC_CHCFG_CHN3_MASK                      (0x1UL << ADC_CHCFG_CHN3_POS)                      /**< 0x00000008 */
#define ADC_CHCFG_CHN3                           ADC_CHCFG_CHN3_MASK                                /**< ADC group regular sequencer channel 3 */
#define ADC_CHCFG_CHN5_POS                       (5U)
#define ADC_CHCFG_CHN5_MASK                      (0x1UL << ADC_CHCFG_CHN5_POS)                      /**< 0x00000020 */
#define ADC_CHCFG_CHN5                           ADC_CHCFG_CHN5_MASK                                /**< ADC group regular sequencer channel 5 */
#define ADC_CHCFG_CHN6_POS                       (6U)
#define ADC_CHCFG_CHN6_MASK                      (0x1UL << ADC_CHCFG_CHN6_POS)                      /**< 0x00000040 */
#define ADC_CHCFG_CHN6                           ADC_CHCFG_CHN6_MASK                                /**< ADC group regular sequencer channel 6 */
#define ADC_CHCFG_CHN7_POS                       (7U)
#define ADC_CHCFG_CHN7_MASK                      (0x1UL << ADC_CHCFG_CHN7_POS)                      /**< 0x00000080 */
#define ADC_CHCFG_CHN7                           ADC_CHCFG_CHN7_MASK                                /**< ADC group regular sequencer channel 7 */
#define ADC_CHCFG_CHN8_POS                       (8U)
#define ADC_CHCFG_CHN8_MASK                      (0x1UL << ADC_CHCFG_CHN8_POS)                      /**< 0x00000100 */
#define ADC_CHCFG_CHN8                           ADC_CHCFG_CHN8_MASK                                /**< ADC group regular sequencer channel 8 */
#define ADC_CHCFG_CHN9_POS                       (9U)
#define ADC_CHCFG_CHN9_MASK                      (0x1UL << ADC_CHCFG_CHN9_POS)                      /**< 0x00000200 */
#define ADC_CHCFG_CHN9                           ADC_CHCFG_CHN9_MASK                                /**< ADC group regular sequencer channel 9 */
#define ADC_CHCFG_CHN10_POS                      (10U)
#define ADC_CHCFG_CHN10_MASK                     (0x1UL << ADC_CHCFG_CHN10_POS)                     /**< 0x00000400 */
#define ADC_CHCFG_CHN10                          ADC_CHCFG_CHN10_MASK                               /**< ADC group regular sequencer channel 10 */

/* Bits for ADC_AWDGCR */
#define ADC_AWDGCR_CHN_POS                       (0U)
#define ADC_AWDGCR_CHN_MASK                      (0x7FFUL << ADC_AWDGCR_CHN_POS)                    /**< 0x000001FF */
#define ADC_AWDGCR_CHN                           ADC_AWDGCR_CHN_MASK                                /**< ADC analog watchdog monitored channel selection */
#define ADC_AWDGCR_CHN0_POS                      (0U)
#define ADC_AWDGCR_CHN0_MASK                     (0x1UL << ADC_AWDGCR_CHN0_POS)                     /**< 0x00000001 */
#define ADC_AWDGCR_CHN0                          ADC_AWDGCR_CHN0_MASK                               /**< ADC analog watchdog monitored channel 0 */
#define ADC_AWDGCR_CHN1_POS                      (1U)
#define ADC_AWDGCR_CHN1_MASK                     (0x1UL << ADC_AWDGCR_CHN1_POS)                     /**< 0x00000002 */
#define ADC_AWDGCR_CHN1                          ADC_AWDGCR_CHN1_MASK                               /**< ADC analog watchdog monitored channel 1 */
#define ADC_AWDGCR_CHN2_POS                      (2U)
#define ADC_AWDGCR_CHN2_MASK                     (0x1UL << ADC_AWDGCR_CHN2_POS)                     /**< 0x00000004 */
#define ADC_AWDGCR_CHN2                          ADC_AWDGCR_CHN2_MASK                               /**< ADC analog watchdog monitored channel 2 */
#define ADC_AWDGCR_CHN3_POS                      (3U)
#define ADC_AWDGCR_CHN3_MASK                     (0x1UL << ADC_AWDGCR_CHN3_POS)                     /**< 0x00000008 */
#define ADC_AWDGCR_CHN3                          ADC_AWDGCR_CHN3_MASK                               /**< ADC analog watchdog monitored channel 3 */
#define ADC_AWDGCR_CHN5_POS                      (5U)
#define ADC_AWDGCR_CHN5_MASK                     (0x1UL << ADC_AWDGCR_CHN5_POS)                     /**< 0x00000020 */
#define ADC_AWDGCR_CHN5                          ADC_AWDGCR_CHN5_MASK                               /**< ADC analog watchdog monitored channel 5 */
#define ADC_AWDGCR_CHN6_POS                      (6U)
#define ADC_AWDGCR_CHN6_MASK                     (0x1UL << ADC_AWDGCR_CHN6_POS)                     /**< 0x00000040 */
#define ADC_AWDGCR_CHN6                          ADC_AWDGCR_CHN6_MASK                               /**< ADC analog watchdog monitored channel 6 */
#define ADC_AWDGCR_CHN7_POS                      (7U)
#define ADC_AWDGCR_CHN7_MASK                     (0x1UL << ADC_AWDGCR_CHN7_POS)                     /**< 0x00000080 */
#define ADC_AWDGCR_CHN7                          ADC_AWDGCR_CHN7_MASK                               /**< ADC analog watchdog monitored channel 7 */
#define ADC_AWDGCR_CHN8_POS                      (8U)
#define ADC_AWDGCR_CHN8_MASK                     (0x1UL << ADC_AWDGCR_CHN8_POS)                     /**< 0x00000100 */
#define ADC_AWDGCR_CHN8                          ADC_AWDGCR_CHN8_MASK                               /**< ADC analog watchdog monitored channel 8 */
#define ADC_AWDGCR_CHN9_POS                      (9U)
#define ADC_AWDGCR_CHN9_MASK                     (0x1UL << ADC_AWDGCR_CHN9_POS)                     /**< 0x00000200 */
#define ADC_AWDGCR_CHN9                          ADC_AWDGCR_CHN9_MASK                               /**< ADC analog watchdog monitored channel 9 */
#define ADC_AWDGCR_CHN10_POS                     (10U)
#define ADC_AWDGCR_CHN10_MASK                    (0x1UL << ADC_AWDGCR_CHN10_POS)                    /**< 0x00000400 */
#define ADC_AWDGCR_CHN10                         ADC_AWDGCR_CHN10_MASK                              /**< ADC analog watchdog monitored channel 10 */

/* Bits for ADC_AWDGTR */
#define ADC_AWDGTR_AWDG_LT_POS                   (0U)
#define ADC_AWDGTR_AWDG_LT_MASK                  (0xFFFUL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000FFF */
#define ADC_AWDGTR_AWDG_LT                       ADC_AWDGTR_AWDG_LT_MASK                            /**< ADC analog watchdog threshold low */
#define ADC_AWDGTR_AWDG_LT_0                     (0x001UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000001 */
#define ADC_AWDGTR_AWDG_LT_1                     (0x002UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000002 */
#define ADC_AWDGTR_AWDG_LT_2                     (0x004UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000004 */
#define ADC_AWDGTR_AWDG_LT_3                     (0x008UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000008 */
#define ADC_AWDGTR_AWDG_LT_4                     (0x010UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000010 */
#define ADC_AWDGTR_AWDG_LT_5                     (0x020UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000020 */
#define ADC_AWDGTR_AWDG_LT_6                     (0x040UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000040 */
#define ADC_AWDGTR_AWDG_LT_7                     (0x080UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000080 */
#define ADC_AWDGTR_AWDG_LT_8                     (0x100UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000100 */
#define ADC_AWDGTR_AWDG_LT_9                     (0x200UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000200 */
#define ADC_AWDGTR_AWDG_LT_10                    (0x400UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000400 */
#define ADC_AWDGTR_AWDG_LT_11                    (0x800UL << ADC_AWDGTR_AWDG_LT_POS)                /**< 0x00000800 */
#define ADC_AWDGTR_AWDG_HT_POS                   (16U)
#define ADC_AWDGTR_AWDG_HT_MASK                  (0xFFFUL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x0FFF0000 */
#define ADC_AWDGTR_AWDG_HT                       ADC_AWDGTR_AWDG_HT_MASK                            /**< ADC Analog watchdog threshold high */

#define ADC_AWDGTR_AWDG_HT_0                     (0x001UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x00010000 */
#define ADC_AWDGTR_AWDG_HT_1                     (0x002UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x00020000 */
#define ADC_AWDGTR_AWDG_HT_2                     (0x004UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x00040000 */
#define ADC_AWDGTR_AWDG_HT_3                     (0x008UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x00080000 */
#define ADC_AWDGTR_AWDG_HT_4                     (0x010UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x00100000 */
#define ADC_AWDGTR_AWDG_HT_5                     (0x020UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x00200000 */
#define ADC_AWDGTR_AWDG_HT_6                     (0x040UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x00400000 */
#define ADC_AWDGTR_AWDG_HT_7                     (0x080UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x00800000 */
#define ADC_AWDGTR_AWDG_HT_8                     (0x100UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x01000000 */
#define ADC_AWDGTR_AWDG_HT_9                     (0x200UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x02000000 */
#define ADC_AWDGTR_AWDG_HT_10                    (0x400UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x04000000 */
#define ADC_AWDGTR_AWDG_HT_11                    (0x800UL << ADC_AWDGTR_AWDG_HT_POS)                /**< 0x08000000 */
/* Bits for ADC_CALFACT */
#define ADC_CALFACT_CALFACT_POS                  (0U)
#define ADC_CALFACT_CALFACT_MASK                 (0x3FUL << ADC_CALFACT_CALFACT_POS)                /**< 0x0000003F */
#define ADC_CALFACT_CALFACT                      ADC_CALFACT_CALFACT_MASK                           /**< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_0                    (0x01UL << ADC_CALFACT_CALFACT_POS)                /**< 0x00000001 */
#define ADC_CALFACT_CALFACT_1                    (0x02UL << ADC_CALFACT_CALFACT_POS)                /**< 0x00000002 */
#define ADC_CALFACT_CALFACT_2                    (0x04UL << ADC_CALFACT_CALFACT_POS)                /**< 0x00000004 */
#define ADC_CALFACT_CALFACT_3                    (0x08UL << ADC_CALFACT_CALFACT_POS)                /**< 0x00000008 */
#define ADC_CALFACT_CALFACT_4                    (0x10UL << ADC_CALFACT_CALFACT_POS)                /**< 0x00000010 */
#define ADC_CALFACT_CALFACT_5                    (0x20UL << ADC_CALFACT_CALFACT_POS)                /**< 0x00000020 */

/* Bits for ADC_DR */
#define ADC_DR_DATA_POS                          (0U)
#define ADC_DR_DATA_MASK                         (0xFFFUL << ADC_DR_DATA_POS)                       /**< 0x00000FFF */
#define ADC_DR_DATA                              ADC_DR_DATA_MASK                                   /**< ADC group regular conversion data */

/* Bits for ADC_CFG3 */
#define ADC_CFG3_MODE_POS                       (1U)
#define ADC_CFG3_MODE_MASK                      (0x1UL << ADC_CFG3_MODE_POS)                        /**< 0x00000002         */
#define ADC_CFG3_MODE                           ADC_CFG3_MODE_MASK                                  /**< ADC mode selection */


/*-----------------------------------------------------------------------------------------------
                                       COMP  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for COMP_CR */
#define COMP_CR_RDACDIV_POS                       (0U)
#define COMP_CR_RDACDIV_MASK                      (0x7UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000007 */
#define COMP_CR_RDACDIV                           COMP_CR_RDACDIV_MASK                             /**< Comparator internal RDAC divide selection */
#define COMP_CR_RDACDIV_1DIV8                     (0x0UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000000 */
#define COMP_CR_RDACDIV_2DIV8                     (0x1UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000001 */
#define COMP_CR_RDACDIV_3DIV8                     (0x2UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000002 */
#define COMP_CR_RDACDIV_4DIV8                     (0x3UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000003 */
#define COMP_CR_RDACDIV_5DIV8                     (0x4UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000004 */
#define COMP_CR_RDACDIV_6DIV8                     (0x5UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000005 */
#define COMP_CR_RDACDIV_7DIV8                     (0x6UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000006 */
#define COMP_CR_RDACDIV_8DIV8                     (0x7UL << COMP_CR_RDACDIV_POS)                   /**< 0x00000007 */
#define COMP_CR_VCSEL_POS                         (6U)
#define COMP_CR_VCSEL_MASK                        (0x1UL << COMP_CR_VCSEL_POS)                     /**< 0x00010000 */
#define COMP_CR_VCSEL                             COMP_CR_VCSEL_MASK                               /**< Comparator internal reference voltage selection */
#define COMP_CR_RDACEN_POS                        (15U)
#define COMP_CR_RDACEN_MASK                       (0x1UL << COMP_CR_RDACEN_POS)                    /**< 0x00000100 */
#define COMP_CR_RDACEN                            COMP_CR_RDACEN_MASK                              /**< Comparator internal RDAC enable                 */

/* Bits for COMP_CSR1 */
#define COMP_CSR1_EN_POS                          (0U)
#define COMP_CSR1_EN_MASK                         (0x1UL << COMP_CSR1_EN_POS)                      /**< 0x00000001 */
#define COMP_CSR1_EN                              COMP_CSR1_EN_MASK                                /**< Comparator enable */
#define COMP_CSR1_INM_POS                         (4U)
#define COMP_CSR1_INM_MASK                        (0x3UL << COMP_CSR1_INM_POS)                     /**< 0x00000010 */
#define COMP_CSR1_INM                             COMP_CSR1_INM_MASK                               /**< Comparator input minus selection           */
#define COMP_CSR1_INM_VRDAC_OUT                   (0x0UL << COMP_CSR1_INM_POS)                     /**< 0x00000000 */
#define COMP_CSR1_INM_IO1                         (0x1UL << COMP_CSR1_INM_POS)                     /**< 0x00000010 */
#define COMP_CSR1_INM_IO2                         (0x2UL << COMP_CSR1_INM_POS)                     /**< 0x00000020 */
#define COMP_CSR1_INP_POS                         (8U)
#define COMP_CSR1_INP_MASK                        (0x3UL << COMP_CSR1_INP_POS)                     /**< 0x00000300 */
#define COMP_CSR1_INP                             COMP_CSR1_INP_MASK                               /**< Comparator input plus selection            */
#define COMP_CSR1_INP_VRDAC_OUT                   (0x0UL << COMP_CSR1_INP_POS)                     /**< 0x00000000 */
#define COMP_CSR1_INP_IO1                         (0x1UL << COMP_CSR1_INP_POS)                     /**< 0x00000100 */
#define COMP_CSR1_INP_IO2                         (0x2UL << COMP_CSR1_INP_POS)                     /**< 0x00000200 */
#define COMP_CSR1_INP_IO3                         (0x3UL << COMP_CSR1_INP_POS)                     /**< 0x00000300 */
#define COMP_CSR1_INPMOD_POS                      (13U)
#define COMP_CSR1_INPMOD_MASK                     (0x1UL << COMP_CSR1_INPMOD_POS)                  /**< 0x00002000 */
#define COMP_CSR1_INPMOD                          COMP_CSR1_INPMOD_MASK                            /**< Pair of comparators window mode              */
#define COMP_CSR1_OUTMOD_POS                      (14U)
#define COMP_CSR1_OUTMOD_MASK                     (0x1UL << COMP_CSR1_OUTMOD_POS)                  /**< 0x00004000 */
#define COMP_CSR1_OUTMOD                          COMP_CSR1_OUTMOD_MASK                            /**< Pair of comparators window output level      */
#define COMP_CSR1_POL_POS                         (15U)
#define COMP_CSR1_POL_MASK                        (0x1UL << COMP_CSR1_POL_POS)                     /**< 0x00008000 */
#define COMP_CSR1_POL                             COMP_CSR1_POL_MASK                               /**< Comparator output polarity                   */
#define COMP_CSR1_HYST_POS                        (16U)
#define COMP_CSR1_HYST_MASK                       (0x1UL << COMP_CSR1_HYST_POS)                    /**< 0x00010000 */
#define COMP_CSR1_HYST                            COMP_CSR1_HYST_MASK                              /**< Comparator input hysteresis function control */
#define COMP_CSR1_SPEED_POS                       (18U)
#define COMP_CSR1_SPEED_MASK                      (0x1UL << COMP_CSR1_SPEED_POS)                   /**< 0x00040000 */
#define COMP_CSR1_SPEED                           COMP_CSR1_SPEED_MASK                             /**< Comparator speed mode */
#define COMP_CSR1_HIGH_SPEED                      (0x0UL << COMP_CSR1_SPEED_POS)                   /**< 0x00000000 */
#define COMP_CSR1_LOW_SPEED                       (0x1UL << COMP_CSR1_SPEED_POS)                   /**< 0x00040000 */
#define COMP_CSR1_FLTCLK_POS                      (22U)
#define COMP_CSR1_FLTCLK_MASK                     (0x3UL << COMP_CSR1_FLTCLK_POS)                  /**< 0x00C00000 */
#define COMP_CSR1_FLTCLK                          COMP_CSR1_FLTCLK_MASK                            /**< Comparator filtering clock */
#define COMP_CSR1_FLTCLK_PCLK                     (0x0UL << COMP_CSR1_FLTCLK_POS)                  /**< 0x00000000 */
#define COMP_CSR1_FLTCLK_RCL                      (0x1UL << COMP_CSR1_FLTCLK_POS)                  /**< 0x00400000 */
#define COMP_CSR1_FLTCLK_LXTAL                    (0x2UL << COMP_CSR1_FLTCLK_POS)                  /**< 0x00800000 */
#define COMP_CSR1_FLTIME_POS                      (25U)
#define COMP_CSR1_FLTIME_MASK                     (0x7UL << COMP_CSR1_FLTIME_POS)                  /**< 0x0E000000 */
#define COMP_CSR1_FLTIME                          COMP_CSR1_FLTIME_MASK                            /**< Comparator filtering time */
#define COMP_CSR1_FLTIME_2CYCLE                   (0x0UL << COMP_CSR1_FLTIME_POS)                  /**< 0x00000000 */
#define COMP_CSR1_FLTIME_4CYCLE                   (0x1UL << COMP_CSR1_FLTIME_POS)                  /**< 0x02000000 */
#define COMP_CSR1_FLTIME_8CYCLE                   (0x2UL << COMP_CSR1_FLTIME_POS)                  /**< 0x04000000 */
#define COMP_CSR1_FLTIME_16CYCLE                  (0x3UL << COMP_CSR1_FLTIME_POS)                  /**< 0x06000000 */
#define COMP_CSR1_FLTIME_32CYCLE                  (0x4UL << COMP_CSR1_FLTIME_POS)                  /**< 0x08000000 */
#define COMP_CSR1_FLTIME_64CYCLE                  (0x5UL << COMP_CSR1_FLTIME_POS)                  /**< 0x0A000000 */
#define COMP_CSR1_FLTIME_256CYCLE                 (0x6UL << COMP_CSR1_FLTIME_POS)                  /**< 0x0C000000 */
#define COMP_CSR1_FLTIME_1024CYCLE                (0x7UL << COMP_CSR1_FLTIME_POS)                  /**< 0x0E000000 */
#define COMP_CSR1_FLTEN_POS                       (28U)
#define COMP_CSR1_FLTEN_MASK                      (0x1UL << COMP_CSR1_FLTEN_POS)                   /**< 0x10000000                  */
#define COMP_CSR1_FLTEN                           COMP_CSR1_FLTEN_MASK                             /**< Comparator filtering enable */
#define COMP_CSR1_VAL_POS                         (30U)
#define COMP_CSR1_VAL_MASK                        (0x1UL << COMP_CSR1_VAL_POS)                     /**< 0x40000000                  */
#define COMP_CSR1_VAL                             COMP_CSR1_VAL_MASK                               /**< Comparator output level     */

/* Bits for COMP_CSR2 */
#define COMP_CSR2_ENSEL_POS                       (0U)
#define COMP_CSR2_ENSEL_MASK                      (0x3UL << COMP_CSR2_ENSEL_POS)                   /**< 0x00000003 */
#define COMP_CSR2_ENSEL                           COMP_CSR2_ENSEL_MASK                             /**< Comparator enable select */
#define COMP_CSR2_ENSEL_EN                        (0x0UL << COMP_CSR2_ENSEL_POS)                   /**< 0x00000000 */
#define COMP_CSR2_ENSEL_TIM3_OC1                  (0x1UL << COMP_CSR2_ENSEL_POS)                   /**< 0x00000001 */
#define COMP_CSR2_ENSEL_TIM3_OC2                  (0x2UL << COMP_CSR2_ENSEL_POS)                   /**< 0x00000002 */
#define COMP_CSR2_FALLEN_POS                      (8U)
#define COMP_CSR2_FALLEN_MASK                     (0x1UL << COMP_CSR2_FALLEN_POS)                  /**< 0x00000100 */
#define COMP_CSR2_FALLEN                          COMP_CSR2_FALLEN_MASK                            /**< Comparator falling trigger configuration */
#define COMP_CSR2_RISEEN_POS                      (9U)
#define COMP_CSR2_RISEEN_MASK                     (0x1UL << COMP_CSR2_RISEEN_POS)                  /**< 0x00000200 */
#define COMP_CSR2_RISEEN                          COMP_CSR2_RISEEN_MASK                            /**< Comparator rising trigger configuration */
#define COMP_CSR2_IE_POS                          (15U)
#define COMP_CSR2_IE_MASK                         (0x1UL << COMP_CSR2_IE_POS)                      /**< 0x00008000 */
#define COMP_CSR2_IE                              COMP_CSR2_IE_MASK                                /**< Comparator interrupt mask */
#define COMP_CSR2_TIMSTOP1_POS                    (16U)
#define COMP_CSR2_TIMSTOP1_MASK                   (0x1UL << COMP_CSR2_TIMSTOP1_POS)                /**< 0x00010000 */
#define COMP_CSR2_TIMSTOP1                        COMP_CSR2_TIMSTOP1_MASK                          /**< Comparator control TIM3_OC1 PWM */
#define COMP_CSR2_TIMSTOP2_POS                    (17U)
#define COMP_CSR2_TIMSTOP2_MASK                   (0x1UL << COMP_CSR2_TIMSTOP2_POS)                /**< 0x00020000 */
#define COMP_CSR2_TIMSTOP2                        COMP_CSR2_TIMSTOP2_MASK                          /**< Comparator control TIM3_OC2 PWM */

/* Bits for COMP_SR */
#define COMP_SR_INTF_POS                          (0U)
#define COMP_SR_INTF_MASK                         (0x1UL << COMP_SR_INTF_POS)                      /**< 0x00000001 */
#define COMP_SR_INTF                              COMP_SR_INTF_MASK                                /**< Comparator interrupt flag */
/*-----------------------------------------------------------------------------------------------
                                       CRC  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for CRC_CSR */
#define CRC_CSR_OUT_XOR_POS                      (2U)
#define CRC_CSR_OUT_XOR_MASK                     (0x1UL << CRC_CSR_OUT_XOR_POS)                     /**< 0x00000004 */
#define CRC_CSR_OUT_XOR                          CRC_CSR_OUT_XOR_MASK                               /**< Output Exclusive OR bit       */
#define CRC_CSR_DATA_REV_POS                     (3U)
#define CRC_CSR_DATA_REV_MASK                    (0x1UL << CRC_CSR_DATA_REV_POS)                    /**< 0x00000008 */
#define CRC_CSR_DATA_REV                         CRC_CSR_DATA_REV_MASK                              /**< Reverse input and output data */

/* Bits for CRC_RDR */
#define CRC_RDR_RESULT_POS                       (0U)
#define CRC_RDR_RESULT_MASK                      (0xFFFFUL << CRC_RDR_RESULT_POS)                   /**< 0x0000FFFF */
#define CRC_RDR_RESULT                           CRC_RDR_RESULT_MASK                                /**< Result data register bits     */

/* Bits for CRC_DR */
#define CRC_DR_DATA_POS                          (0U)
#define CRC_DR_DATA_MASK                         (0xFFUL << CRC_DR_DATA_POS)                        /**< 0x000000FF */
#define CRC_DR_DATA                              CRC_DR_DATA_MASK                                   /**< Data register bits            */


/*-----------------------------------------------------------------------------------------------
                                       DBG  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for DBG_CR */
#define DBG_CR_DBG_STOP_POS                      (0U)
#define DBG_CR_DBG_STOP_MASK                     (0x1UL << DBG_CR_DBG_STOP_POS)                     /**< 0x00000001 */
#define DBG_CR_DBG_STOP                          DBG_CR_DBG_STOP_MASK                               /**< Debug options in Stop mode */

/* Bits for DBG_APB_FZ1 */
#define DBG_APB_FZ1_TIM3_HOLD_POS                (1U)
#define DBG_APB_FZ1_TIM3_HOLD_MASK               (0x1UL << DBG_APB_FZ1_TIM3_HOLD_POS)               /**< 0x00000002 */
#define DBG_APB_FZ1_TIM3_HOLD                    DBG_APB_FZ1_TIM3_HOLD_MASK                         /**< Clocking of TIM3 counter when the core is halted   */
#define DBG_APB_FZ1_TIM8_HOLD_POS                (6U)
#define DBG_APB_FZ1_TIM8_HOLD_MASK               (0x1UL << DBG_APB_FZ1_TIM8_HOLD_POS)               /**< 0x00000040 */
#define DBG_APB_FZ1_TIM8_HOLD                    DBG_APB_FZ1_TIM8_HOLD_MASK                         /**< Clocking of TIM8 counter when the core is halted   */
#define DBG_APB_FZ1_RTC_HOLD_POS                 (16U)
#define DBG_APB_FZ1_RTC_HOLD_MASK                (0x1UL << DBG_APB_FZ1_RTC_HOLD_POS)                /**< 0x00010000 */
#define DBG_APB_FZ1_RTC_HOLD                     DBG_APB_FZ1_RTC_HOLD_MASK                          /**< Clocking of RTC counter when the core is halted    */
#define DBG_APB_FZ1_IWDG_HOLD_POS                (18U)
#define DBG_APB_FZ1_IWDG_HOLD_MASK               (0x1UL << DBG_APB_FZ1_IWDG_HOLD_POS)               /**< 0x00040000 */
#define DBG_APB_FZ1_IWDG_HOLD                    DBG_APB_FZ1_IWDG_HOLD_MASK                         /**< Clocking of IWDG counter when the core is halted   */
#define DBG_APB_FZ1_LPTIM1_HOLD_POS              (29U)
#define DBG_APB_FZ1_LPTIM1_HOLD_MASK             (0x1UL << DBG_APB_FZ1_LPTIM1_HOLD_POS)             /**< 0x20000000 */
#define DBG_APB_FZ1_LPTIM1_HOLD                  DBG_APB_FZ1_LPTIM1_HOLD_MASK                       /**< Clocking of LPTIM1 counter when the core is halted */

/* Bits for DBG_APB_FZ2 */
#define DBG_APB_FZ2_TIM1_HOLD_POS                (0U)
#define DBG_APB_FZ2_TIM1_HOLD_MASK               (0x1UL << DBG_APB_FZ2_TIM1_HOLD_POS)               /**< 0x00000001 */
#define DBG_APB_FZ2_TIM1_HOLD                    DBG_APB_FZ2_TIM1_HOLD_MASK                         /**< Clocking of TIM1 counter when the core is halted   */


/*-----------------------------------------------------------------------------------------------
                                       DMA  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for DMA_ISR */
#define DMA_ISR_G0_POS                           (0U)
#define DMA_ISR_G0_MASK                          (0x1UL << DMA_ISR_G0_POS)                          /**< 0x00000001 */
#define DMA_ISR_G0                               DMA_ISR_G0_MASK                                    /**< Channel 0 global interrupt flag    */
#define DMA_ISR_TF0_POS                          (1U)
#define DMA_ISR_TF0_MASK                         (0x1UL << DMA_ISR_TF0_POS)                         /**< 0x00000002 */
#define DMA_ISR_TF0                              DMA_ISR_TF0_MASK                                   /**< Channel 0 transfer complete flag   */
#define DMA_ISR_TH0_POS                          (2U)
#define DMA_ISR_TH0_MASK                         (0x1UL << DMA_ISR_TH0_POS)                         /**< 0x00000004 */
#define DMA_ISR_TH0                              DMA_ISR_TH0_MASK                                   /**< Channel 0 half transfer flag       */
#define DMA_ISR_TE0_POS                          (3U)
#define DMA_ISR_TE0_MASK                         (0x1UL << DMA_ISR_TE0_POS)                         /**< 0x00000008 */
#define DMA_ISR_TE0                              DMA_ISR_TE0_MASK                                   /**< Channel 0 transfer Error flag      */
#define DMA_ISR_G1_POS                           (4U)
#define DMA_ISR_G1_MASK                          (0x1UL << DMA_ISR_G1_POS)                          /**< 0x00000010 */
#define DMA_ISR_G1                               DMA_ISR_G1_MASK                                    /**< Channel 1 global interrupt flag    */
#define DMA_ISR_TF1_POS                          (5U)
#define DMA_ISR_TF1_MASK                         (0x1UL << DMA_ISR_TF1_POS)                         /**< 0x00000020 */
#define DMA_ISR_TF1                              DMA_ISR_TF1_MASK                                   /**< Channel 1 transfer complete flag   */
#define DMA_ISR_TH1_POS                          (6U)
#define DMA_ISR_TH1_MASK                         (0x1UL << DMA_ISR_TH1_POS)                         /**< 0x00000040 */
#define DMA_ISR_TH1                              DMA_ISR_TH1_MASK                                   /**< Channel 1 half transfer flag       */
#define DMA_ISR_TE1_POS                          (7U)
#define DMA_ISR_TE1_MASK                         (0x1UL << DMA_ISR_TE1_POS)                         /**< 0x00000080 */
#define DMA_ISR_TE1                              DMA_ISR_TE1_MASK                                   /**< Channel 1 transfer error flag      */
#define DMA_ISR_G2_POS                           (8U)
#define DMA_ISR_G2_MASK                          (0x1UL << DMA_ISR_G2_POS)                          /**< 0x00000100 */
#define DMA_ISR_G2                               DMA_ISR_G2_MASK                                    /**< Channel 2 global interrupt flag    */
#define DMA_ISR_TF2_POS                          (9U)
#define DMA_ISR_TF2_MASK                         (0x1UL << DMA_ISR_TF2_POS)                         /**< 0x00000200 */
#define DMA_ISR_TF2                              DMA_ISR_TF2_MASK                                   /**< Channel 2 transfer complete flag   */
#define DMA_ISR_TH2_POS                          (10U)
#define DMA_ISR_TH2_MASK                         (0x1UL << DMA_ISR_TH2_POS)                         /**< 0x00000400 */
#define DMA_ISR_TH2                              DMA_ISR_TH2_MASK                                   /**< Channel 2 half transfer flag       */
#define DMA_ISR_TE2_POS                          (11U)
#define DMA_ISR_TE2_MASK                         (0x1UL << DMA_ISR_TE2_POS)                         /**< 0x00000800 */
#define DMA_ISR_TE2                              DMA_ISR_TE2_MASK                                   /**< Channel 2 transfer error flag      */

/* Bits for DMA_ICR */
#define DMA_ICR_GCF0_POS                         (0U)
#define DMA_ICR_GCF0_MASK                        (0x1UL << DMA_ICR_GCF0_POS)                        /**< 0x00000001 */
#define DMA_ICR_GCF0                             DMA_ICR_GCF0_MASK                                  /**< Channel 0 global interrupt clear   */
#define DMA_ICR_TFCF0_POS                        (1U)
#define DMA_ICR_TFCF0_MASK                       (0x1UL << DMA_ICR_TFCF0_POS)                       /**< 0x00000002 */
#define DMA_ICR_TFCF0                            DMA_ICR_TFCF0_MASK                                 /**< Channel 0 transfer complete clear  */
#define DMA_ICR_THCF0_POS                        (2U)
#define DMA_ICR_THCF0_MASK                       (0x1UL << DMA_ICR_THCF0_POS)                       /**< 0x00000004 */
#define DMA_ICR_THCF0                            DMA_ICR_THCF0_MASK                                 /**< Channel 0 half transfer clear      */
#define DMA_ICR_TECF0_POS                        (3U)
#define DMA_ICR_TECF0_MASK                       (0x1UL << DMA_ICR_TECF0_POS)                       /**< 0x00000008 */
#define DMA_ICR_TECF0                            DMA_ICR_TECF0_MASK                                 /**< Channel 0 transfer error clear     */
#define DMA_ICR_GCF1_POS                         (4U)
#define DMA_ICR_GCF1_MASK                        (0x1UL << DMA_ICR_GCF1_POS)                        /**< 0x00000010 */
#define DMA_ICR_GCF1                             DMA_ICR_GCF1_MASK                                  /**< Channel 1 global interrupt clear   */
#define DMA_ICR_TFCF1_POS                        (5U)
#define DMA_ICR_TFCF1_MASK                       (0x1UL << DMA_ICR_TFCF1_POS)                       /**< 0x00000020 */
#define DMA_ICR_TFCF1                            DMA_ICR_TFCF1_MASK                                 /**< Channel 1 transfer complete clear  */
#define DMA_ICR_THCF1_POS                        (6U)
#define DMA_ICR_THCF1_MASK                       (0x1UL << DMA_ICR_THCF1_POS)                       /**< 0x00000040 */
#define DMA_ICR_THCF1                            DMA_ICR_THCF1_MASK                                 /**< Channel 1 half transfer clear      */
#define DMA_ICR_TECF1_POS                        (7U)
#define DMA_ICR_TECF1_MASK                       (0x1UL << DMA_ICR_TECF1_POS)                       /**< 0x00000080 */
#define DMA_ICR_TECF1                            DMA_ICR_TECF1_MASK                                 /**< Channel 1 transfer error clear     */
#define DMA_ICR_GCF2_POS                         (8U)
#define DMA_ICR_GCF2_MASK                        (0x1UL << DMA_ICR_GCF2_POS)                        /**< 0x00000100 */
#define DMA_ICR_GCF2                             DMA_ICR_GCF2_MASK                                  /**< Channel 2 global interrupt clear   */
#define DMA_ICR_TFCF2_POS                        (9U)
#define DMA_ICR_TFCF2_MASK                       (0x1UL << DMA_ICR_TFCF2_POS)                       /**< 0x00000200 */
#define DMA_ICR_TFCF2                            DMA_ICR_TFCF2_MASK                                 /**< Channel 2 transfer complete clear  */
#define DMA_ICR_THCF2_POS                        (10U)
#define DMA_ICR_THCF2_MASK                       (0x1UL << DMA_ICR_THCF2_POS)                       /**< 0x00000400 */
#define DMA_ICR_THCF2                            DMA_ICR_THCF2_MASK                                 /**< Channel 2 half transfer clear      */
#define DMA_ICR_TECF2_POS                        (11U)
#define DMA_ICR_TECF2_MASK                       (0x1UL << DMA_ICR_TECF2_POS)                       /**< 0x00000800 */
#define DMA_ICR_TECF2                            DMA_ICR_TECF2_MASK                                 /**< Channel 2 transfer error clear     */

/* Bits for DMA_CC */
#define DMA_CC_EN_POS                            (0U)
#define DMA_CC_EN_MASK                           (0x1UL << DMA_CC_EN_POS)                           /**< 0x00000001 */
#define DMA_CC_EN                                DMA_CC_EN_MASK                                     /**< Channel enable */
#define DMA_CC_TFIE_POS                          (1U)
#define DMA_CC_TFIE_MASK                         (0x1UL << DMA_CC_TFIE_POS)                         /**< 0x00000002 */
#define DMA_CC_TFIE                              DMA_CC_TFIE_MASK                                   /**< Transfer complete interrupt enable */
#define DMA_CC_THIE_POS                          (2U)
#define DMA_CC_THIE_MASK                         (0x1UL << DMA_CC_THIE_POS)                         /**< 0x00000004 */
#define DMA_CC_THIE                              DMA_CC_THIE_MASK                                   /**< Half transfer interrupt enable     */
#define DMA_CC_TEIE_POS                          (3U)
#define DMA_CC_TEIE_MASK                         (0x1UL << DMA_CC_TEIE_POS)                         /**< 0x00000008 */
#define DMA_CC_TEIE                              DMA_CC_TEIE_MASK                                   /**< Transfer error interrupt enable    */
#define DMA_CC_DINC_POS                          (4U)
#define DMA_CC_DINC_MASK                         (0x1UL << DMA_CC_DINC_POS)                         /**< 0x00000010 */
#define DMA_CC_DINC                              DMA_CC_DINC_MASK                                   /**< Destination address increment mode */
#define DMA_CC_SINC_POS                          (5U)
#define DMA_CC_SINC_MASK                         (0x1UL << DMA_CC_SINC_POS)                         /**< 0x00000020 */
#define DMA_CC_SINC                              DMA_CC_SINC_MASK                                   /**< Source address increment mode      */
#define DMA_CC_SIZE_POS                          (6U)
#define DMA_CC_SIZE_MASK                         (0x3UL << DMA_CC_SIZE_POS)                         /**< 0x000000C0 */
#define DMA_CC_SIZE                              DMA_CC_SIZE_MASK                                   /**< Transfer data size                 */
#define DMA_CC_SIZE_BYTE                         (0x0 << DMA_CC_SIZE_POS)                           /**< 0x00000000 */
#define DMA_CC_SIZE_HALFWORD                     (0x1 << DMA_CC_SIZE_POS)                           /**< 0x00000040 */
#define DMA_CC_SIZE_WORD                         (0x2 << DMA_CC_SIZE_POS)                           /**< 0x00000080 */
#define DMA_CC_PL_POS                            (8U)
#define DMA_CC_PL_MASK                           (0x3UL << DMA_CC_PL_POS)                           /**< 0x00000300 */
#define DMA_CC_PL                                DMA_CC_PL_MASK                                     /**< Transfer polarity                  */
#define DMA_CC_PL_LOW                            (0x0UL << DMA_CC_PL_POS)                           /**< 0x00000000 */
#define DMA_CC_PL_MEDIUM                         (0x1UL << DMA_CC_PL_POS)                           /**< 0x00000100 */
#define DMA_CC_PL_HIGH                           (0x2UL << DMA_CC_PL_POS)                           /**< 0x00000200 */
#define DMA_CC_PL_VERY_HIGH                      (0x3UL << DMA_CC_PL_POS)                           /**< 0x00000300 */
#define DMA_CC_CIRC_POS                          (11U)
#define DMA_CC_CIRC_MASK                         (0x1UL << DMA_CC_CIRC_POS)                         /**< 0x00000800 */
#define DMA_CC_CIRC                              DMA_CC_CIRC_MASK                                   /**< Circulate mode                     */
#define DMA_CC_TYPE_POS                          (12U)
#define DMA_CC_TYPE_MASK                         (0x1UL << DMA_CC_TYPE_POS)                         /**< 0x00001000 */
#define DMA_CC_TYPE                              DMA_CC_TYPE_MASK                                   /**< DMA transmit type                  */
#define DMA_CC_REQ_ID_POS                        (16U)
#define DMA_CC_REQ_ID_MASK                       (0x1FUL << DMA_CC_REQ_ID_POS)                      /**< 0x001F0000 */
#define DMA_CC_REQ_ID                            DMA_CC_REQ_ID_MASK                                 /**< DMA request ID                     */

/* Bits for DMA_CNDTR */
#define DMA_CNDTR_NDT_POS                        (0U)
#define DMA_CNDTR_NDT_MASK                       (0xFFFFUL << DMA_CNDTR_NDT_POS)                    /**< 0x0000FFFF */
#define DMA_CNDTR_NDT                            DMA_CNDTR_NDT_MASK                                 /**< Number of data to transfer         */

/* Bits for DMA_CSAR */
#define DMA_CSAR_SA_POS                          (0U)
#define DMA_CSAR_SA_MASK                         (0xFFFFFFFFUL << DMA_CSAR_SA_POS)                  /**< 0xFFFFFFFF */
#define DMA_CSAR_SA                              DMA_CSAR_SA_MASK                                   /**< Source address                     */

/* Bits for DMA_CDAR */
#define DMA_CDAR_DA_POS                          (0U)
#define DMA_CDAR_DA_MASK                         (0xFFFFFFFFUL << DMA_CDAR_DA_POS)                  /**< 0xFFFFFFFF */
#define DMA_CDAR_DA                              DMA_CDAR_DA_MASK                                   /**< Destination address                */


/*-----------------------------------------------------------------------------------------------
                                       EXTI  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for EXTI_RTSR */
#define EXTI_RTSR_RT0_POS                        (0U)
#define EXTI_RTSR_RT0_MASK                       (0x1UL << EXTI_RTSR_RT0_POS)                       /**< 0x00000001 */
#define EXTI_RTSR_RT0                            EXTI_RTSR_RT0_MASK                                 /**< Rising trigger configuration for input line 0 */
#define EXTI_RTSR_RT1_POS                        (1U)
#define EXTI_RTSR_RT1_MASK                       (0x1UL << EXTI_RTSR_RT1_POS)                       /**< 0x00000002 */
#define EXTI_RTSR_RT1                            EXTI_RTSR_RT1_MASK                                 /**< Rising trigger configuration for input line 1 */
#define EXTI_RTSR_RT2_POS                        (2U)
#define EXTI_RTSR_RT2_MASK                       (0x1UL << EXTI_RTSR_RT2_POS)                       /**< 0x00000004 */
#define EXTI_RTSR_RT2                            EXTI_RTSR_RT2_MASK                                 /**< Rising trigger configuration for input line 2 */
#define EXTI_RTSR_RT3_POS                        (3U)
#define EXTI_RTSR_RT3_MASK                       (0x1UL << EXTI_RTSR_RT3_POS)                       /**< 0x00000008 */
#define EXTI_RTSR_RT3                            EXTI_RTSR_RT3_MASK                                 /**< Rising trigger configuration for input line 3 */
#define EXTI_RTSR_RT4_POS                        (4U)
#define EXTI_RTSR_RT4_MASK                       (0x1UL << EXTI_RTSR_RT4_POS)                       /**< 0x00000010 */
#define EXTI_RTSR_RT4                            EXTI_RTSR_RT4_MASK                                 /**< Rising trigger configuration for input line 4 */
#define EXTI_RTSR_RT5_POS                        (5U)
#define EXTI_RTSR_RT5_MASK                       (0x1UL << EXTI_RTSR_RT5_POS)                       /**< 0x00000020 */
#define EXTI_RTSR_RT5                            EXTI_RTSR_RT5_MASK                                 /**< Rising trigger configuration for input line 5 */
#define EXTI_RTSR_RT6_POS                        (6U)
#define EXTI_RTSR_RT6_MASK                       (0x1UL << EXTI_RTSR_RT6_POS)                       /**< 0x00000040 */
#define EXTI_RTSR_RT6                            EXTI_RTSR_RT6_MASK                                 /**< Rising trigger configuration for input line 6 */
#define EXTI_RTSR_RT7_POS                        (7U)
#define EXTI_RTSR_RT7_MASK                       (0x1UL << EXTI_RTSR_RT7_POS)                       /**< 0x00000080 */
#define EXTI_RTSR_RT7                            EXTI_RTSR_RT7_MASK                                 /**< Rising trigger configuration for input line 7 */
#define EXTI_RTSR_RT8_POS                        (8U)
#define EXTI_RTSR_RT8_MASK                       (0x1UL << EXTI_RTSR_RT8_POS)                       /**< 0x00000100 */
#define EXTI_RTSR_RT8                            EXTI_RTSR_RT8_MASK                                 /**< Rising trigger configuration for input line 8 */
#define EXTI_RTSR_RT9_POS                        (9U)
#define EXTI_RTSR_RT9_MASK                       (0x1UL << EXTI_RTSR_RT9_POS)                       /**< 0x00000200 */
#define EXTI_RTSR_RT9                            EXTI_RTSR_RT9_MASK                                 /**< Rising trigger configuration for input line 9 */

/* Bits for EXTI_FTSR */
#define EXTI_FTSR_FT0_POS                        (0U)
#define EXTI_FTSR_FT0_MASK                       (0x1UL << EXTI_FTSR_FT0_POS)                       /**< 0x00000001 */
#define EXTI_FTSR_FT0                            EXTI_FTSR_FT0_MASK                                 /**< Falling trigger configuration for input line 0 */
#define EXTI_FTSR_FT1_POS                        (1U)
#define EXTI_FTSR_FT1_MASK                       (0x1UL << EXTI_FTSR_FT1_POS)                       /**< 0x00000002 */
#define EXTI_FTSR_FT1                            EXTI_FTSR_FT1_MASK                                 /**< Falling trigger configuration for input line 1 */
#define EXTI_FTSR_FT2_POS                        (2U)
#define EXTI_FTSR_FT2_MASK                       (0x1UL << EXTI_FTSR_FT2_POS)                       /**< 0x00000004 */
#define EXTI_FTSR_FT2                            EXTI_FTSR_FT2_MASK                                 /**< Falling trigger configuration for input line 2 */
#define EXTI_FTSR_FT3_POS                        (3U)
#define EXTI_FTSR_FT3_MASK                       (0x1UL << EXTI_FTSR_FT3_POS)                       /**< 0x00000008 */
#define EXTI_FTSR_FT3                            EXTI_FTSR_FT3_MASK                                 /**< Falling trigger configuration for input line 3 */
#define EXTI_FTSR_FT4_POS                        (4U)
#define EXTI_FTSR_FT4_MASK                       (0x1UL << EXTI_FTSR_FT4_POS)                       /**< 0x00000010 */
#define EXTI_FTSR_FT4                            EXTI_FTSR_FT4_MASK                                 /**< Falling trigger configuration for input line 4 */
#define EXTI_FTSR_FT5_POS                        (5U)
#define EXTI_FTSR_FT5_MASK                       (0x1UL << EXTI_FTSR_FT5_POS)                       /**< 0x00000020 */
#define EXTI_FTSR_FT5                            EXTI_FTSR_FT5_MASK                                 /**< Falling trigger configuration for input line 5 */
#define EXTI_FTSR_FT6_POS                        (6U)
#define EXTI_FTSR_FT6_MASK                       (0x1UL << EXTI_FTSR_FT6_POS)                       /**< 0x00000040 */
#define EXTI_FTSR_FT6                            EXTI_FTSR_FT6_MASK                                 /**< Falling trigger configuration for input line 6 */
#define EXTI_FTSR_FT7_POS                        (7U)
#define EXTI_FTSR_FT7_MASK                       (0x1UL << EXTI_FTSR_FT7_POS)                       /**< 0x00000080 */
#define EXTI_FTSR_FT7                            EXTI_FTSR_FT7_MASK                                 /**< Falling trigger configuration for input line 7 */
#define EXTI_FTSR_FT8_POS                        (8U)
#define EXTI_FTSR_FT8_MASK                       (0x1UL << EXTI_FTSR_FT8_POS)                       /**< 0x00000100 */
#define EXTI_FTSR_FT8                            EXTI_FTSR_FT8_MASK                                 /**< Falling trigger configuration for input line 8 */
#define EXTI_FTSR_FT9_POS                        (9U)
#define EXTI_FTSR_FT9_MASK                       (0x1UL << EXTI_FTSR_FT9_POS)                       /**< 0x00000200 */
#define EXTI_FTSR_FT9                            EXTI_FTSR_FT9_MASK                                 /**< Falling trigger configuration for input line 9 */

/* Bits for EXTI_PIR */
#define EXTI_PIR_PIF0_POS                        (0U)
#define EXTI_PIR_PIF0_MASK                       (0x1UL << EXTI_PIR_PIF0_POS)                        /**< 0x00000001 */
#define EXTI_PIR_PIF0                            EXTI_PIR_PIF0_MASK                                  /**< Rising or Falling pending interrupt flag on line 0 */
#define EXTI_PIR_PIF1_POS                        (1U)
#define EXTI_PIR_PIF1_MASK                       (0x1UL << EXTI_PIR_PIF1_POS)                        /**< 0x00000002 */
#define EXTI_PIR_PIF1                            EXTI_PIR_PIF1_MASK                                  /**< Rising or Falling pending interrupt flag on line 1 */
#define EXTI_PIR_PIF2_POS                        (2U)
#define EXTI_PIR_PIF2_MASK                       (0x1UL << EXTI_PIR_PIF2_POS)                        /**< 0x00000004 */
#define EXTI_PIR_PIF2                            EXTI_PIR_PIF2_MASK                                  /**< Rising or Falling pending interrupt flag on line 2 */
#define EXTI_PIR_PIF3_POS                        (3U)
#define EXTI_PIR_PIF3_MASK                       (0x1UL << EXTI_PIR_PIF3_POS)                        /**< 0x00000008 */
#define EXTI_PIR_PIF3                            EXTI_PIR_PIF3_MASK                                  /**< Rising or Falling pending interrupt flag on line 3 */
#define EXTI_PIR_PIF4_POS                        (4U)
#define EXTI_PIR_PIF4_MASK                       (0x1UL << EXTI_PIR_PIF4_POS)                        /**< 0x00000010 */
#define EXTI_PIR_PIF4                            EXTI_PIR_PIF4_MASK                                  /**< Rising or Falling pending interrupt flag on line 4 */
#define EXTI_PIR_PIF5_POS                        (5U)
#define EXTI_PIR_PIF5_MASK                       (0x1UL << EXTI_PIR_PIF5_POS)                        /**< 0x00000020 */
#define EXTI_PIR_PIF5                            EXTI_PIR_PIF5_MASK                                  /**< Rising or Falling pending interrupt flag on line 5 */
#define EXTI_PIR_PIF6_POS                        (6U)
#define EXTI_PIR_PIF6_MASK                       (0x1UL << EXTI_PIR_PIF6_POS)                        /**< 0x00000040 */
#define EXTI_PIR_PIF6                            EXTI_PIR_PIF6_MASK                                  /**< Rising or Falling pending interrupt flag on line 6 */
#define EXTI_PIR_PIF7_POS                        (7U)
#define EXTI_PIR_PIF7_MASK                       (0x1UL << EXTI_PIR_PIF7_POS)                        /**< 0x00000080 */
#define EXTI_PIR_PIF7                            EXTI_PIR_PIF7_MASK                                  /**< Rising or Falling pending interrupt flag on line 7 */
#define EXTI_PIR_PIF8_POS                        (8U)
#define EXTI_PIR_PIF8_MASK                       (0x1UL << EXTI_PIR_PIF8_POS)                        /**< 0x00000100 */
#define EXTI_PIR_PIF8                            EXTI_PIR_PIF8_MASK                                  /**< Rising or Falling pending interrupt flag on line 8 */
#define EXTI_PIR_PIF9_POS                        (9U)
#define EXTI_PIR_PIF9_MASK                       (0x1UL << EXTI_PIR_PIF9_POS)                        /**< 0x00000200 */
#define EXTI_PIR_PIF9                            EXTI_PIR_PIF9_MASK                                  /**< Rising or Falling pending interrupt flag on line 9 */

/* Bits for EXTI_EXTICR1 */
#define EXTI_EXTICR1_EXTI0_POS                   (0U)
#define EXTI_EXTICR1_EXTI0_MASK                  (0x3UL << EXTI_EXTICR1_EXTI0_POS)                 /**< 0x00000003 */
#define EXTI_EXTICR1_EXTI0                       EXTI_EXTICR1_EXTI0_MASK                           /**< EXTI 0 configuration */
#define EXTI_EXTICR1_EXTI1_POS                   (4U)
#define EXTI_EXTICR1_EXTI1_MASK                  (0x3UL << EXTI_EXTICR1_EXTI1_POS)                 /**< 0x00000030 */
#define EXTI_EXTICR1_EXTI1                       EXTI_EXTICR1_EXTI1_MASK                           /**< EXTI 1 configuration */
#define EXTI_EXTICR1_EXTI2_POS                   (8U)
#define EXTI_EXTICR1_EXTI2_MASK                  (0x3UL << EXTI_EXTICR1_EXTI2_POS)                 /**< 0x00000300 */
#define EXTI_EXTICR1_EXTI2                       EXTI_EXTICR1_EXTI2_MASK                           /**< EXTI 2 configuration */
#define EXTI_EXTICR1_EXTI3_POS                   (12U)
#define EXTI_EXTICR1_EXTI3_MASK                  (0x3UL << EXTI_EXTICR1_EXTI3_POS)                 /**< 0x00003000 */
#define EXTI_EXTICR1_EXTI3                       EXTI_EXTICR1_EXTI3_MASK                           /**< EXTI 3 configuration */
#define EXTI_EXTICR1_EXTI4_POS                   (16U)
#define EXTI_EXTICR1_EXTI4_MASK                  (0x3UL << EXTI_EXTICR1_EXTI4_POS)                 /**< 0x00030000 */
#define EXTI_EXTICR1_EXTI4                       EXTI_EXTICR1_EXTI4_MASK                           /**< EXTI 4 configuration */
#define EXTI_EXTICR1_EXTI5_POS                   (20U)
#define EXTI_EXTICR1_EXTI5_MASK                  (0x3UL << EXTI_EXTICR1_EXTI5_POS)                 /**< 0x00300000 */
#define EXTI_EXTICR1_EXTI5                       EXTI_EXTICR1_EXTI5_MASK                           /**< EXTI 5 configuration */
#define EXTI_EXTICR1_EXTI6_POS                   (24U)
#define EXTI_EXTICR1_EXTI6_MASK                  (0x3UL << EXTI_EXTICR1_EXTI6_POS)                 /**< 0x03000000 */
#define EXTI_EXTICR1_EXTI6                       EXTI_EXTICR1_EXTI6_MASK                           /**< EXTI 6 configuration */
#define EXTI_EXTICR1_EXTI7_POS                   (28U)
#define EXTI_EXTICR1_EXTI7_MASK                  (0x3UL << EXTI_EXTICR1_EXTI7_POS)                 /**< 0x30000000 */
#define EXTI_EXTICR1_EXTI7                       EXTI_EXTICR1_EXTI7_MASK                           /**< EXTI 7 configuration */

/* Bits for EXTI_EXTICR2 */
#define EXTI_EXTICR2_EXTI8_POS                   (0U)
#define EXTI_EXTICR2_EXTI8_MASK                  (0x3UL << EXTI_EXTICR2_EXTI8_POS)                 /**< 0x00000003 */
#define EXTI_EXTICR2_EXTI8                       EXTI_EXTICR2_EXTI8_MASK                           /**< EXTI 8 configuration  */
#define EXTI_EXTICR2_EXTI9_POS                   (4U)
#define EXTI_EXTICR2_EXTI9_MASK                  (0x3UL << EXTI_EXTICR2_EXTI9_POS)                 /**< 0x00000030 */
#define EXTI_EXTICR2_EXTI9                       EXTI_EXTICR2_EXTI9_MASK                           /**< EXTI 8 configuration  */

/* Bits for EXTI_FILTER */
#define EXTI_FILTER_FLT0_POS                     (0U)
#define EXTI_FILTER_FLT0_MASK                    (0x1UL << EXTI_FILTER_FLT0_POS)                    /**< 0x00000001 */
#define EXTI_FILTER_FLT0                         EXTI_FILTER_FLT0_MASK                              /**< Filter mask on line 0 */
#define EXTI_FILTER_FLT1_POS                     (1U)
#define EXTI_FILTER_FLT1_MASK                    (0x1UL << EXTI_FILTER_FLT1_POS)                    /**< 0x00000002 */
#define EXTI_FILTER_FLT1                         EXTI_FILTER_FLT1_MASK                              /**< Filter mask on line 1 */
#define EXTI_FILTER_FLT2_POS                     (2U)
#define EXTI_FILTER_FLT2_MASK                    (0x1UL << EXTI_FILTER_FLT2_POS)                    /**< 0x00000004 */
#define EXTI_FILTER_FLT2                         EXTI_FILTER_FLT2_MASK                              /**< Filter mask on line 2 */
#define EXTI_FILTER_FLT3_POS                     (3U)
#define EXTI_FILTER_FLT3_MASK                    (0x1UL << EXTI_FILTER_FLT3_POS)                    /**< 0x00000008 */
#define EXTI_FILTER_FLT3                         EXTI_FILTER_FLT3_MASK                              /**< Filter mask on line 3 */
#define EXTI_FILTER_FLT4_POS                     (4U)
#define EXTI_FILTER_FLT4_MASK                    (0x1UL << EXTI_FILTER_FLT4_POS)                    /**< 0x00000010 */
#define EXTI_FILTER_FLT4                         EXTI_FILTER_FLT4_MASK                              /**< Filter mask on line 4 */
#define EXTI_FILTER_FLT5_POS                     (5U)
#define EXTI_FILTER_FLT5_MASK                    (0x1UL << EXTI_FILTER_FLT5_POS)                    /**< 0x00000020 */
#define EXTI_FILTER_FLT5                         EXTI_FILTER_FLT5_MASK                              /**< Filter mask on line 5 */
#define EXTI_FILTER_FLT6_POS                     (6U)
#define EXTI_FILTER_FLT6_MASK                    (0x1UL << EXTI_FILTER_FLT6_POS)                    /**< 0x00000040 */
#define EXTI_FILTER_FLT6                         EXTI_FILTER_FLT6_MASK                              /**< Filter mask on line 6 */
#define EXTI_FILTER_FLT7_POS                     (7U)
#define EXTI_FILTER_FLT7_MASK                    (0x1UL << EXTI_FILTER_FLT7_POS)                    /**< 0x00000080 */
#define EXTI_FILTER_FLT7                         EXTI_FILTER_FLT7_MASK                              /**< Filter mask on line 7 */
#define EXTI_FILTER_FLT8_POS                     (8U)
#define EXTI_FILTER_FLT8_MASK                    (0x1UL << EXTI_FILTER_FLT8_POS)                    /**< 0x00000100 */
#define EXTI_FILTER_FLT8                         EXTI_FILTER_FLT8_MASK                              /**< Filter mask on line 8 */
#define EXTI_FILTER_FLT9_POS                     (9U)
#define EXTI_FILTER_FLT9_MASK                    (0x1UL << EXTI_FILTER_FLT9_POS)                    /**< 0x00000200 */
#define EXTI_FILTER_FLT9                         EXTI_FILTER_FLT9_MASK                              /**< Filter mask on line 9 */
#define EXTI_FILTER_FLTCLK_POS                   (16U)
#define EXTI_FILTER_FLTCLK_MASK                  (0x7UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00070000 */
#define EXTI_FILTER_FLTCLK                       EXTI_FILTER_FLTCLK_MASK                            /**< Filter clock configuration */
#define EXTI_FILTER_FLTCLK_HCLK                  (0x0UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00000000 */
#define EXTI_FILTER_FLTCLK_HCLK_DIV2             (0x1UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00010000 */
#define EXTI_FILTER_FLTCLK_HCLK_DIV4             (0x2UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00020000 */
#define EXTI_FILTER_FLTCLK_HCLK_DIV8             (0x3UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00030000 */
#define EXTI_FILTER_FLTCLK_TIM8_OV               (0x4UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00040000 */
#define EXTI_FILTER_FLTCLK_RCL                   (0x5UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00050000 */
#define EXTI_FILTER_FLTCLK_LXTAL                 (0x6UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00060000 */
#define EXTI_FILTER_FLTCLK_LPTIM1_OV             (0x7UL << EXTI_FILTER_FLTCLK_POS)                  /**< 0x00070000 */

/* Bits for EXTI_IMR */
#define EXTI_IMR_IM0_POS                         (0U)
#define EXTI_IMR_IM0_MASK                        (0x1UL << EXTI_IMR_IM0_POS)                        /**< 0x00000001 */
#define EXTI_IMR_IM0                             EXTI_IMR_IM0_MASK                                  /**< Interrupt mask on line 0 */
#define EXTI_IMR_IM1_POS                         (1U)
#define EXTI_IMR_IM1_MASK                        (0x1UL << EXTI_IMR_IM1_POS)                        /**< 0x00000002 */
#define EXTI_IMR_IM1                             EXTI_IMR_IM1_MASK                                  /**< Interrupt mask on line 1 */
#define EXTI_IMR_IM2_POS                         (2U)
#define EXTI_IMR_IM2_MASK                        (0x1UL << EXTI_IMR_IM2_POS)                        /**< 0x00000004 */
#define EXTI_IMR_IM2                             EXTI_IMR_IM2_MASK                                  /**< Interrupt mask on line 2 */
#define EXTI_IMR_IM3_POS                         (3U)
#define EXTI_IMR_IM3_MASK                        (0x1UL << EXTI_IMR_IM3_POS)                        /**< 0x00000008 */
#define EXTI_IMR_IM3                             EXTI_IMR_IM3_MASK                                  /**< Interrupt mask on line 3 */
#define EXTI_IMR_IM4_POS                         (4U)
#define EXTI_IMR_IM4_MASK                        (0x1UL << EXTI_IMR_IM4_POS)                        /**< 0x00000010 */
#define EXTI_IMR_IM4                             EXTI_IMR_IM4_MASK                                  /**< Interrupt mask on line 4 */
#define EXTI_IMR_IM5_POS                         (5U)
#define EXTI_IMR_IM5_MASK                        (0x1UL << EXTI_IMR_IM5_POS)                        /**< 0x00000020 */
#define EXTI_IMR_IM5                             EXTI_IMR_IM5_MASK                                  /**< Interrupt mask on line 5 */
#define EXTI_IMR_IM6_POS                         (6U)
#define EXTI_IMR_IM6_MASK                        (0x1UL << EXTI_IMR_IM6_POS)                        /**< 0x00000040 */
#define EXTI_IMR_IM6                             EXTI_IMR_IM6_MASK                                  /**< Interrupt mask on line 6 */
#define EXTI_IMR_IM7_POS                         (7U)
#define EXTI_IMR_IM7_MASK                        (0x1UL << EXTI_IMR_IM7_POS)                        /**< 0x00000080 */
#define EXTI_IMR_IM7                             EXTI_IMR_IM7_MASK                                  /**< Interrupt mask on line 7 */
#define EXTI_IMR_IM8_POS                         (8U)
#define EXTI_IMR_IM8_MASK                        (0x1UL << EXTI_IMR_IM8_POS)                        /**< 0x00000100 */
#define EXTI_IMR_IM8                             EXTI_IMR_IM8_MASK                                  /**< Interrupt mask on line 8 */
#define EXTI_IMR_IM9_POS                         (9U)
#define EXTI_IMR_IM9_MASK                        (0x1UL << EXTI_IMR_IM9_POS)                        /**< 0x00000200 */
#define EXTI_IMR_IM9                             EXTI_IMR_IM9_MASK                                  /**< Interrupt mask on line 9 */
#define EXTI_IMR_IM16_POS                        (16U)
#define EXTI_IMR_IM16_MASK                       (0x1UL << EXTI_IMR_IM16_POS)                       /**< 0x00010000 */
#define EXTI_IMR_IM16                            EXTI_IMR_IM16_MASK                                 /**< Interrupt mask on line 16 */
#define EXTI_IMR_IM17_POS                        (17U)
#define EXTI_IMR_IM17_MASK                       (0x1UL << EXTI_IMR_IM17_POS)                       /**< 0x00020000 */
#define EXTI_IMR_IM17                            EXTI_IMR_IM17_MASK                                 /**< Interrupt mask on line 17 */
#define EXTI_IMR_IM24_POS                        (24U)
#define EXTI_IMR_IM24_MASK                       (0x1UL << EXTI_IMR_IM24_POS)                       /**< 0x01000000 */
#define EXTI_IMR_IM24                            EXTI_IMR_IM24_MASK                                 /**< Interrupt mask on line 24 */
#define EXTI_IMR_IM25_POS                        (25U)
#define EXTI_IMR_IM25_MASK                       (0x1UL << EXTI_IMR_IM25_POS)                       /**< 0x02000000 */
#define EXTI_IMR_IM25                            EXTI_IMR_IM25_MASK                                 /**< Interrupt mask on line 25 */
#define EXTI_IMR_IM29_POS                        (29U)
#define EXTI_IMR_IM29_MASK                       (0x1UL << EXTI_IMR_IM29_POS)                       /**< 0x20000000 */
#define EXTI_IMR_IM29                            EXTI_IMR_IM29_MASK                                 /**< Interrupt mask on line 29 */
#define EXTI_IMR_IM30_POS                        (30U)
#define EXTI_IMR_IM30_MASK                       (0x1UL << EXTI_IMR_IM30_POS)                       /**< 0x40000000 */
#define EXTI_IMR_IM30                            EXTI_IMR_IM30_MASK                                 /**< Interrupt mask on line 30 */
#define EXTI_IMR_IM31_POS                        (31U)
#define EXTI_IMR_IM31_MASK                       (0x1UL << EXTI_IMR_IM31_POS)                       /**< 0x80000000 */
#define EXTI_IMR_IM31                            EXTI_IMR_IM31_MASK                                 /**< Interrupt mask on line 31 */

/* Bits for EXTI_EMR */
#define EXTI_EMR_EM0_POS                         (0U)
#define EXTI_EMR_EM0_MASK                        (0x1UL << EXTI_EMR_EM0_POS)                        /**< 0x00000001 */
#define EXTI_EMR_EM0                             EXTI_EMR_EM0_MASK                                  /**< Event mask on line 0 */
#define EXTI_EMR_EM1_POS                         (1U)
#define EXTI_EMR_EM1_MASK                        (0x1UL << EXTI_EMR_EM1_POS)                        /**< 0x00000002 */
#define EXTI_EMR_EM1                             EXTI_EMR_EM1_MASK                                  /**< Event mask on line 1 */
#define EXTI_EMR_EM2_POS                         (2U)
#define EXTI_EMR_EM2_MASK                        (0x1UL << EXTI_EMR_EM2_POS)                        /**< 0x00000004 */
#define EXTI_EMR_EM2                             EXTI_EMR_EM2_MASK                                  /**< Event mask on line 2 */
#define EXTI_EMR_EM3_POS                         (3U)
#define EXTI_EMR_EM3_MASK                        (0x1UL << EXTI_EMR_EM3_POS)                        /**< 0x00000008 */
#define EXTI_EMR_EM3                             EXTI_EMR_EM3_MASK                                  /**< Event mask on line 3 */
#define EXTI_EMR_EM4_POS                         (4U)
#define EXTI_EMR_EM4_MASK                        (0x1UL << EXTI_EMR_EM4_POS)                        /**< 0x00000010 */
#define EXTI_EMR_EM4                             EXTI_EMR_EM4_MASK                                  /**< Event mask on line 4 */
#define EXTI_EMR_EM5_POS                         (5U)
#define EXTI_EMR_EM5_MASK                        (0x1UL << EXTI_EMR_EM5_POS)                        /**< 0x00000020 */
#define EXTI_EMR_EM5                             EXTI_EMR_EM5_MASK                                  /**< Event mask on line 5 */
#define EXTI_EMR_EM6_POS                         (6U)
#define EXTI_EMR_EM6_MASK                        (0x1UL << EXTI_EMR_EM6_POS)                        /**< 0x00000040 */
#define EXTI_EMR_EM6                             EXTI_EMR_EM6_MASK                                  /**< Event mask on line 6 */
#define EXTI_EMR_EM7_POS                         (7U)
#define EXTI_EMR_EM7_MASK                        (0x1UL << EXTI_EMR_EM7_POS)                        /**< 0x00000080 */
#define EXTI_EMR_EM7                             EXTI_EMR_EM7_MASK                                  /**< Event mask on line 7 */
#define EXTI_EMR_EM8_POS                         (8U)
#define EXTI_EMR_EM8_MASK                        (0x1UL << EXTI_EMR_EM8_POS)                        /**< 0x00000100 */
#define EXTI_EMR_EM8                             EXTI_EMR_EM8_MASK                                  /**< Event mask on line 8 */
#define EXTI_EMR_EM9_POS                         (9U)
#define EXTI_EMR_EM9_MASK                        (0x1UL << EXTI_EMR_EM9_POS)                        /**< 0x00000200 */
#define EXTI_EMR_EM9                             EXTI_EMR_EM9_MASK                                  /**< Event mask on line 9 */
#define EXTI_EMR_EM16_POS                        (16U)
#define EXTI_EMR_EM16_MASK                       (0x1UL << EXTI_EMR_EM16_POS)                       /**< 0x00010000 */
#define EXTI_EMR_EM16                            EXTI_EMR_EM16_MASK                                 /**< Event mask on line 16 */
#define EXTI_EMR_EM17_POS                        (17U)
#define EXTI_EMR_EM17_MASK                       (0x1UL << EXTI_EMR_EM17_POS)                       /**< 0x00020000 */
#define EXTI_EMR_EM17                            EXTI_EMR_EM17_MASK                                 /**< Event mask on line 17 */
#define EXTI_EMR_EM24_POS                        (24U)
#define EXTI_EMR_EM24_MASK                       (0x1UL << EXTI_EMR_EM24_POS)                       /**< 0x01000000 */
#define EXTI_EMR_EM24                            EXTI_EMR_EM24_MASK                                 /**< Event mask on line 24 */
#define EXTI_EMR_EM25_POS                        (25U)
#define EXTI_EMR_EM25_MASK                       (0x1UL << EXTI_EMR_EM25_POS)                       /**< 0x02000000 */
#define EXTI_EMR_EM25                            EXTI_EMR_EM25_MASK                                 /**< Event mask on line 25 */
#define EXTI_EMR_EM29_POS                        (29U)
#define EXTI_EMR_EM29_MASK                       (0x1UL << EXTI_EMR_EM29_POS)                       /**< 0x20000000 */
#define EXTI_EMR_EM29                            EXTI_EMR_EM29_MASK                                 /**< Event mask on line 29 */
#define EXTI_EMR_EM30_POS                        (30U)
#define EXTI_EMR_EM30_MASK                       (0x1UL << EXTI_EMR_EM30_POS)                       /**< 0x40000000 */
#define EXTI_EMR_EM30                            EXTI_EMR_EM30_MASK                                 /**< Event mask on line 30 */
#define EXTI_EMR_EM31_POS                        (31U)
#define EXTI_EMR_EM31_MASK                       (0x1UL << EXTI_EMR_EM31_POS)                       /**< 0x80000000 */
#define EXTI_EMR_EM31                            EXTI_EMR_EM31_MASK                                 /**< Event mask on line 31 */


/*-----------------------------------------------------------------------------------------------
                                       FLASH  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for FLASH_ACR */
#define FLASH_ACR_LATENCY_POS                    (0U)
#define FLASH_ACR_LATENCY_MASK                   (0x3UL << FLASH_ACR_LATENCY_POS)                   /**< 0x00000003 */
#define FLASH_ACR_LATENCY                        FLASH_ACR_LATENCY_MASK                             /**< Flash read access wait latency         */
#define FLASH_ACR_LATENCY_0CLK                   (0x0UL << FLASH_ACR_LATENCY_POS)                   /**< 0x00000000 */
#define FLASH_ACR_LATENCY_1CLK                   (0x1UL << FLASH_ACR_LATENCY_POS)                   /**< 0x00000001 */

/* Bits for FLASH_CRKEY */
#define FLASH_CRKEY_CRKEY_POS                    (0U)
#define FLASH_CRKEY_CRKEY_MASK                   (0xFFFFFFFFUL << FLASH_CRKEY_CRKEY_POS)            /**< 0xFFFFFFFF */
#define FLASH_CRKEY_CRKEY                        FLASH_CRKEY_CRKEY_MASK                             /**< CR unlock CR regigster key             */

/* Bits for FLASH_OPTKEY */
#define FLASH_OPTKEY_OPTKEY_POS                  (0U)
#define FLASH_OPTKEY_OPTKEY_MASK                 (0xFFFFFFFFUL << FLASH_OPTKEY_OPTKEY_POS)          /**< 0xFFFFFFFF */
#define FLASH_OPTKEY_OPTKEY                      FLASH_OPTKEY_OPTKEY_MASK                           /**< Option bytes unlock key                */

/* Bits for FLASH_SR */
#define FLASH_SR_WRPERR_POS                      (4U)
#define FLASH_SR_WRPERR_MASK                     (0x1UL << FLASH_SR_WRPERR_POS)                     /**< 0x00000010 */
#define FLASH_SR_WRPERR                          FLASH_SR_WRPERR_MASK                               /**< Flash WRPERR flag                      */
#define FLASH_SR_OPTVERR_POS                     (15U)
#define FLASH_SR_OPTVERR_MASK                    (0x1UL << FLASH_SR_OPTVERR_POS)                    /**< 0x00008000 */
#define FLASH_SR_OPTVERR                         FLASH_SR_OPTVERR_MASK                              /**< Flash option bytes verify error flag   */
#define FLASH_SR_BSY_POS                         (16U)
#define FLASH_SR_BSY_MASK                        (0x1UL << FLASH_SR_BSY_POS)                        /**< 0x00010000 */
#define FLASH_SR_BSY                             FLASH_SR_BSY_MASK                                  /**< Flash operation status flag            */
#define FLASH_SR_EOP_POS                         (24U)
#define FLASH_SR_EOP_MASK                        (0x1UL << FLASH_SR_EOP_POS)                        /**< 0x01000000 */
#define FLASH_SR_EOP                             FLASH_SR_EOP_MASK                                  /**< Flash operation complete flag          */

/* Bits for FLASH_CR */
#define FLASH_CR_OP_MODE_POS                     (1U)
#define FLASH_CR_OP_MODE_MASK                    (0x3UL << FLASH_CR_OP_MODE_POS)                    /**< 0x00000006 */
#define FLASH_CR_OP_MODE                         FLASH_CR_OP_MODE_MASK                              /**< Flash operate mode selection           */
#define FLASH_CR_OP_MODE_IDLE                    (0x0UL << FLASH_CR_OP_MODE_POS)                    /**< 0x00000000 */
#define FLASH_CR_OP_MODE_PROGRAM                 (0x1UL << FLASH_CR_OP_MODE_POS)                    /**< 0x00000002 */
#define FLASH_CR_OP_MODE_PAGE_ERASE              (0x2UL << FLASH_CR_OP_MODE_POS)                    /**< 0x00000004 */
#define FLASH_CR_OP_MODE_MASS_ERASE              (0x3UL << FLASH_CR_OP_MODE_POS)                    /**< 0x00000006 */
#define FLASH_CR_EOPIE_POS                       (24U)
#define FLASH_CR_EOPIE_MASK                      (0x1UL << FLASH_CR_EOPIE_POS)                      /**< 0x01000000 */
#define FLASH_CR_EOPIE                           FLASH_CR_EOPIE_MASK                                /**< Flash operation complete interrupt control */
#define FLASH_CR_OPERRIE_POS                     (25U)
#define FLASH_CR_OPERRIE_MASK                    (0x1UL << FLASH_CR_OPERRIE_POS)                    /**< 0x02000000 */
#define FLASH_CR_OPERRIE                         FLASH_CR_OPERRIE_MASK                              /**< Flash option error interrupt control   */
#define FLASH_CR_OPTLOCK_POS                     (30U)
#define FLASH_CR_OPTLOCK_MASK                    (0x1UL << FLASH_CR_OPTLOCK_POS)                    /**< 0x40000000 */
#define FLASH_CR_OPTLOCK                         FLASH_CR_OPTLOCK_MASK                              /**< Flash option bytes lock status         */
#define FLASH_CR_LOCK_POS                        (31U)
#define FLASH_CR_LOCK_MASK                       (0x1UL << FLASH_CR_LOCK_POS)                       /**< 0x80000000 */
#define FLASH_CR_LOCK                            FLASH_CR_LOCK_MASK                                 /**< Flash CR register lock status          */

/* Bits for FLASH_OPTR1 */
#define FLASH_OPTR1_RDPRP_POS                    (0U)
#define FLASH_OPTR1_RDPRP_MASK                   (0x3UL << FLASH_OPTR1_RDPRP_POS)                   /**< 0x00000003 */
#define FLASH_OPTR1_RDPRP                        FLASH_OPTR1_RDPRP_MASK                             /**< Flash RDP level            */

/* Bits for FLASH_OPTR2 */
#define FLASH_OPTR2_IWDG_STOP_POS                (5U)
#define FLASH_OPTR2_IWDG_STOP_MASK               (0x1UL << FLASH_OPTR2_IWDG_STOP_POS)               /**< 0x00000020 */
#define FLASH_OPTR2_IWDG_STOP                    FLASH_OPTR2_IWDG_STOP_MASK                         /**< IWDG counter stop control in Stop mode */
#define FLASH_OPTR2_BOOT0_SW_POS                 (13U)
#define FLASH_OPTR2_BOOT0_SW_MASK                (0x1UL << FLASH_OPTR2_BOOT0_SW_POS)                /**< 0x00002000 */
#define FLASH_OPTR2_BOOT0_SW                     FLASH_OPTR2_BOOT0_SW_MASK                          /**< Boot0 option bit                       */
#define FLASH_OPTR2_BOOT_SEL_POS                 (14U)
#define FLASH_OPTR2_BOOT_SEL_MASK                (0x1UL << FLASH_OPTR2_BOOT_SEL_POS)                /**< 0x00004000 */
#define FLASH_OPTR2_BOOT_SEL                     FLASH_OPTR2_BOOT_SEL_MASK                          /**< Boot configuration                     */

/* Bits for FLASH_WRP */
#define FLASH_WRP_WRP_POS                        (0U)
#define FLASH_WRP_WRP_MASK                       (0xFFUL << FLASH_WRP_WRP_POS)                      /**< 0x000000FF */
#define FLASH_WRP_WRP                            FLASH_WRP_WRP_MASK                                 /**< Flash WRP configuration                */


/*-----------------------------------------------------------------------------------------------
                                       GPIO  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for GPIO_MODE */
#define GPIO_MODE_MODE0_POS                      (0U)
#define GPIO_MODE_MODE0_MASK                     (0x3UL << GPIO_MODE_MODE0_POS)                     /**< 0x00000003 */
#define GPIO_MODE_MODE0                          GPIO_MODE_MODE0_MASK                               /**< GPIO pin 0 mode configuration */
#define GPIO_MODE_MODE1_POS                      (2U)
#define GPIO_MODE_MODE1_MASK                     (0x3UL << GPIO_MODE_MODE1_POS)                     /**< 0x0000000C */
#define GPIO_MODE_MODE1                          GPIO_MODE_MODE1_MASK                               /**< GPIO pin 1 mode configuration */
#define GPIO_MODE_MODE2_POS                      (4U)
#define GPIO_MODE_MODE2_MASK                     (0x3UL << GPIO_MODE_MODE2_POS)                     /**< 0x00000030 */
#define GPIO_MODE_MODE2                          GPIO_MODE_MODE2_MASK                               /**< GPIO pin 2 mode configuration */
#define GPIO_MODE_MODE3_POS                      (6U)
#define GPIO_MODE_MODE3_MASK                     (0x3UL << GPIO_MODE_MODE3_POS)                     /**< 0x000000C0 */
#define GPIO_MODE_MODE3                          GPIO_MODE_MODE3_MASK                               /**< GPIO pin 3 mode configuration */
#define GPIO_MODE_MODE4_POS                      (8U)
#define GPIO_MODE_MODE4_MASK                     (0x3UL << GPIO_MODE_MODE4_POS)                     /**< 0x00000300 */
#define GPIO_MODE_MODE4                          GPIO_MODE_MODE4_MASK                               /**< GPIO pin 4 mode configuration */
#define GPIO_MODE_MODE5_POS                      (10U)
#define GPIO_MODE_MODE5_MASK                     (0x3UL << GPIO_MODE_MODE5_POS)                     /**< 0x00000C00 */
#define GPIO_MODE_MODE5                          GPIO_MODE_MODE5_MASK                               /**< GPIO pin 5 mode configuration */
#define GPIO_MODE_MODE6_POS                      (12U)
#define GPIO_MODE_MODE6_MASK                     (0x3UL << GPIO_MODE_MODE6_POS)                     /**< 0x00003000 */
#define GPIO_MODE_MODE6                          GPIO_MODE_MODE6_MASK                               /**< GPIO pin 6 mode configuration */
#define GPIO_MODE_MODE7_POS                      (14U)
#define GPIO_MODE_MODE7_MASK                     (0x3UL << GPIO_MODE_MODE7_POS)                     /**< 0x0000C000 */
#define GPIO_MODE_MODE7                          GPIO_MODE_MODE7_MASK                               /**< GPIO pin 7 mode configuration */
#define GPIO_MODE_MODE8_POS                      (16U)
#define GPIO_MODE_MODE8_MASK                     (0x3UL << GPIO_MODE_MODE8_POS)                     /**< 0x00030000 */
#define GPIO_MODE_MODE8                          GPIO_MODE_MODE8_MASK                               /**< GPIO pin 8 mode configuration */
#define GPIO_MODE_MODE9_POS                      (18U)
#define GPIO_MODE_MODE9_MASK                     (0x3UL << GPIO_MODE_MODE9_POS)                     /**< 0x000C0000 */
#define GPIO_MODE_MODE9                          GPIO_MODE_MODE9_MASK                               /**< GPIO pin 9 mode configuration */
#define GPIO_MODE_MODE10_POS                     (20U)
#define GPIO_MODE_MODE10_MASK                    (0x3UL << GPIO_MODE_MODE10_POS)                    /**< 0x00300000 */
#define GPIO_MODE_MODE10                         GPIO_MODE_MODE10_MASK                              /**< GPIO pin 10 mode configuration */
#define GPIO_MODE_MODE11_POS                     (22U)
#define GPIO_MODE_MODE11_MASK                    (0x3UL << GPIO_MODE_MODE11_POS)                    /**< 0x00C00000 */
#define GPIO_MODE_MODE11                         GPIO_MODE_MODE11_MASK                              /**< GPIO pin 11 mode configuration */
#define GPIO_MODE_MODE12_POS                     (24U)
#define GPIO_MODE_MODE12_MASK                    (0x3UL << GPIO_MODE_MODE12_POS)                    /**< 0x03000000 */
#define GPIO_MODE_MODE12                         GPIO_MODE_MODE12_MASK                              /**< GPIO pin 12 mode configuration */
#define GPIO_MODE_MODE13_POS                     (26U)
#define GPIO_MODE_MODE13_MASK                    (0x3UL << GPIO_MODE_MODE13_POS)                    /**< 0x0C000000 */
#define GPIO_MODE_MODE13                         GPIO_MODE_MODE13_MASK                              /**< GPIO pin 13 mode configuration */
#define GPIO_MODE_MODE14_POS                     (28U)
#define GPIO_MODE_MODE14_MASK                    (0x3UL << GPIO_MODE_MODE14_POS)                    /**< 0x30000000 */
#define GPIO_MODE_MODE14                         GPIO_MODE_MODE14_MASK                              /**< GPIO pin 14 mode configuration */
#define GPIO_MODE_MODE15_POS                     (30U)
#define GPIO_MODE_MODE15_MASK                    (0x3UL << GPIO_MODE_MODE15_POS)                    /**< 0xC0000000 */
#define GPIO_MODE_MODE15                         GPIO_MODE_MODE15_MASK                              /**< GPIO pin 15 mode configuration */

/* Bits for GPIO_OTYPE */
#define GPIO_OTYPE_OT0_POS                       (0U)
#define GPIO_OTYPE_OT0_MASK                      (0x1UL << GPIO_OTYPE_OT0_POS)                      /**< 0x00000001 */
#define GPIO_OTYPE_OT0                           GPIO_OTYPE_OT0_MASK                                /**< GPIO pin 0 optput type configuration */
#define GPIO_OTYPE_OT1_POS                       (1U)
#define GPIO_OTYPE_OT1_MASK                      (0x1UL << GPIO_OTYPE_OT1_POS)                      /**< 0x00000002 */
#define GPIO_OTYPE_OT1                           GPIO_OTYPE_OT1_MASK                                /**< GPIO pin 1 optput type configuration */
#define GPIO_OTYPE_OT2_POS                       (2U)
#define GPIO_OTYPE_OT2_MASK                      (0x1UL << GPIO_OTYPE_OT2_POS)                      /**< 0x00000004 */
#define GPIO_OTYPE_OT2                           GPIO_OTYPE_OT2_MASK                                /**< GPIO pin 2 optput type configuration */
#define GPIO_OTYPE_OT3_POS                       (3U)
#define GPIO_OTYPE_OT3_MASK                      (0x1UL << GPIO_OTYPE_OT3_POS)                      /**< 0x00000008 */
#define GPIO_OTYPE_OT3                           GPIO_OTYPE_OT3_MASK                                /**< GPIO pin 3 optput type configuration */
#define GPIO_OTYPE_OT4_POS                       (4U)
#define GPIO_OTYPE_OT4_MASK                      (0x1UL << GPIO_OTYPE_OT4_POS)                      /**< 0x00000010 */
#define GPIO_OTYPE_OT4                           GPIO_OTYPE_OT4_MASK                                /**< GPIO pin 4 optput type configuration */
#define GPIO_OTYPE_OT5_POS                       (5U)
#define GPIO_OTYPE_OT5_MASK                      (0x1UL << GPIO_OTYPE_OT5_POS)                      /**< 0x00000020 */
#define GPIO_OTYPE_OT5                           GPIO_OTYPE_OT5_MASK                                /**< GPIO pin 5 optput type configuration */
#define GPIO_OTYPE_OT6_POS                       (6U)
#define GPIO_OTYPE_OT6_MASK                      (0x1UL << GPIO_OTYPE_OT6_POS)                      /**< 0x00000040 */
#define GPIO_OTYPE_OT6                           GPIO_OTYPE_OT6_MASK                                /**< GPIO pin 6 optput type configuration */
#define GPIO_OTYPE_OT7_POS                       (7U)
#define GPIO_OTYPE_OT7_MASK                      (0x1UL << GPIO_OTYPE_OT7_POS)                      /**< 0x00000080 */
#define GPIO_OTYPE_OT7                           GPIO_OTYPE_OT7_MASK                                /**< GPIO pin 7 optput type configuration */
#define GPIO_OTYPE_OT8_POS                       (8U)
#define GPIO_OTYPE_OT8_MASK                      (0x1UL << GPIO_OTYPE_OT8_POS)                      /**< 0x00000100 */
#define GPIO_OTYPE_OT8                           GPIO_OTYPE_OT8_MASK                                /**< GPIO pin 8 optput type configuration */
#define GPIO_OTYPE_OT9_POS                       (9U)
#define GPIO_OTYPE_OT9_MASK                      (0x1UL << GPIO_OTYPE_OT9_POS)                      /**< 0x00000200 */
#define GPIO_OTYPE_OT9                           GPIO_OTYPE_OT9_MASK                                /**< GPIO pin 9 optput type configuration */
#define GPIO_OTYPE_OT10_POS                      (10U)
#define GPIO_OTYPE_OT10_MASK                     (0x1UL << GPIO_OTYPE_OT10_POS)                     /**< 0x00000400 */
#define GPIO_OTYPE_OT10                          GPIO_OTYPE_OT10_MASK                               /**< GPIO pin 10 optput type configuration */
#define GPIO_OTYPE_OT11_POS                      (11U)
#define GPIO_OTYPE_OT11_MASK                     (0x1UL << GPIO_OTYPE_OT11_POS)                     /**< 0x00000800 */
#define GPIO_OTYPE_OT11                          GPIO_OTYPE_OT11_MASK                               /**< GPIO pin11 optput type configuration */
#define GPIO_OTYPE_OT12_POS                      (12U)
#define GPIO_OTYPE_OT12_MASK                     (0x1UL << GPIO_OTYPE_OT12_POS)                     /**< 0x00001000 */
#define GPIO_OTYPE_OT12                          GPIO_OTYPE_OT12_MASK                               /**< GPIO pin 12 optput type configuration */
#define GPIO_OTYPE_OT13_POS                      (13U)
#define GPIO_OTYPE_OT13_MASK                     (0x1UL << GPIO_OTYPE_OT13_POS)                     /**< 0x00002000 */
#define GPIO_OTYPE_OT13                          GPIO_OTYPE_OT13_MASK                               /**< GPIO pin 13 optput type configuration */
#define GPIO_OTYPE_OT14_POS                      (14U)
#define GPIO_OTYPE_OT14_MASK                     (0x1UL << GPIO_OTYPE_OT14_POS)                     /**< 0x00004000 */
#define GPIO_OTYPE_OT14                          GPIO_OTYPE_OT14_MASK                               /**< GPIO pin 14 optput type configuration */
#define GPIO_OTYPE_OT15_POS                      (15U)
#define GPIO_OTYPE_OT15_MASK                     (0x1UL << GPIO_OTYPE_OT15_POS)                     /**< 0x00008000 */
#define GPIO_OTYPE_OT15                          GPIO_OTYPE_OT15_MASK                               /**< GPIO pin 15 optput type configuration */

/* Bits for GPIO_PUPD */
#define GPIO_PUPD_PUPD0_POS                      (0U)
#define GPIO_PUPD_PUPD0_MASK                     (0x3UL << GPIO_PUPD_PUPD0_POS)                     /**< 0x00000003 */
#define GPIO_PUPD_PUPD0                          GPIO_PUPD_PUPD0_MASK                               /**< GPIO pin 0 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD1_POS                      (2U)
#define GPIO_PUPD_PUPD1_MASK                     (0x3UL << GPIO_PUPD_PUPD1_POS)                     /**< 0x0000000C */
#define GPIO_PUPD_PUPD1                          GPIO_PUPD_PUPD1_MASK                               /**< GPIO pin 1 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD2_POS                      (4U)
#define GPIO_PUPD_PUPD2_MASK                     (0x3UL << GPIO_PUPD_PUPD2_POS)                     /**< 0x00000030 */
#define GPIO_PUPD_PUPD2                          GPIO_PUPD_PUPD2_MASK                               /**< GPIO pin 2 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD3_POS                      (6U)
#define GPIO_PUPD_PUPD3_MASK                     (0x3UL << GPIO_PUPD_PUPD3_POS)                     /**< 0x000000C0 */
#define GPIO_PUPD_PUPD3                          GPIO_PUPD_PUPD3_MASK                               /**< GPIO pin 3 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD4_POS                      (8U)
#define GPIO_PUPD_PUPD4_MASK                     (0x3UL << GPIO_PUPD_PUPD4_POS)                     /**< 0x00000300 */
#define GPIO_PUPD_PUPD4                          GPIO_PUPD_PUPD4_MASK                               /**< GPIO pin 4 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD5_POS                      (10U)
#define GPIO_PUPD_PUPD5_MASK                     (0x3UL << GPIO_PUPD_PUPD5_POS)                     /**< 0x00000C00 */
#define GPIO_PUPD_PUPD5                          GPIO_PUPD_PUPD5_MASK                               /**< GPIO pin 5 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD6_POS                      (12U)
#define GPIO_PUPD_PUPD6_MASK                     (0x3UL << GPIO_PUPD_PUPD6_POS)                     /**< 0x00003000 */
#define GPIO_PUPD_PUPD6                          GPIO_PUPD_PUPD6_MASK                               /**< GPIO pin 6 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD7_POS                      (14U)
#define GPIO_PUPD_PUPD7_MASK                     (0x3UL << GPIO_PUPD_PUPD7_POS)                     /**< 0x0000C000 */
#define GPIO_PUPD_PUPD7                          GPIO_PUPD_PUPD7_MASK                               /**< GPIO pin 7 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD8_POS                      (16U)
#define GPIO_PUPD_PUPD8_MASK                     (0x3UL << GPIO_PUPD_PUPD8_POS)                     /**< 0x00030000 */
#define GPIO_PUPD_PUPD8                          GPIO_PUPD_PUPD8_MASK                               /**< GPIO pin 8 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD9_POS                      (18U)
#define GPIO_PUPD_PUPD9_MASK                     (0x3UL << GPIO_PUPD_PUPD9_POS)                     /**< 0x000C0000 */
#define GPIO_PUPD_PUPD9                          GPIO_PUPD_PUPD9_MASK                               /**< GPIO pin 9 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD10_POS                     (20U)
#define GPIO_PUPD_PUPD10_MASK                    (0x3UL << GPIO_PUPD_PUPD10_POS)                    /**< 0x00300000 */
#define GPIO_PUPD_PUPD10                         GPIO_PUPD_PUPD10_MASK                              /**< GPIO pin 10 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD11_POS                     (22U)
#define GPIO_PUPD_PUPD11_MASK                    (0x3UL << GPIO_PUPD_PUPD11_POS)                    /**< 0x00C00000 */
#define GPIO_PUPD_PUPD11                         GPIO_PUPD_PUPD11_MASK                              /**< GPIO pin 11 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD12_POS                     (24U)
#define GPIO_PUPD_PUPD12_MASK                    (0x3UL << GPIO_PUPD_PUPD12_POS)                    /**< 0x03000000 */
#define GPIO_PUPD_PUPD12                         GPIO_PUPD_PUPD12_MASK                              /**< GPIO pin 12 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD13_POS                     (26U)
#define GPIO_PUPD_PUPD13_MASK                    (0x3UL << GPIO_PUPD_PUPD13_POS)                    /**< 0x0C000000 */
#define GPIO_PUPD_PUPD13                         GPIO_PUPD_PUPD13_MASK                              /**< GPIO pin 13 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD14_POS                     (28U)
#define GPIO_PUPD_PUPD14_MASK                    (0x3UL << GPIO_PUPD_PUPD14_POS)                    /**< 0x30000000 */
#define GPIO_PUPD_PUPD14                         GPIO_PUPD_PUPD14_MASK                              /**< GPIO pin 14 pull-up/pull-down configuration */
#define GPIO_PUPD_PUPD15_POS                     (30U)
#define GPIO_PUPD_PUPD15_MASK                    (0x3UL << GPIO_PUPD_PUPD15_POS)                    /**< 0xC0000000 */
#define GPIO_PUPD_PUPD15                         GPIO_PUPD_PUPD15_MASK                              /**< GPIO pin 15 pull-up/pull-down configuration */

/* Bits for GPIO_IDR */
#define GPIO_IDR_ID0_POS                         (0U)
#define GPIO_IDR_ID0_MASK                        (0x1UL << GPIO_IDR_ID0_POS)                        /**< 0x00000001 */
#define GPIO_IDR_ID0                             GPIO_IDR_ID0_MASK                                  /**< GPIO pin 0 input data */
#define GPIO_IDR_ID1_POS                         (1U)
#define GPIO_IDR_ID1_MASK                        (0x1UL << GPIO_IDR_ID1_POS)                        /**< 0x00000002 */
#define GPIO_IDR_ID1                             GPIO_IDR_ID1_MASK                                  /**< GPIO pin 1 input data */
#define GPIO_IDR_ID2_POS                         (2U)
#define GPIO_IDR_ID2_MASK                        (0x1UL << GPIO_IDR_ID2_POS)                        /**< 0x00000004 */
#define GPIO_IDR_ID2                             GPIO_IDR_ID2_MASK                                  /**< GPIO pin 2 input data */
#define GPIO_IDR_ID3_POS                         (3U)
#define GPIO_IDR_ID3_MASK                        (0x1UL << GPIO_IDR_ID3_POS)                        /**< 0x00000008 */
#define GPIO_IDR_ID3                             GPIO_IDR_ID3_MASK                                  /**< GPIO pin 3 input data */
#define GPIO_IDR_ID4_POS                         (4U)
#define GPIO_IDR_ID4_MASK                        (0x1UL << GPIO_IDR_ID4_POS)                        /**< 0x00000010 */
#define GPIO_IDR_ID4                             GPIO_IDR_ID4_MASK                                  /**< GPIO pin 4 input data */
#define GPIO_IDR_ID5_POS                         (5U)
#define GPIO_IDR_ID5_MASK                        (0x1UL << GPIO_IDR_ID5_POS)                        /**< 0x00000020 */
#define GPIO_IDR_ID5                             GPIO_IDR_ID5_MASK                                  /**< GPIO pin 5 input data */
#define GPIO_IDR_ID6_POS                         (6U)
#define GPIO_IDR_ID6_MASK                        (0x1UL << GPIO_IDR_ID6_POS)                        /**< 0x00000040 */
#define GPIO_IDR_ID6                             GPIO_IDR_ID6_MASK                                  /**< GPIO pin 6 input data */
#define GPIO_IDR_ID7_POS                         (7U)
#define GPIO_IDR_ID7_MASK                        (0x1UL << GPIO_IDR_ID7_POS)                        /**< 0x00000080 */
#define GPIO_IDR_ID7                             GPIO_IDR_ID7_MASK                                  /**< GPIO pin 7 input data */
#define GPIO_IDR_ID8_POS                         (8U)
#define GPIO_IDR_ID8_MASK                        (0x1UL << GPIO_IDR_ID8_POS)                        /**< 0x00000100 */
#define GPIO_IDR_ID8                             GPIO_IDR_ID8_MASK                                  /**< GPIO pin 8 input data */
#define GPIO_IDR_ID9_POS                         (9U)
#define GPIO_IDR_ID9_MASK                        (0x1UL << GPIO_IDR_ID9_POS)                        /**< 0x00000200 */
#define GPIO_IDR_ID9                             GPIO_IDR_ID9_MASK                                  /**< GPIO pin 9 input data */
#define GPIO_IDR_ID10_POS                        (10U)
#define GPIO_IDR_ID10_MASK                       (0x1UL << GPIO_IDR_ID10_POS)                       /**< 0x00000400 */
#define GPIO_IDR_ID10                            GPIO_IDR_ID10_MASK                                 /**< GPIO pin 10 input data */
#define GPIO_IDR_ID11_POS                        (11U)
#define GPIO_IDR_ID11_MASK                       (0x1UL << GPIO_IDR_ID11_POS)                       /**< 0x00000800 */
#define GPIO_IDR_ID11                            GPIO_IDR_ID11_MASK                                 /**< GPIO pin 11 input data */
#define GPIO_IDR_ID12_POS                        (12U)
#define GPIO_IDR_ID12_MASK                       (0x1UL << GPIO_IDR_ID12_POS)                       /**< 0x00001000 */
#define GPIO_IDR_ID12                            GPIO_IDR_ID12_MASK                                 /**< GPIO pin 12 input data */
#define GPIO_IDR_ID13_POS                        (13U)
#define GPIO_IDR_ID13_MASK                       (0x1UL << GPIO_IDR_ID13_POS)                       /**< 0x00002000 */
#define GPIO_IDR_ID13                            GPIO_IDR_ID13_MASK                                 /**< GPIO pin 13 input data */
#define GPIO_IDR_ID14_POS                        (14U)
#define GPIO_IDR_ID14_MASK                       (0x1UL << GPIO_IDR_ID14_POS)                       /**< 0x00004000 */
#define GPIO_IDR_ID14                            GPIO_IDR_ID14_MASK                                 /**< GPIO pin 14 input data */
#define GPIO_IDR_ID15_POS                        (15U)
#define GPIO_IDR_ID15_MASK                       (0x1UL << GPIO_IDR_ID15_POS)                       /**< 0x00008000 */
#define GPIO_IDR_ID15                            GPIO_IDR_ID15_MASK                                 /**< GPIO pin 15 input data */

/* Bits for GPIO_ODR */
#define GPIO_ODR_OD0_POS                         (0U)
#define GPIO_ODR_OD0_MASK                        (0x1UL << GPIO_ODR_OD0_POS)                        /**< 0x00000001 */
#define GPIO_ODR_OD0                             GPIO_ODR_OD0_MASK                                  /**< GPIO pin 0 output data */
#define GPIO_ODR_OD1_POS                         (1U)
#define GPIO_ODR_OD1_MASK                        (0x1UL << GPIO_ODR_OD1_POS)                        /**< 0x00000002 */
#define GPIO_ODR_OD1                             GPIO_ODR_OD1_MASK                                  /**< GPIO pin 1 output data */
#define GPIO_ODR_OD2_POS                         (2U)
#define GPIO_ODR_OD2_MASK                        (0x1UL << GPIO_ODR_OD2_POS)                        /**< 0x00000004 */
#define GPIO_ODR_OD2                             GPIO_ODR_OD2_MASK                                  /**< GPIO pin 2 output data */
#define GPIO_ODR_OD3_POS                         (3U)
#define GPIO_ODR_OD3_MASK                        (0x1UL << GPIO_ODR_OD3_POS)                        /**< 0x00000008 */
#define GPIO_ODR_OD3                             GPIO_ODR_OD3_MASK                                  /**< GPIO pin 3 output data */
#define GPIO_ODR_OD4_POS                         (4U)
#define GPIO_ODR_OD4_MASK                        (0x1UL << GPIO_ODR_OD4_POS)                        /**< 0x00000010 */
#define GPIO_ODR_OD4                             GPIO_ODR_OD4_MASK                                  /**< GPIO pin 4 output data */
#define GPIO_ODR_OD5_POS                         (5U)
#define GPIO_ODR_OD5_MASK                        (0x1UL << GPIO_ODR_OD5_POS)                        /**< 0x00000020 */
#define GPIO_ODR_OD5                             GPIO_ODR_OD5_MASK                                  /**< GPIO pin 5 output data */
#define GPIO_ODR_OD6_POS                         (6U)
#define GPIO_ODR_OD6_MASK                        (0x1UL << GPIO_ODR_OD6_POS)                        /**< 0x00000040 */
#define GPIO_ODR_OD6                             GPIO_ODR_OD6_MASK                                  /**< GPIO pin 6 output data */
#define GPIO_ODR_OD7_POS                         (7U)
#define GPIO_ODR_OD7_MASK                        (0x1UL << GPIO_ODR_OD7_POS)                        /**< 0x00000080 */
#define GPIO_ODR_OD7                             GPIO_ODR_OD7_MASK                                  /**< GPIO pin 7 output data */
#define GPIO_ODR_OD8_POS                         (8U)
#define GPIO_ODR_OD8_MASK                        (0x1UL << GPIO_ODR_OD8_POS)                        /**< 0x00000100 */
#define GPIO_ODR_OD8                             GPIO_ODR_OD8_MASK                                  /**< GPIO pin 8 output data */
#define GPIO_ODR_OD9_POS                         (9U)
#define GPIO_ODR_OD9_MASK                        (0x1UL << GPIO_ODR_OD9_POS)                        /**< 0x00000200 */
#define GPIO_ODR_OD9                             GPIO_ODR_OD9_MASK                                  /**< GPIO pin 9 output data */
#define GPIO_ODR_OD10_POS                        (10U)
#define GPIO_ODR_OD10_MASK                       (0x1UL << GPIO_ODR_OD10_POS)                       /**< 0x00000400 */
#define GPIO_ODR_OD10                            GPIO_ODR_OD10_MASK                                 /**< GPIO pin 10 output data */
#define GPIO_ODR_OD11_POS                        (11U)
#define GPIO_ODR_OD11_MASK                       (0x1UL << GPIO_ODR_OD11_POS)                       /**< 0x00000800 */
#define GPIO_ODR_OD11                            GPIO_ODR_OD11_MASK                                 /**< GPIO pin 11 output data */
#define GPIO_ODR_OD12_POS                        (12U)
#define GPIO_ODR_OD12_MASK                       (0x1UL << GPIO_ODR_OD12_POS)                       /**< 0x00001000 */
#define GPIO_ODR_OD12                            GPIO_ODR_OD12_MASK                                 /**< GPIO pin 12 output data */
#define GPIO_ODR_OD13_POS                        (13U)
#define GPIO_ODR_OD13_MASK                       (0x1UL << GPIO_ODR_OD13_POS)                       /**< 0x00002000 */
#define GPIO_ODR_OD13                            GPIO_ODR_OD13_MASK                                 /**< GPIO pin 13 output data */
#define GPIO_ODR_OD14_POS                        (14U)
#define GPIO_ODR_OD14_MASK                       (0x1UL << GPIO_ODR_OD14_POS)                       /**< 0x00004000 */
#define GPIO_ODR_OD14                            GPIO_ODR_OD14_MASK                                 /**< GPIO pin 14 output data */
#define GPIO_ODR_OD15_POS                        (15U)
#define GPIO_ODR_OD15_MASK                       (0x1UL << GPIO_ODR_OD15_POS)                       /**< 0x00008000 */
#define GPIO_ODR_OD15                            GPIO_ODR_OD15_MASK                                 /**< GPIO pin 15 output data */

/* Bits for GPIO_BSR */
#define GPIO_BSR_BS0_POS                         (0U)
#define GPIO_BSR_BS0_MASK                        (0x1UL << GPIO_BSR_BS0_POS)                        /**< 0x00000001 */
#define GPIO_BSR_BS0                             GPIO_BSR_BS0_MASK                                  /**< GPIO pin 0 ret configuration */
#define GPIO_BSR_BS1_POS                         (1U)
#define GPIO_BSR_BS1_MASK                        (0x1UL << GPIO_BSR_BS1_POS)                        /**< 0x00000002 */
#define GPIO_BSR_BS1                             GPIO_BSR_BS1_MASK                                  /**< GPIO pin 1 ret configuration */
#define GPIO_BSR_BS2_POS                         (2U)
#define GPIO_BSR_BS2_MASK                        (0x1UL << GPIO_BSR_BS2_POS)                        /**< 0x00000004 */
#define GPIO_BSR_BS2                             GPIO_BSR_BS2_MASK                                  /**< GPIO pin 2 ret configuration */
#define GPIO_BSR_BS3_POS                         (3U)
#define GPIO_BSR_BS3_MASK                        (0x1UL << GPIO_BSR_BS3_POS)                        /**< 0x00000008 */
#define GPIO_BSR_BS3                             GPIO_BSR_BS3_MASK                                  /**< GPIO pin 3 ret configuration */
#define GPIO_BSR_BS4_POS                         (4U)
#define GPIO_BSR_BS4_MASK                        (0x1UL << GPIO_BSR_BS4_POS)                        /**< 0x00000010 */
#define GPIO_BSR_BS4                             GPIO_BSR_BS4_MASK                                  /**< GPIO pin 4 ret configuration */
#define GPIO_BSR_BS5_POS                         (5U)
#define GPIO_BSR_BS5_MASK                        (0x1UL << GPIO_BSR_BS5_POS)                        /**< 0x00000020 */
#define GPIO_BSR_BS5                             GPIO_BSR_BS5_MASK                                  /**< GPIO pin 5 ret configuration */
#define GPIO_BSR_BS6_POS                         (6U)
#define GPIO_BSR_BS6_MASK                        (0x1UL << GPIO_BSR_BS6_POS)                        /**< 0x00000040 */
#define GPIO_BSR_BS6                             GPIO_BSR_BS6_MASK                                  /**< GPIO pin 6 ret configuration */
#define GPIO_BSR_BS7_POS                         (7U)
#define GPIO_BSR_BS7_MASK                        (0x1UL << GPIO_BSR_BS7_POS)                        /**< 0x00000080 */
#define GPIO_BSR_BS7                             GPIO_BSR_BS7_MASK                                  /**< GPIO pin 7 ret configuration */
#define GPIO_BSR_BS8_POS                         (8U)
#define GPIO_BSR_BS8_MASK                        (0x1UL << GPIO_BSR_BS8_POS)                        /**< 0x00000100 */
#define GPIO_BSR_BS8                             GPIO_BSR_BS8_MASK                                  /**< GPIO pin 8 ret configuration */
#define GPIO_BSR_BS9_POS                         (9U)
#define GPIO_BSR_BS9_MASK                        (0x1UL << GPIO_BSR_BS9_POS)                        /**< 0x00000200 */
#define GPIO_BSR_BS9                             GPIO_BSR_BS9_MASK                                  /**< GPIO pin 9 ret configuration */
#define GPIO_BSR_BS10_POS                        (10U)
#define GPIO_BSR_BS10_MASK                       (0x1UL << GPIO_BSR_BS10_POS)                       /**< 0x00000400 */
#define GPIO_BSR_BS10                            GPIO_BSR_BS10_MASK                                 /**< GPIO pin 10 ret configuration */
#define GPIO_BSR_BS11_POS                        (11U)
#define GPIO_BSR_BS11_MASK                       (0x1UL << GPIO_BSR_BS11_POS)                       /**< 0x00000800 */
#define GPIO_BSR_BS11                            GPIO_BSR_BS11_MASK                                 /**< GPIO pin 11 ret configuration */
#define GPIO_BSR_BS12_POS                        (12U)
#define GPIO_BSR_BS12_MASK                       (0x1UL << GPIO_BSR_BS12_POS)                       /**< 0x00001000 */
#define GPIO_BSR_BS12                            GPIO_BSR_BS12_MASK                                 /**< GPIO pin 12 ret configuration */
#define GPIO_BSR_BS13_POS                        (13U)
#define GPIO_BSR_BS13_MASK                       (0x1UL << GPIO_BSR_BS13_POS)                       /**< 0x00002000 */
#define GPIO_BSR_BS13                            GPIO_BSR_BS13_MASK                                 /**< GPIO pin 13 ret configuration */
#define GPIO_BSR_BS14_POS                        (14U)
#define GPIO_BSR_BS14_MASK                       (0x1UL << GPIO_BSR_BS14_POS)                       /**< 0x00004000 */
#define GPIO_BSR_BS14                            GPIO_BSR_BS14_MASK                                 /**< GPIO pin 14 ret configuration */
#define GPIO_BSR_BS15_POS                        (15U)
#define GPIO_BSR_BS15_MASK                       (0x1UL << GPIO_BSR_BS15_POS)                       /**< 0x00008000 */
#define GPIO_BSR_BS15                            GPIO_BSR_BS15_MASK                                 /**< GPIO pin 15 ret configuration */
#define GPIO_BSR_BR0_POS                         (16U)
#define GPIO_BSR_BR0_MASK                        (0x1UL << GPIO_BSR_BR0_POS)                        /**< 0x00010000 */
#define GPIO_BSR_BR0                             GPIO_BSR_BR0_MASK                                  /**< GPIO pin 0 reset configuration */
#define GPIO_BSR_BR1_POS                         (17U)
#define GPIO_BSR_BR1_MASK                        (0x1UL << GPIO_BSR_BR1_POS)                        /**< 0x00020000 */
#define GPIO_BSR_BR1                             GPIO_BSR_BR1_MASK                                  /**< GPIO pin 1 reset configuration */
#define GPIO_BSR_BR2_POS                         (18U)
#define GPIO_BSR_BR2_MASK                        (0x1UL << GPIO_BSR_BR2_POS)                        /**< 0x00040000 */
#define GPIO_BSR_BR2                             GPIO_BSR_BR2_MASK                                  /**< GPIO pin 2 reset configuration */
#define GPIO_BSR_BR3_POS                         (19U)
#define GPIO_BSR_BR3_MASK                        (0x1UL << GPIO_BSR_BR3_POS)                        /**< 0x00080000 */
#define GPIO_BSR_BR3                             GPIO_BSR_BR3_MASK                                  /**< GPIO pin 3 reset configuration */
#define GPIO_BSR_BR4_POS                         (20U)
#define GPIO_BSR_BR4_MASK                        (0x1UL << GPIO_BSR_BR4_POS)                        /**< 0x00100000 */
#define GPIO_BSR_BR4                             GPIO_BSR_BR4_MASK                                  /**< GPIO pin 4 reset configuration */
#define GPIO_BSR_BR5_POS                         (21U)
#define GPIO_BSR_BR5_MASK                        (0x1UL << GPIO_BSR_BR5_POS)                        /**< 0x00200000 */
#define GPIO_BSR_BR5                             GPIO_BSR_BR5_MASK                                  /**< GPIO pin 5 reset configuration */
#define GPIO_BSR_BR6_POS                         (22U)
#define GPIO_BSR_BR6_MASK                        (0x1UL << GPIO_BSR_BR6_POS)                        /**< 0x00400000 */
#define GPIO_BSR_BR6                             GPIO_BSR_BR6_MASK                                  /**< GPIO pin 6 reset configuration */
#define GPIO_BSR_BR7_POS                         (23U)
#define GPIO_BSR_BR7_MASK                        (0x1UL << GPIO_BSR_BR7_POS)                        /**< 0x00800000 */
#define GPIO_BSR_BR7                             GPIO_BSR_BR7_MASK                                  /**< GPIO pin 7 reset configuration */
#define GPIO_BSR_BR8_POS                         (24U)
#define GPIO_BSR_BR8_MASK                        (0x1UL << GPIO_BSR_BR8_POS)                        /**< 0x01000000 */
#define GPIO_BSR_BR8                             GPIO_BSR_BR8_MASK                                  /**< GPIO pin 8 reset configuration */
#define GPIO_BSR_BR9_POS                         (25U)
#define GPIO_BSR_BR9_MASK                        (0x1UL << GPIO_BSR_BR9_POS)                        /**< 0x02000000 */
#define GPIO_BSR_BR9                             GPIO_BSR_BR9_MASK                                  /**< GPIO pin 9 reset configuration */
#define GPIO_BSR_BR10_POS                        (26U)
#define GPIO_BSR_BR10_MASK                       (0x1UL << GPIO_BSR_BR10_POS)                       /**< 0x04000000 */
#define GPIO_BSR_BR10                            GPIO_BSR_BR10_MASK                                 /**< GPIO pin 10 reset configuration */
#define GPIO_BSR_BR11_POS                        (27U)
#define GPIO_BSR_BR11_MASK                       (0x1UL << GPIO_BSR_BR11_POS)                       /**< 0x08000000 */
#define GPIO_BSR_BR11                            GPIO_BSR_BR11_MASK                                 /**< GPIO pin 11 reset configuration */
#define GPIO_BSR_BR12_POS                        (28U)
#define GPIO_BSR_BR12_MASK                       (0x1UL << GPIO_BSR_BR12_POS)                       /**< 0x10000000 */
#define GPIO_BSR_BR12                            GPIO_BSR_BR12_MASK                                 /**< GPIO pin 12 reset configuration */
#define GPIO_BSR_BR13_POS                        (29U)
#define GPIO_BSR_BR13_MASK                       (0x1UL << GPIO_BSR_BR13_POS)                       /**< 0x20000000 */
#define GPIO_BSR_BR13                            GPIO_BSR_BR13_MASK                                 /**< GPIO pin 13 reset configuration */
#define GPIO_BSR_BR14_POS                        (30U)
#define GPIO_BSR_BR14_MASK                       (0x1UL << GPIO_BSR_BR14_POS)                       /**< 0x40000000 */
#define GPIO_BSR_BR14                            GPIO_BSR_BR14_MASK                                 /**< GPIO pin 14 reset configuration */
#define GPIO_BSR_BR15_POS                        (31U)
#define GPIO_BSR_BR15_MASK                       (0x1UL << GPIO_BSR_BR15_POS)                       /**< 0x80000000 */
#define GPIO_BSR_BR15                            GPIO_BSR_BR15_MASK                                 /**< GPIO pin 15 reset configuration */

/* Bits for GPIO_AFL */
#define GPIO_AFL_AFSEL0_POS                      (0U)
#define GPIO_AFL_AFSEL0_MASK                     (0x7UL << GPIO_AFL_AFSEL0_POS)                     /**< 0x00000007 */
#define GPIO_AFL_AFSEL0                          GPIO_AFL_AFSEL0_MASK                               /**< GPIO pin 0 alternate function configuration */
#define GPIO_AFL_AFSEL1_POS                      (4U)
#define GPIO_AFL_AFSEL1_MASK                     (0x7UL << GPIO_AFL_AFSEL1_POS)                     /**< 0x00000070 */
#define GPIO_AFL_AFSEL1                          GPIO_AFL_AFSEL1_MASK                               /**< GPIO pin 1 alternate function configuration */
#define GPIO_AFL_AFSEL2_POS                      (8U)
#define GPIO_AFL_AFSEL2_MASK                     (0x7UL << GPIO_AFL_AFSEL2_POS)                     /**< 0x00000700 */
#define GPIO_AFL_AFSEL2                          GPIO_AFL_AFSEL2_MASK                               /**< GPIO pin 2 alternate function configuration */
#define GPIO_AFL_AFSEL3_POS                      (12U)
#define GPIO_AFL_AFSEL3_MASK                     (0x7UL << GPIO_AFL_AFSEL3_POS)                     /**< 0x00007000 */
#define GPIO_AFL_AFSEL3                          GPIO_AFL_AFSEL3_MASK                               /**< GPIO pin 3 alternate function configuration */
#define GPIO_AFL_AFSEL4_POS                      (16U)
#define GPIO_AFL_AFSEL4_MASK                     (0x7UL << GPIO_AFL_AFSEL4_POS)                     /**< 0x00070000 */
#define GPIO_AFL_AFSEL4                          GPIO_AFL_AFSEL4_MASK                               /**< GPIO pin 4 alternate function configuration */
#define GPIO_AFL_AFSEL5_POS                      (20U)
#define GPIO_AFL_AFSEL5_MASK                     (0x7UL << GPIO_AFL_AFSEL5_POS)                     /**< 0x00700000 */
#define GPIO_AFL_AFSEL5                          GPIO_AFL_AFSEL5_MASK                               /**< GPIO pin 5 alternate function configuration */
#define GPIO_AFL_AFSEL6_POS                      (24U)
#define GPIO_AFL_AFSEL6_MASK                     (0x7UL << GPIO_AFL_AFSEL6_POS)                     /**< 0x07000000 */
#define GPIO_AFL_AFSEL6                          GPIO_AFL_AFSEL6_MASK                               /**< GPIO pin 6 alternate function configuration */
#define GPIO_AFL_AFSEL7_POS                      (28U)
#define GPIO_AFL_AFSEL7_MASK                     (0x7UL << GPIO_AFL_AFSEL7_POS)                     /**< 0x70000000 */
#define GPIO_AFL_AFSEL7                          GPIO_AFL_AFSEL7_MASK                               /**< GPIO pin 7 alternate function configuration */

/* Bits for GPIO_AFH */
#define GPIO_AFH_AFSEL8_POS                      (0U)
#define GPIO_AFH_AFSEL8_MASK                     (0x7UL << GPIO_AFH_AFSEL8_POS)                     /**< 0x00000007 */
#define GPIO_AFH_AFSEL8                          GPIO_AFH_AFSEL8_MASK                               /**< GPIO pin 8 alternate function configuration */
#define GPIO_AFH_AFSEL9_POS                      (4U)
#define GPIO_AFH_AFSEL9_MASK                     (0x7UL << GPIO_AFH_AFSEL9_POS)                     /**< 0x00000070 */
#define GPIO_AFH_AFSEL9                          GPIO_AFH_AFSEL9_MASK                               /**< GPIO pin 9 alternate function configuration */
#define GPIO_AFH_AFSEL10_POS                     (8U)
#define GPIO_AFH_AFSEL10_MASK                    (0x7UL << GPIO_AFH_AFSEL10_POS)                    /**< 0x00000700 */
#define GPIO_AFH_AFSEL10                         GPIO_AFH_AFSEL10_MASK                              /**< GPIO pin 10 alternate function configuration */
#define GPIO_AFH_AFSEL11_POS                     (12U)
#define GPIO_AFH_AFSEL11_MASK                    (0x7UL << GPIO_AFH_AFSEL11_POS)                    /**< 0x00007000 */
#define GPIO_AFH_AFSEL11                         GPIO_AFH_AFSEL11_MASK                              /**< GPIO pin 11 alternate function configuration */
#define GPIO_AFH_AFSEL12_POS                     (16U)
#define GPIO_AFH_AFSEL12_MASK                    (0x7UL << GPIO_AFH_AFSEL12_POS)                    /**< 0x00070000 */
#define GPIO_AFH_AFSEL12                         GPIO_AFH_AFSEL12_MASK                              /**< GPIO pin 12 alternate function configuration */
#define GPIO_AFH_AFSEL13_POS                     (20U)
#define GPIO_AFH_AFSEL13_MASK                    (0x7UL << GPIO_AFH_AFSEL13_POS)                    /**< 0x00700000 */
#define GPIO_AFH_AFSEL13                         GPIO_AFH_AFSEL13_MASK                              /**< GPIO pin 13 alternate function configuration */
#define GPIO_AFH_AFSEL14_POS                     (24U)
#define GPIO_AFH_AFSEL14_MASK                    (0x7UL << GPIO_AFH_AFSEL14_POS)                    /**< 0x07000000 */
#define GPIO_AFH_AFSEL14                         GPIO_AFH_AFSEL14_MASK                              /**< GPIO pin 14 alternate function configuration */
#define GPIO_AFH_AFSEL15_POS                     (28U)
#define GPIO_AFH_AFSEL15_MASK                    (0x7UL << GPIO_AFH_AFSEL15_POS)                    /**< 0x70000000 */
#define GPIO_AFH_AFSEL15                         GPIO_AFH_AFSEL15_MASK                              /**< GPIO pin 15 alternate function configuration */

/* Bits for GPIO_BR */
#define GPIO_BR_BR0_POS                          (0U)
#define GPIO_BR_BR0_MASK                         (0x1UL << GPIO_BR_BR0_POS)                         /**< 0x00000001 */
#define GPIO_BR_BR0                              GPIO_BR_BR0_MASK                                   /**< GPIO pin 0 reset configuration */
#define GPIO_BR_BR1_POS                          (1U)
#define GPIO_BR_BR1_MASK                         (0x1UL << GPIO_BR_BR1_POS)                         /**< 0x00000002 */
#define GPIO_BR_BR1                              GPIO_BR_BR1_MASK                                   /**< GPIO pin 1 reset configuration */
#define GPIO_BR_BR2_POS                          (2U)
#define GPIO_BR_BR2_MASK                         (0x1UL << GPIO_BR_BR2_POS)                         /**< 0x00000004 */
#define GPIO_BR_BR2                              GPIO_BR_BR2_MASK                                   /**< GPIO pin 2 reset configuration */
#define GPIO_BR_BR3_POS                          (3U)
#define GPIO_BR_BR3_MASK                         (0x1UL << GPIO_BR_BR3_POS)                         /**< 0x00000008 */
#define GPIO_BR_BR3                              GPIO_BR_BR3_MASK                                   /**< GPIO pin 3 reset configuration */
#define GPIO_BR_BR4_POS                          (4U)
#define GPIO_BR_BR4_MASK                         (0x1UL << GPIO_BR_BR4_POS)                         /**< 0x00000010 */
#define GPIO_BR_BR4                              GPIO_BR_BR4_MASK                                   /**< GPIO pin 4 reset configuration */
#define GPIO_BR_BR5_POS                          (5U)
#define GPIO_BR_BR5_MASK                         (0x1UL << GPIO_BR_BR5_POS)                         /**< 0x00000020 */
#define GPIO_BR_BR5                              GPIO_BR_BR5_MASK                                   /**< GPIO pin 5 reset configuration */
#define GPIO_BR_BR6_POS                          (6U)
#define GPIO_BR_BR6_MASK                         (0x1UL << GPIO_BR_BR6_POS)                         /**< 0x00000040 */
#define GPIO_BR_BR6                              GPIO_BR_BR6_MASK                                   /**< GPIO pin 6 reset configuration */
#define GPIO_BR_BR7_POS                          (7U)
#define GPIO_BR_BR7_MASK                         (0x1UL << GPIO_BR_BR7_POS)                         /**< 0x00000080 */
#define GPIO_BR_BR7                              GPIO_BR_BR7_MASK                                   /**< GPIO pin 7 reset configuration */
#define GPIO_BR_BR8_POS                          (8U)
#define GPIO_BR_BR8_MASK                         (0x1UL << GPIO_BR_BR8_POS)                         /**< 0x00000100 */
#define GPIO_BR_BR8                              GPIO_BR_BR8_MASK                                   /**< GPIO pin 8 reset configuration */
#define GPIO_BR_BR9_POS                          (9U)
#define GPIO_BR_BR9_MASK                         (0x1UL << GPIO_BR_BR9_POS)                         /**< 0x00000200 */
#define GPIO_BR_BR9                              GPIO_BR_BR9_MASK                                   /**< GPIO pin 9 reset configuration */
#define GPIO_BR_BR10_POS                         (10U)
#define GPIO_BR_BR10_MASK                        (0x1UL << GPIO_BR_BR10_POS)                        /**< 0x00000400 */
#define GPIO_BR_BR10                             GPIO_BR_BR10_MASK                                  /**< GPIO pin 10 reset configuration */
#define GPIO_BR_BR11_POS                         (11U)
#define GPIO_BR_BR11_MASK                        (0x1UL << GPIO_BR_BR11_POS)                        /**< 0x00000800 */
#define GPIO_BR_BR11                             GPIO_BR_BR11_MASK                                  /**< GPIO pin 11 reset configuration */
#define GPIO_BR_BR12_POS                         (12U)
#define GPIO_BR_BR12_MASK                        (0x1UL << GPIO_BR_BR12_POS)                        /**< 0x00001000 */
#define GPIO_BR_BR12                             GPIO_BR_BR12_MASK                                  /**< GPIO pin 12 reset configuration */
#define GPIO_BR_BR13_POS                         (13U)
#define GPIO_BR_BR13_MASK                        (0x1UL << GPIO_BR_BR13_POS)                        /**< 0x00002000 */
#define GPIO_BR_BR13                             GPIO_BR_BR13_MASK                                  /**< GPIO pin 13 reset configuration */
#define GPIO_BR_BR14_POS                         (14U)
#define GPIO_BR_BR14_MASK                        (0x1UL << GPIO_BR_BR14_POS)                        /**< 0x00004000 */
#define GPIO_BR_BR14                             GPIO_BR_BR14_MASK                                  /**< GPIO pin 14 reset configuration */
#define GPIO_BR_BR15_POS                         (15U)
#define GPIO_BR_BR15_MASK                        (0x1UL << GPIO_BR_BR15_POS)                        /**< 0x00008000 */
#define GPIO_BR_BR15                             GPIO_BR_BR15_MASK                                  /**< GPIO pin 15 reset configuration */

/* Bits for GPIO_HDCFG1 */
#define GPIO_HDCFG1_HDN0_POS                     (0U)
#define GPIO_HDCFG1_HDN0_MASK                    (0x1UL << GPIO_HDCFG1_HDN0_POS)                    /**< 0x00000001 */
#define GPIO_HDCFG1_HDN0                         GPIO_HDCFG1_HDN0_MASK                              /**< GPIO pin 0 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN1_POS                     (1U)
#define GPIO_HDCFG1_HDN1_MASK                    (0x1UL << GPIO_HDCFG1_HDN1_POS)                    /**< 0x00000002 */
#define GPIO_HDCFG1_HDN1                         GPIO_HDCFG1_HDN1_MASK                              /**< GPIO pin 1 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN2_POS                     (2U)
#define GPIO_HDCFG1_HDN2_MASK                    (0x1UL << GPIO_HDCFG1_HDN2_POS)                    /**< 0x00000004 */
#define GPIO_HDCFG1_HDN2                         GPIO_HDCFG1_HDN2_MASK                              /**< GPIO pin 2 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN3_POS                     (3U)
#define GPIO_HDCFG1_HDN3_MASK                    (0x1UL << GPIO_HDCFG1_HDN3_POS)                    /**< 0x00000008 */
#define GPIO_HDCFG1_HDN3                         GPIO_HDCFG1_HDN3_MASK                              /**< GPIO pin 3 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN4_POS                     (4U)
#define GPIO_HDCFG1_HDN4_MASK                    (0x1UL << GPIO_HDCFG1_HDN4_POS)                    /**< 0x00000010 */
#define GPIO_HDCFG1_HDN4                         GPIO_HDCFG1_HDN4_MASK                              /**< GPIO pin 4 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN5_POS                     (5U)
#define GPIO_HDCFG1_HDN5_MASK                    (0x1UL << GPIO_HDCFG1_HDN5_POS)                    /**< 0x00000020 */
#define GPIO_HDCFG1_HDN5                         GPIO_HDCFG1_HDN5_MASK                              /**< GPIO pin 5 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN6_POS                     (6U)
#define GPIO_HDCFG1_HDN6_MASK                    (0x1UL << GPIO_HDCFG1_HDN6_POS)                    /**< 0x00000040 */
#define GPIO_HDCFG1_HDN6                         GPIO_HDCFG1_HDN6_MASK                              /**< GPIO pin 6 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN7_POS                     (7U)
#define GPIO_HDCFG1_HDN7_MASK                    (0x1UL << GPIO_HDCFG1_HDN7_POS)                    /**< 0x00000080 */
#define GPIO_HDCFG1_HDN7                         GPIO_HDCFG1_HDN7_MASK                              /**< GPIO pin 7 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN8_POS                     (8U)
#define GPIO_HDCFG1_HDN8_MASK                    (0x1UL << GPIO_HDCFG1_HDN8_POS)                    /**< 0x00000100 */
#define GPIO_HDCFG1_HDN8                         GPIO_HDCFG1_HDN8_MASK                              /**< GPIO pin 8 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN9_POS                     (9U)
#define GPIO_HDCFG1_HDN9_MASK                    (0x1UL << GPIO_HDCFG1_HDN9_POS)                    /**< 0x00000200 */
#define GPIO_HDCFG1_HDN9                         GPIO_HDCFG1_HDN9_MASK                              /**< GPIO pin 9 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN10_POS                    (10U)
#define GPIO_HDCFG1_HDN10_MASK                   (0x1UL << GPIO_HDCFG1_HDN10_POS)                   /**< 0x00000400 */
#define GPIO_HDCFG1_HDN10                        GPIO_HDCFG1_HDN10_MASK                             /**< GPIO pin 10 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN11_POS                    (11U)
#define GPIO_HDCFG1_HDN11_MASK                   (0x1UL << GPIO_HDCFG1_HDN11_POS)                   /**< 0x00000800 */
#define GPIO_HDCFG1_HDN11                        GPIO_HDCFG1_HDN11_MASK                             /**< GPIO pin 11 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN12_POS                    (12U)
#define GPIO_HDCFG1_HDN12_MASK                   (0x1UL << GPIO_HDCFG1_HDN12_POS)                   /**< 0x00001000 */
#define GPIO_HDCFG1_HDN12                        GPIO_HDCFG1_HDN12_MASK                             /**< GPIO pin 12 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN13_POS                    (13U)
#define GPIO_HDCFG1_HDN13_MASK                   (0x1UL << GPIO_HDCFG1_HDN13_POS)                   /**< 0x00002000 */
#define GPIO_HDCFG1_HDN13                        GPIO_HDCFG1_HDN13_MASK                             /**< GPIO pin 13 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN14_POS                    (14U)
#define GPIO_HDCFG1_HDN14_MASK                   (0x1UL << GPIO_HDCFG1_HDN14_POS)                   /**< 0x00004000 */
#define GPIO_HDCFG1_HDN14                        GPIO_HDCFG1_HDN14_MASK                             /**< GPIO pin 14 drive mode 1 configuration */
#define GPIO_HDCFG1_HDN15_POS                    (15U)
#define GPIO_HDCFG1_HDN15_MASK                   (0x1UL << GPIO_HDCFG1_HDN15_POS)                   /**< 0x00008000 */
#define GPIO_HDCFG1_HDN15                        GPIO_HDCFG1_HDN15_MASK                             /**< GPIO pin 15 drive mode 1 configuration */

/* Bits for GPIO_HDCFG2 */
#define GPIO_HDCFG2_HDP0_POS                     (0U)
#define GPIO_HDCFG2_HDP0_MASK                    (0x3UL << GPIO_HDCFG2_HDP0_POS)                    /**< 0x00000003 */
#define GPIO_HDCFG2_HDP0                         GPIO_HDCFG2_HDP0_MASK                              /**< GPIO pin 0 drive mode 2 configuration */
#define GPIO_HDCFG2_HDP1_POS                     (2U)
#define GPIO_HDCFG2_HDP1_MASK                    (0x3UL << GPIO_HDCFG2_HDP1_POS)                    /**< 0x0000000C */
#define GPIO_HDCFG2_HDP1                         GPIO_HDCFG2_HDP1_MASK                              /**< GPIO pin 1 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP2_POS                     (4U)
#define GPIO_HDCFG2_HDP2_MASK                    (0x3UL << GPIO_HDCFG2_HDP2_POS)                    /**< 0x00000030 */
#define GPIO_HDCFG2_HDP2                         GPIO_HDCFG2_HDP2_MASK                              /**< GPIO pin 2 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP3_POS                     (6U)
#define GPIO_HDCFG2_HDP3_MASK                    (0x3UL << GPIO_HDCFG2_HDP3_POS)                    /**< 0x000000C0 */
#define GPIO_HDCFG2_HDP3                         GPIO_HDCFG2_HDP3_MASK                              /**< GPIO pin 3 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP4_POS                     (8U)
#define GPIO_HDCFG2_HDP4_MASK                    (0x3UL << GPIO_HDCFG2_HDP4_POS)                    /**< 0x00000300 */
#define GPIO_HDCFG2_HDP4                         GPIO_HDCFG2_HDP4_MASK                              /**< GPIO pin 4 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP5_POS                     (10U)
#define GPIO_HDCFG2_HDP5_MASK                    (0x3UL << GPIO_HDCFG2_HDP5_POS)                    /**< 0x00000C00 */
#define GPIO_HDCFG2_HDP5                         GPIO_HDCFG2_HDP5_MASK                              /**< GPIO pin 5 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP6_POS                     (12U)
#define GPIO_HDCFG2_HDP6_MASK                    (0x3UL << GPIO_HDCFG2_HDP6_POS)                    /**< 0x00003000 */
#define GPIO_HDCFG2_HDP6                         GPIO_HDCFG2_HDP6_MASK                              /**< GPIO pin 6 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP7_POS                     (14U)
#define GPIO_HDCFG2_HDP7_MASK                    (0x3UL << GPIO_HDCFG2_HDP7_POS)                    /**< 0x0000C000 */
#define GPIO_HDCFG2_HDP7                         GPIO_HDCFG2_HDP7_MASK                              /**< GPIO pin 7 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP8_POS                     (16U)
#define GPIO_HDCFG2_HDP8_MASK                    (0x3UL << GPIO_HDCFG2_HDP8_POS)                    /**< 0x00030000 */
#define GPIO_HDCFG2_HDP8                         GPIO_HDCFG2_HDP8_MASK                              /**< GPIO pin 8 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP9_POS                     (18U)
#define GPIO_HDCFG2_HDP9_MASK                    (0x3UL << GPIO_HDCFG2_HDP9_POS)                    /**< 0x000C0000 */
#define GPIO_HDCFG2_HDP9                         GPIO_HDCFG2_HDP9_MASK                              /**< GPIO pin 9 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP10_POS                    (20U)
#define GPIO_HDCFG2_HDP10_MASK                   (0x3UL << GPIO_HDCFG2_HDP10_POS)                   /**< 0x00300000 */
#define GPIO_HDCFG2_HDP10                        GPIO_HDCFG2_HDP10_MASK                             /**< GPIO pin 10 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP11_POS                    (22U)
#define GPIO_HDCFG2_HDP11_MASK                   (0x3UL << GPIO_HDCFG2_HDP11_POS)                   /**< 0x00C00000 */
#define GPIO_HDCFG2_HDP11                        GPIO_HDCFG2_HDP11_MASK                             /**< GPIO pin 11 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP12_POS                    (24U)
#define GPIO_HDCFG2_HDP12_MASK                   (0x3UL << GPIO_HDCFG2_HDP12_POS)                   /**< 0x03000000 */
#define GPIO_HDCFG2_HDP12                        GPIO_HDCFG2_HDP12_MASK                             /**< GPIO pin 12 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP13_POS                    (26U)
#define GPIO_HDCFG2_HDP13_MASK                   (0x3UL << GPIO_HDCFG2_HDP13_POS)                   /**< 0x0C000000 */
#define GPIO_HDCFG2_HDP13                        GPIO_HDCFG2_HDP13_MASK                             /**< GPIO pin 13 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP14_POS                    (28U)
#define GPIO_HDCFG2_HDP14_MASK                   (0x3UL << GPIO_HDCFG2_HDP14_POS)                   /**< 0x30000000 */
#define GPIO_HDCFG2_HDP14                        GPIO_HDCFG2_HDP14_MASK                             /**< GPIO pin 14 drive mode 2 configuration  */
#define GPIO_HDCFG2_HDP15_POS                    (30U)
#define GPIO_HDCFG2_HDP15_MASK                   (0x3UL << GPIO_HDCFG2_HDP15_POS)                   /**< 0xC0000000 */
#define GPIO_HDCFG2_HDP15                        GPIO_HDCFG2_HDP15_MASK                             /**< GPIO pin 15 drive mode 2 configuration  */


/*-----------------------------------------------------------------------------------------------
                                       I2C  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for I2C_CR1 */
#define I2C_CR1_PE_POS                           (0U)
#define I2C_CR1_PE_MASK                          (0x1UL << I2C_CR1_PE_POS)                          /**< 0x00000001 */
#define I2C_CR1_PE                               I2C_CR1_PE_MASK                                    /**< Peripheral enable          */
#define I2C_CR1_BUFIE_POS                        (1U)
#define I2C_CR1_BUFIE_MASK                       (0x1UL << I2C_CR1_BUFIE_POS)                       /**< 0x00000002 */
#define I2C_CR1_BUFIE                            I2C_CR1_BUFIE_MASK                                 /**< Buffer interrupt enable    */
#define I2C_CR1_EVTIE_POS                        (3U)
#define I2C_CR1_EVTIE_MASK                       (0x1UL << I2C_CR1_EVTIE_POS)                       /**< 0x00000008 */
#define I2C_CR1_EVTIE                            I2C_CR1_EVTIE_MASK                                 /**< Event interrupt enable     */
#define I2C_CR1_ERRIE_POS                        (7U)
#define I2C_CR1_ERRIE_MASK                       (0x1UL << I2C_CR1_ERRIE_POS)                       /**< 0x00000080 */
#define I2C_CR1_ERRIE                            I2C_CR1_ERRIE_MASK                                 /**< Errors interrupt enable    */
#define I2C_CR1_DNF_POS                          (8U)
#define I2C_CR1_DNF_MASK                         (0xFUL << I2C_CR1_DNF_POS)                         /**< 0x00000F00 */
#define I2C_CR1_DNF                              I2C_CR1_DNF_MASK                                   /**< Digital noise filter       */
#define I2C_CR1_DNF_DISABLE                      (0x0UL << I2C_CR1_DNF_POS)                         /**< 0x00000000 */
#define I2C_CR1_DNF_1CLK                         (0x1UL << I2C_CR1_DNF_POS)                         /**< 0x00000100 */
#define I2C_CR1_DNF_2CLK                         (0x2UL << I2C_CR1_DNF_POS)                         /**< 0x00000200 */
#define I2C_CR1_DNF_3CLK                         (0x3UL << I2C_CR1_DNF_POS)                         /**< 0x00000300 */
#define I2C_CR1_DNF_4CLK                         (0x4UL << I2C_CR1_DNF_POS)                         /**< 0x00000400 */
#define I2C_CR1_DNF_5CLK                         (0x5UL << I2C_CR1_DNF_POS)                         /**< 0x00000500 */
#define I2C_CR1_DNF_6CLK                         (0x6UL << I2C_CR1_DNF_POS)                         /**< 0x00000600 */
#define I2C_CR1_DNF_7CLK                         (0x7UL << I2C_CR1_DNF_POS)                         /**< 0x00000700 */
#define I2C_CR1_DNF_8CLK                         (0x8UL << I2C_CR1_DNF_POS)                         /**< 0x00000800 */
#define I2C_CR1_DNF_9CLK                         (0x9UL << I2C_CR1_DNF_POS)                         /**< 0x00000900 */
#define I2C_CR1_DNF_10CLK                        (0xAUL << I2C_CR1_DNF_POS)                         /**< 0x00000A00 */
#define I2C_CR1_DNF_11CLK                        (0xBUL << I2C_CR1_DNF_POS)                         /**< 0x00000B00 */
#define I2C_CR1_DNF_12CLK                        (0xCUL << I2C_CR1_DNF_POS)                         /**< 0x00000C00 */
#define I2C_CR1_DNF_13CLK                        (0xDUL << I2C_CR1_DNF_POS)                         /**< 0x00000D00 */
#define I2C_CR1_DNF_14CLK                        (0xEUL << I2C_CR1_DNF_POS)                         /**< 0x00000E00 */
#define I2C_CR1_DNF_15CLK                        (0xFUL << I2C_CR1_DNF_POS)                         /**< 0x00000F00 */
#define I2C_CR1_SIIE_POS                         (13U)
#define I2C_CR1_SIIE_MASK                        (0x1UL << I2C_CR1_SIIE_POS)                        /**< 0x00002000 */
#define I2C_CR1_SIIE                             I2C_CR1_SIIE_MASK                                  /**< Single byte status interrupt enable    */
#define I2C_CR1_TXDMAEN_POS                      (14U)
#define I2C_CR1_TXDMAEN_MASK                     (0x1UL << I2C_CR1_TXDMAEN_POS)                     /**< 0x00004000 */
#define I2C_CR1_TXDMAEN                          I2C_CR1_TXDMAEN_MASK                               /**< DMA transmission requests enable       */
#define I2C_CR1_RXDMAEN_POS                      (15U)
#define I2C_CR1_RXDMAEN_MASK                     (0x1UL << I2C_CR1_RXDMAEN_POS)                     /**< 0x00008000 */
#define I2C_CR1_RXDMAEN                          I2C_CR1_RXDMAEN_MASK                               /**< DMA reception requests enable          */
#define I2C_CR1_SBC_POS                          (16U)
#define I2C_CR1_SBC_MASK                         (0x1UL << I2C_CR1_SBC_POS)                         /**< 0x00010000 */
#define I2C_CR1_SBC                              I2C_CR1_SBC_MASK                                   /**< Sinle byte control enable              */
#define I2C_CR1_NOSTRETCH_POS                    (17U)
#define I2C_CR1_NOSTRETCH_MASK                   (0x1UL << I2C_CR1_NOSTRETCH_POS)                   /**< 0x00020000 */
#define I2C_CR1_NOSTRETCH                        I2C_CR1_NOSTRETCH_MASK                             /**< Clock stretching disable               */
#define I2C_CR1_GCEN_POS                         (19U)
#define I2C_CR1_GCEN_MASK                        (0x1UL << I2C_CR1_GCEN_POS)                        /**< 0x00080000 */
#define I2C_CR1_GCEN                             I2C_CR1_GCEN_MASK                                  /**< General call enable                    */

/* Bits for I2C_CR2 */
#define I2C_CR2_NACK_POS                         (15U)
#define I2C_CR2_NACK_MASK                        (0x1UL << I2C_CR2_NACK_POS)                        /**< 0x00008000 */
#define I2C_CR2_NACK                             I2C_CR2_NACK_MASK                                  /**< NACK generation (slave mode)           */

/* Bits for I2C_ADDR1 */
#define I2C_ADDR1_ADDR1_POS                      (1U)
#define I2C_ADDR1_ADDR1_MASK                     (0x7FUL << I2C_ADDR1_ADDR1_POS)                   /**< 0x000000FE */
#define I2C_ADDR1_ADDR1                          I2C_ADDR1_ADDR1_MASK                               /**< Interface address 1                    */
#define I2C_ADDR1_ADDR1EN_POS                    (15U)
#define I2C_ADDR1_ADDR1EN_MASK                   (0x1UL << I2C_ADDR1_ADDR1EN_POS)                   /**< 0x00008000 */
#define I2C_ADDR1_ADDR1EN                        I2C_ADDR1_ADDR1EN_MASK                             /**< Address 1 enable                       */

/* Bits for I2C_ADDR2 */
#define I2C_ADDR2_ADDR2_POS                      (1U)
#define I2C_ADDR2_ADDR2_MASK                     (0x7FUL << I2C_ADDR2_ADDR2_POS)                    /**< 0x000000FE */
#define I2C_ADDR2_ADDR2                          I2C_ADDR2_ADDR2_MASK                               /**< Interface address 2                    */
#define I2C_ADDR2_ADDR2EN_POS                    (15U)
#define I2C_ADDR2_ADDR2EN_MASK                   (0x1UL << I2C_ADDR2_ADDR2EN_POS)                   /**< 0x00008000 */
#define I2C_ADDR2_ADDR2EN                        I2C_ADDR2_ADDR2EN_MASK                             /**< Address 2 enable                       */

/* Bits for I2C_ISR */
#define I2C_ISR_TXE_POS                          (0U)
#define I2C_ISR_TXE_MASK                         (0x1UL << I2C_ISR_TXE_POS)                         /**< 0x00000001 */
#define I2C_ISR_TXE                              I2C_ISR_TXE_MASK                                   /**< Transmit data register empty           */
#define I2C_ISR_TXIS_POS                         (1U)
#define I2C_ISR_TXIS_MASK                        (0x1UL << I2C_ISR_TXIS_POS)                        /**< 0x00000002 */
#define I2C_ISR_TXIS                             I2C_ISR_TXIS_MASK                                  /**< Transmit interrupt status              */
#define I2C_ISR_RXNE_POS                         (2U)
#define I2C_ISR_RXNE_MASK                        (0x1UL << I2C_ISR_RXNE_POS)                        /**< 0x00000004 */
#define I2C_ISR_RXNE                             I2C_ISR_RXNE_MASK                                  /**< Receive data register not empty        */
#define I2C_ISR_ADDR_POS                         (3U)
#define I2C_ISR_ADDR_MASK                        (0x1UL << I2C_ISR_ADDR_POS)                        /**< 0x00000008 */
#define I2C_ISR_ADDR                             I2C_ISR_ADDR_MASK                                  /**< Address matched (slave mode)           */
#define I2C_ISR_NACKF_POS                        (4U)
#define I2C_ISR_NACKF_MASK                       (0x1UL << I2C_ISR_NACKF_POS)                       /**< 0x00000010 */
#define I2C_ISR_NACKF                            I2C_ISR_NACKF_MASK                                 /**< NACK received flag                     */
#define I2C_ISR_STOPF_POS                        (5U)
#define I2C_ISR_STOPF_MASK                       (0x1UL << I2C_ISR_STOPF_POS)                       /**< 0x00000020 */
#define I2C_ISR_STOPF                            I2C_ISR_STOPF_MASK                                 /**< STOP detection flag                    */
#define I2C_ISR_BERR_POS                         (8U)
#define I2C_ISR_BERR_MASK                        (0x1UL << I2C_ISR_BERR_POS)                        /**< 0x00000100 */
#define I2C_ISR_BERR                             I2C_ISR_BERR_MASK                                  /**< Bus error flag                         */
#define I2C_ISR_OVR_POS                          (10U)
#define I2C_ISR_OVR_MASK                         (0x1UL << I2C_ISR_OVR_POS)                         /**< 0x00000400 */
#define I2C_ISR_OVR                              I2C_ISR_OVR_MASK                                   /**< Arbitration lost flag                  */
#define I2C_ISR_BUSY_POS                         (15U)
#define I2C_ISR_BUSY_MASK                        (0x1UL << I2C_ISR_BUSY_POS)                        /**< 0x00008000 */
#define I2C_ISR_BUSY                             I2C_ISR_BUSY_MASK                                  /**< Bus busy */
#define I2C_ISR_DIR_POS                          (16U)
#define I2C_ISR_DIR_MASK                         (0x1UL << I2C_ISR_DIR_POS)                         /**< 0x00010000 */
#define I2C_ISR_DIR                              I2C_ISR_DIR_MASK                                   /**< Transfer direction (slave mode)        */
#define I2C_ISR_GCALLADDR_POS                    (24U)
#define I2C_ISR_GCALLADDR_MASK                   (0x1UL << I2C_ISR_GCALLADDR_POS)                   /**< 0x01000000 */
#define I2C_ISR_GCALLADDR                        I2C_ISR_GCALLADDR_MASK                             /**< General Call address matched (GCEN=1)  */
#define I2C_ISR_DUADDR_POS                       (25U)
#define I2C_ISR_DUADDR_MASK                      (0x1UL << I2C_ISR_DUADDR_POS)                      /**< 0x02000000 */
#define I2C_ISR_DUADDR                           I2C_ISR_DUADDR_MASK                                /**< Address 2 matched                      */
#define I2C_ISR_SI_POS                           (31U)
#define I2C_ISR_SI_MASK                          (0x1UL << I2C_ISR_SI_POS)                          /**< 0x80000000 */
#define I2C_ISR_SI                               I2C_ISR_SI_MASK                                    /**< single byte status                     */

/* Bits for I2C_ICR */
#define I2C_ICR_ADDRCF_POS                       (3U)
#define I2C_ICR_ADDRCF_MASK                      (0x1UL << I2C_ICR_ADDRCF_POS)                      /**< 0x00000008 */
#define I2C_ICR_ADDRCF                           I2C_ICR_ADDRCF_MASK                                /**< ADDR flag clear    */
#define I2C_ICR_NACKCF_POS                       (4U)
#define I2C_ICR_NACKCF_MASK                      (0x1UL << I2C_ICR_NACKCF_POS)                      /**< 0x00000010 */
#define I2C_ICR_NACKCF                           I2C_ICR_NACKCF_MASK                                /**< NACK flag clear    */
#define I2C_ICR_STOPCF_POS                       (5U)
#define I2C_ICR_STOPCF_MASK                      (0x1UL << I2C_ICR_STOPCF_POS)                      /**< 0x00000020 */
#define I2C_ICR_STOPCF                           I2C_ICR_STOPCF_MASK                                /**< STOPF flag clear   */
#define I2C_ICR_BERRCF_POS                       (8U)
#define I2C_ICR_BERRCF_MASK                      (0x1UL << I2C_ICR_BERRCF_POS)                      /**< 0x00000100 */
#define I2C_ICR_BERRCF                           I2C_ICR_BERRCF_MASK                                /**< BERR flag clear    */
#define I2C_ICR_OVRCF_POS                        (10U)
#define I2C_ICR_OVRCF_MASK                       (0x1UL << I2C_ICR_OVRCF_POS)                       /**< 0x00000400 */
#define I2C_ICR_OVRCF                            I2C_ICR_OVRCF_MASK                                 /**< OVR flag clear     */
#define I2C_ICR_SICF_POS                         (31U)
#define I2C_ICR_SICF_MASK                        (0x1UL << I2C_ICR_SICF_POS)                        /**< 0x80000000 */
#define I2C_ICR_SICF                             I2C_ICR_SICF_MASK                                  /**< SI flag clear      */

/* Bits for I2C_RDR */
#define I2C_RDR_RXDATA_POS                       (0U)
#define I2C_RDR_RXDATA_MASK                      (0xFFUL << I2C_RDR_RXDATA_POS)                     /**< 0x000000FF */
#define I2C_RDR_RXDATA                           I2C_RDR_RXDATA_MASK                                /**< 8-bit receive data  */

/* Bits for I2C_TDR */
#define I2C_TDR_TXDATA_POS                       (0U)
#define I2C_TDR_TXDATA_MASK                      (0xFFUL << I2C_TDR_TXDATA_POS)                     /**< 0x000000FF */
#define I2C_TDR_TXDATA                           I2C_TDR_TXDATA_MASK                                /**< 8-bit transmit data */


/*-----------------------------------------------------------------------------------------------
                                       IRTIM  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for IRTIM_CR */
#define IRTIM_CR_IR_POL_POS                      (2U)
#define IRTIM_CR_IR_POL_MASK                     (0x1UL << IRTIM_CR_IR_POL_POS)                     /**< 0x00000004 */
#define IRTIM_CR_IR_POL                          IRTIM_CR_IR_POL_MASK                               /**< IRTIM config output pol                   */

#define IRTIM_CR_IR_MODE_POS                     (3U)
#define IRTIM_CR_IR_MODE_MASK                    (0x3UL << IRTIM_CR_IR_MODE_POS)                    /**< 0x00000018 */
#define IRTIM_CR_IR_MODE                         IRTIM_CR_IR_MODE_MASK                              /**< IRTIM select the modulation signal        */
#define IRTIM_CR_IR_MODE_TIM3_OC1                (0x0UL << IRTIM_CR_IR_MODE_POS)                    /**< 0x00000000 */ 
#define IRTIM_CR_IR_MODE_UART1_TX                (0x1UL << IRTIM_CR_IR_MODE_POS)                    /**< 0x00000008 */
#define IRTIM_CR_IR_MODE_UART2_TX                (0x2UL << IRTIM_CR_IR_MODE_POS)                    /**< 0x00000010 */

#define IRTIM_CR_IR_CARSEL_POS                   (5U)
#define IRTIM_CR_IR_CARSEL_MASK                  (0x1UL << IRTIM_CR_IR_CARSEL_POS)                  /**< 0x00000020 */
#define IRTIM_CR_IR_CARSEL                       IRTIM_CR_IR_CARSEL_MASK                            /**< IRTIM select the carrier signal           */
#define IRTIM_CR_IR_CARSEL_TIM1_OC1              (0x0UL << IRTIM_CR_IR_CARSEL_POS)                  /**< 0x00000000 */ 
#define IRTIM_CR_IR_CARSEL_TIM3_OC1              (0x1UL << IRTIM_CR_IR_CARSEL_POS)                  /**< 0x00000020 */


/*-----------------------------------------------------------------------------------------------
                                       IWDG  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for IWDG_CR */
#define IWDG_CR_KEY_POS                          (0U)
#define IWDG_CR_KEY_MASK                         (0xFFFFUL << IWDG_CR_KEY_POS)                      /**< 0x0000FFFF */
#define IWDG_CR_KEY                              IWDG_CR_KEY_MASK                                   /**< KEY[15:0] bits(16-bit key value)           */

/* Bits for IWDG_CFG */
#define IWDG_CFG_OVP_POS                         (0U)
#define IWDG_CFG_OVP_MASK                        (0x7UL << IWDG_CFG_OVP_POS)                        /**< 0x00000007 */
#define IWDG_CFG_OVP                             IWDG_CFG_OVP_MASK                                  /**< OVP[2:0] bits (3-bit overflowperiod value) */
#define IWDG_CFG_OVP_128                         (0x0UL << IWDG_CFG_OVP_POS)                        /**< 0x00000000 */
#define IWDG_CFG_OVP_256                         (0x1UL << IWDG_CFG_OVP_POS)                        /**< 0x00000001 */
#define IWDG_CFG_OVP_512                         (0x2UL << IWDG_CFG_OVP_POS)                        /**< 0x00000002 */
#define IWDG_CFG_OVP_1024                        (0x3UL << IWDG_CFG_OVP_POS)                        /**< 0x00000003 */
#define IWDG_CFG_OVP_2048                        (0x4UL << IWDG_CFG_OVP_POS)                        /**< 0x00000004 */
#define IWDG_CFG_OVP_4096                        (0x5UL << IWDG_CFG_OVP_POS)                        /**< 0x00000005 */
#define IWDG_CFG_OVP_8192                        (0x6UL << IWDG_CFG_OVP_POS)                        /**< 0x00000006 */
#define IWDG_CFG_OVP_16384                       (0x7UL << IWDG_CFG_OVP_POS)                        /**< 0x00000007 */
             
/* Bits for IWDG_CNT */
#define IWDG_CNT_CNT_POS                         (0U)
#define IWDG_CNT_CNT_MASK                        (0xFFFUL << IWDG_CNT_CNT_POS)                      /**< 0x00000FFF */
#define IWDG_CNT_CNT                             IWDG_CNT_CNT_MASK                                  /**< CNT[11:0] bits (12-bit counter value)     */


/*-----------------------------------------------------------------------------------------------
                                       LPTIM  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for LPTIM_ISR */
#define LPTIM_ISR_ARRM_POS                       (1U)
#define LPTIM_ISR_ARRM_MASK                      (0x1UL << LPTIM_ISR_ARRM_POS)                      /**< 0x00000002 */
#define LPTIM_ISR_ARRM                           LPTIM_ISR_ARRM_MASK                                /**< Autoreload match            */

/* Bits for LPTIM_ICR */
#define LPTIM_ICR_ARRM_CF_POS                    (1U)
#define LPTIM_ICR_ARRM_CF_MASK                   (0x1UL << LPTIM_ICR_ARRM_CF_POS)                   /**< 0x00000002 */
#define LPTIM_ICR_ARRM_CF                        LPTIM_ICR_ARRM_CF_MASK                             /**< Autoreload match clear flag */

/* Bits for LPTIM_IER */
#define LPTIM_IER_ARRM_IE_POS                    (1U)
#define LPTIM_IER_ARRM_IE_MASK                   (0x1UL << LPTIM_IER_ARRM_IE_POS)                   /**< 0x00000002 */
#define LPTIM_IER_ARRM_IE                        LPTIM_IER_ARRM_IE_MASK                             /**< Autoreload match interrupt enable */
#define LPTIM_IER_ARR_DMAEN_POS                  (13U)
#define LPTIM_IER_ARR_DMAEN_MASK                 (0x1UL << LPTIM_IER_ARR_DMAEN_POS)                 /**< 0x00002000 */
#define LPTIM_IER_ARR_DMAEN                      LPTIM_IER_ARR_DMAEN_MASK                           /**< Autoreload match DMA request      */

/* Bits for LPTIM_CFG */
#define LPTIM_CFG_CKSEL_POS                      (0U)
#define LPTIM_CFG_CKSEL_MASK                     (0x1UL << LPTIM_CFG_CKSEL_POS)                     /**< 0x00000001 */
#define LPTIM_CFG_CKSEL                          LPTIM_CFG_CKSEL_MASK                               /**< Clock selector                   */
#define LPTIM_CFG_CKPOL_POS                      (1U)
#define LPTIM_CFG_CKPOL_MASK                     (0x3UL << LPTIM_CFG_CKPOL_POS)                     /**< 0x00000006 */
#define LPTIM_CFG_CKPOL                          LPTIM_CFG_CKPOL_MASK                               /**< CKPOL[1:0] bits (clock polarity) */
#define LPTIM_CFG_CKPOL_RISING                   (0x0UL << LPTIM_CFG_CKPOL_POS)                     /**< 0x00000000 */ 
#define LPTIM_CFG_CKPOL_FALLING                  (0x1UL << LPTIM_CFG_CKPOL_POS)                     /**< 0x00000002 */
#define LPTIM_CFG_CKPOL_RISING_FALLING           (0x2UL << LPTIM_CFG_CKPOL_POS)                     /**< 0x00000004 */

#define LPTIM_CFG_PRESC_POS                      (9U)
#define LPTIM_CFG_PRESC_MASK                     (0x7UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000E00 */
#define LPTIM_CFG_PRESC                          LPTIM_CFG_PRESC_MASK                               /**< PRESC[2:0] bits (clock prescaler) */
#define LPTIM_CFG_PRESC_1                        (0x0UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000000 */
#define LPTIM_CFG_PRESC_2                        (0x1UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000200 */
#define LPTIM_CFG_PRESC_4                        (0x2UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000400 */
#define LPTIM_CFG_PRESC_8                        (0x3UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000600 */
#define LPTIM_CFG_PRESC_16                       (0x4UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000800 */
#define LPTIM_CFG_PRESC_32                       (0x5UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000A00 */
#define LPTIM_CFG_PRESC_64                       (0x6UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000C00 */
#define LPTIM_CFG_PRESC_128                      (0x7UL << LPTIM_CFG_PRESC_POS)                     /**< 0x00000E00 */

#define LPTIM_CFG_COUNT_MODE_POS                 (23U)
#define LPTIM_CFG_COUNT_MODE_MASK                (0x1UL << LPTIM_CFG_COUNT_MODE_POS)                /**< 0x00800000 */
#define LPTIM_CFG_COUNT_MODE                     LPTIM_CFG_COUNT_MODE_MASK                          /**< Counter mode enable             */

/* Bits for LPTIM_CR */
#define LPTIM_CR_ENABLE_POS                      (0U)
#define LPTIM_CR_ENABLE_MASK                     (0x1UL << LPTIM_CR_ENABLE_POS)                     /**< 0x00000001 */
#define LPTIM_CR_ENABLE                          LPTIM_CR_ENABLE_MASK                               /**< LPTIM enable                    */
#define LPTIM_CR_SNGSTRT_POS                     (1U)
#define LPTIM_CR_SNGSTRT_MASK                    (0x1UL << LPTIM_CR_SNGSTRT_POS)                    /**< 0x00000002 */
#define LPTIM_CR_SNGSTRT                         LPTIM_CR_SNGSTRT_MASK                              /**< LPTIM start in single mode      */
#define LPTIM_CR_CNTSTRT_POS                     (2U)
#define LPTIM_CR_CNTSTRT_MASK                    (0x1UL << LPTIM_CR_CNTSTRT_POS)                    /**< 0x00000004 */
#define LPTIM_CR_CNTSTRT                         LPTIM_CR_CNTSTRT_MASK                              /**< LPTIM start in continuous mode  */

/* Bits for LPTIM_ARR */
#define LPTIM_ARR_ARR_POS                        (0U)
#define LPTIM_ARR_ARR_MASK                       (0xFFFFUL << LPTIM_ARR_ARR_POS)                    /**< 0x0000FFFF */
#define LPTIM_ARR_ARR                            LPTIM_ARR_ARR_MASK                                 /**< Auto reload value               */

/* Bits for LPTIM_CNT */
#define LPTIM_CNT_CNT_POS                        (0U)
#define LPTIM_CNT_CNT_MASK                       (0xFFFFUL << LPTIM_CNT_CNT_POS)                    /**< 0x0000FFFF */
#define LPTIM_CNT_CNT                            LPTIM_CNT_CNT_MASK                                 /**< Counter value                   */


/*-----------------------------------------------------------------------------------------------
                                       PMU  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for PMU_CR1 */
#define PMU_CR1_VAON_WEN_POS                     (8U)
#define PMU_CR1_VAON_WEN_MASK                    (0x1UL << PMU_CR1_VAON_WEN_POS)                    /**< 0x00000100 */
#define PMU_CR1_VAON_WEN                         PMU_CR1_VAON_WEN_MASK                              /**< VCORE_AON domain write protection control */
#define PMU_CR1_BGR_EN_POS                       (15U)
#define PMU_CR1_BGR_EN_MASK                      (0x1UL << PMU_CR1_BGR_EN_POS)                      /**< 0x00008000 */
#define PMU_CR1_BGR_EN                           PMU_CR1_BGR_EN_MASK                                /**< BGR enable                                */

/* Bits for PMU_CR2 */
#define PMU_CR2_PVD_EN_POS                       (0U)
#define PMU_CR2_PVD_EN_MASK                      (0x1UL << PMU_CR2_PVD_EN_POS)                      /**< 0x00000001 */
#define PMU_CR2_PVD_EN                           PMU_CR2_PVD_EN_MASK                                /**< PVD enable                               */
#define PMU_CR2_PVD_LEVEL_POS                    (1U)
#define PMU_CR2_PVD_LEVEL_MASK                   (0x7UL << PMU_CR2_PVD_LEVEL_POS)                   /**< 0x0000000E */
#define PMU_CR2_PVD_LEVEL                        PMU_CR2_PVD_LEVEL_MASK                             /**< PVD threshold selection(raising/falling) */
#define PMU_CR2_FILTER_TIME_POS                  (7U)
#define PMU_CR2_FILTER_TIME_MASK                 (0x7UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000380 */
#define PMU_CR2_FILTER_TIME                      PMU_CR2_FILTER_TIME_MASK                           /**< PVD filter time                          */
#define PMU_CR2_FILTER_TIME_2CYCLE               (0x0UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000000 */
#define PMU_CR2_FILTER_TIME_4CYCLE               (0x1UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000080 */
#define PMU_CR2_FILTER_TIME_8CYCLE               (0x2UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000100 */
#define PMU_CR2_FILTER_TIME_16CYCLE              (0x3UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000180 */
#define PMU_CR2_FILTER_TIME_32CYCLE              (0x4UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000200 */
#define PMU_CR2_FILTER_TIME_64CYCLE              (0x5UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000280 */
#define PMU_CR2_FILTER_TIME_256CYCLE             (0x6UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000300 */
#define PMU_CR2_FILTER_TIME_1024CYCLE            (0x7UL << PMU_CR2_FILTER_TIME_POS)                 /**< 0x00000380 */

#define PMU_CR2_FILTER_EN_POS                    (10U)
#define PMU_CR2_FILTER_EN_MASK                   (0x1UL << PMU_CR2_FILTER_EN_POS)                   /**< 0x00000400 */
#define PMU_CR2_FILTER_EN                        PMU_CR2_FILTER_EN_MASK                             /**< PVD filter enable                        */
#define PMU_CR2_RT_EN_POS                        (11U)                   
#define PMU_CR2_RT_EN_MASK                       (0x1UL << PMU_CR2_RT_EN_POS)                       /**< 0x00000800 */
#define PMU_CR2_RT_EN                            PMU_CR2_RT_EN_MASK                                 /**< PVD from below threshold to above threshold alarm enable */
#define PMU_CR2_FT_EN_POS                        (12U)
#define PMU_CR2_FT_EN_MASK                       (0x1UL << PMU_CR2_FT_EN_POS)                       /**< 0x00001000 */
#define PMU_CR2_FT_EN                            PMU_CR2_FT_EN_MASK                                 /**< PVD from above threshold to below threshold alarm enable */
#define PMU_CR2_LT_EN_POS                        (13U)
#define PMU_CR2_LT_EN_MASK                       (0x1UL << PMU_CR2_LT_EN_POS)                       /**< 0x00002000 */
#define PMU_CR2_LT_EN                            PMU_CR2_LT_EN_MASK                                 /**< PVD below threshold alarm enable        */
#define PMU_CR2_PVD_IE_POS                       (15U)
#define PMU_CR2_PVD_IE_MASK                      (0x1UL << PMU_CR2_PVD_IE_POS)                      /**< 0x00008000 */
#define PMU_CR2_PVD_IE                           PMU_CR2_PVD_IE_MASK                                /**< PVD interrupt enable                    */
#define PMU_CR2_PVD_ACT_POS                      (16U)
#define PMU_CR2_PVD_ACT_MASK                     (0x1UL << PMU_CR2_PVD_ACT_POS)                     /**< 0x00010000 */
#define PMU_CR2_PVD_ACT                          PMU_CR2_PVD_ACT_MASK                               /**< PVD trigger                             */ 
#define PMU_CR2_FILTER_CLK_POS                   (20U)
#define PMU_CR2_FILTER_CLK_MASK                  (0x3UL << PMU_CR2_FILTER_CLK_POS)                  /**< 0x00300000 */
#define PMU_CR2_FILTER_CLK                       PMU_CR2_FILTER_CLK_MASK                            /**< PVD filter clock                        */ 
#define PMU_CR2_FILTER_CLK_SYSCLK                (0x0UL << PMU_CR2_FILTER_CLK_POS)                  /**< 0x00000000 */
#define PMU_CR2_FILTER_CLK_RCL                   (0x1UL << PMU_CR2_FILTER_CLK_POS)                  /**< 0x00100000 */
#define PMU_CR2_FILTER_CLK_LXTAL                 (0x2UL << PMU_CR2_FILTER_CLK_POS)                  /**< 0x00200000 */

/* Bits for PMU_SR */
#define PMU_SR_PVD_STATUS_POS                    (11U)
#define PMU_SR_PVD_STATUS_MASK                   (0x1UL << PMU_SR_PVD_STATUS_POS)                   /**< 0x00000800 */
#define PMU_SR_PVD_STATUS                        PMU_SR_PVD_STATUS_MASK                             /**< PVD output status           */
#define PMU_SR_PVD_INTF_POS                      (12U)
#define PMU_SR_PVD_INTF_MASK                     (0x1UL << PMU_SR_PVD_INTF_POS)                     /**< 0x00001000 */
#define PMU_SR_PVD_INTF                          PMU_SR_PVD_INTF_MASK                               /**< PVD interrupt flag          */
  
/* Bits for PMU_CLR */
#define PMU_CLR_PVD_INTF_CLR_POS                 (12U)
#define PMU_CLR_PVD_INTF_CLR_MASK                (0x1UL << PMU_CLR_PVD_INTF_CLR_POS)                /**< 0x00001000 */
#define PMU_CLR_PVD_INTF_CLR                     PMU_CLR_PVD_INTF_CLR_MASK                          /**< Clear pvd interrupt flag    */

/*-----------------------------------------------------------------------------------------------
                                       RCC  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for RCC_CSR1 */
#define RCC_CSR1_RCHON_POS                       (8U)
#define RCC_CSR1_RCHON_MASK                      (0x1UL << RCC_CSR1_RCHON_POS)                      /**< 0x00000100 */
#define RCC_CSR1_RCHON                           RCC_CSR1_RCHON_MASK                                /**< RCH enable                     */
#define RCC_CSR1_RCH_AWON_POS                    (9U)                                                                                  
#define RCC_CSR1_RCH_AWON_MASK                   (0x1UL << RCC_CSR1_RCH_AWON_POS)                   /**< 0x00000200 */                 
#define RCC_CSR1_RCH_AWON                        RCC_CSR1_RCH_AWON_MASK                             /**< RCH always on                  */
#define RCC_CSR1_RCHRDY_POS                      (10U)
#define RCC_CSR1_RCHRDY_MASK                     (0x1UL << RCC_CSR1_RCHRDY_POS)                     /**< 0x00000400 */
#define RCC_CSR1_RCHRDY                          RCC_CSR1_RCHRDY_MASK                               /**< RCH ready flag                 */
#define RCC_CSR1_RCHFREQ_POS                     (11U)                                                                                  
#define RCC_CSR1_RCHFREQ_MASK                    (0x3UL << RCC_CSR1_RCHFREQ_POS)                    /**< 0x00001800 */                  
#define RCC_CSR1_RCHFREQ                         RCC_CSR1_RCHFREQ_MASK                              /**< RCH clock select               */
#define RCC_CSR1_RCHFREQ_RCH4                    (0x0UL << RCC_CSR1_RCHFREQ_POS)                    /**< 0x00000000 */                  
#define RCC_CSR1_RCHFREQ_RCH16                   (0x1UL << RCC_CSR1_RCHFREQ_POS)                    /**< 0x00000800 */                  
#define RCC_CSR1_RCHFREQ_RCH48                   (0x2UL << RCC_CSR1_RCHFREQ_POS)                    /**< 0x000001800 */                  

/* Bits for RCC_CFG */
#define RCC_CFG_SYSW_POS                         (0U)
#define RCC_CFG_SYSW_MASK                        (0x3UL << RCC_CFG_SYSW_POS)                        /**< 0x00000003 */
#define RCC_CFG_SYSW                             RCC_CFG_SYSW_MASK                                  /**< System clock selection        */
#define RCC_CFG_SYSW_RCH                         (0x0UL << RCC_CFG_SYSW_POS)                        /**< 0x00000000 */
#define RCC_CFG_SYSW_LXTAL                       (0x2UL << RCC_CFG_SYSW_POS)                        /**< 0x00000002 */
#define RCC_CFG_SYSW_RCL                         (0x3UL << RCC_CFG_SYSW_POS)                        /**< 0x00000003 */
                                               
#define RCC_CFG_SYSWS_POS                        (3U)
#define RCC_CFG_SYSWS_MASK                       (0x3UL << RCC_CFG_SYSWS_POS)                       /**< 0x00000018 */
#define RCC_CFG_SYSWS                            RCC_CFG_SYSWS_MASK                                 /**< System clock select status    */
#define RCC_CFG_SYSWS_RCH                        (0x0UL << RCC_CFG_SYSWS_POS)                       /**< 0x00000000 */
#define RCC_CFG_SYSWS_LXTAL                      (0x2UL << RCC_CFG_SYSWS_POS)                       /**< 0x00000010 */
#define RCC_CFG_SYSWS_RCL                        (0x3UL << RCC_CFG_SYSWS_POS)                       /**< 0x00000018 */

#define RCC_CFG_HPRE_POS                         (8U)
#define RCC_CFG_HPRE_MASK                        (0x7UL << RCC_CFG_HPRE_POS)                        /**< 0x00000700 */
#define RCC_CFG_HPRE                             RCC_CFG_HPRE_MASK                                  /**< AHB clock division factor     */
#define RCC_CFG_HPRE_1                           (0x0UL << RCC_CFG_HPRE_POS)                        /**< 0x00000000 */
#define RCC_CFG_HPRE_2                           (0x1UL << RCC_CFG_HPRE_POS)                        /**< 0x00000100 */
#define RCC_CFG_HPRE_4                           (0x2UL << RCC_CFG_HPRE_POS)                        /**< 0x00000200 */
#define RCC_CFG_HPRE_8                           (0x3UL << RCC_CFG_HPRE_POS)                        /**< 0x00000300 */
#define RCC_CFG_HPRE_16                          (0x4UL << RCC_CFG_HPRE_POS)                        /**< 0x00000400 */
#define RCC_CFG_HPRE_32                          (0x5UL << RCC_CFG_HPRE_POS)                        /**< 0x00000500 */
#define RCC_CFG_HPRE_64                          (0x6UL << RCC_CFG_HPRE_POS)                        /**< 0x00000600 */
#define RCC_CFG_HPRE_128                         (0x7UL << RCC_CFG_HPRE_POS)                        /**< 0x00000700 */

#define RCC_CFG_PPRE_POS                         (12U)
#define RCC_CFG_PPRE_MASK                        (0x7UL << RCC_CFG_PPRE_POS)                        /**< 0x00007000 */
#define RCC_CFG_PPRE                             RCC_CFG_PPRE_MASK                                  /**< APB clock division factor     */
#define RCC_CFG_PPRE_1                           (0x0UL << RCC_CFG_PPRE_POS)                        /**< 0x00000000 */
#define RCC_CFG_PPRE_2                           (0x4UL << RCC_CFG_PPRE_POS)                        /**< 0x00004000 */
#define RCC_CFG_PPRE_4                           (0x5UL << RCC_CFG_PPRE_POS)                        /**< 0x00005000 */
#define RCC_CFG_PPRE_8                           (0x6UL << RCC_CFG_PPRE_POS)                        /**< 0x00006000 */
#define RCC_CFG_PPRE_16                          (0x7UL << RCC_CFG_PPRE_POS)                        /**< 0x00007000 */
 
#define RCC_CFG_MCOSEL_POS                       (24U)
#define RCC_CFG_MCOSEL_MASK                      (0x7UL << RCC_CFG_MCOSEL_POS)                      /**< 0x07000000 */
#define RCC_CFG_MCOSEL                           RCC_CFG_MCOSEL_MASK                                /**< MCO clock output selection    */
#define RCC_CFG_MCOSEL_DISABLE                   (0x0UL << RCC_CFG_MCOSEL_POS)                      /**< 0x00000000 */
#define RCC_CFG_MCOSEL_SYSCLK                    (0x1UL << RCC_CFG_MCOSEL_POS)                      /**< 0x01000000 */
#define RCC_CFG_MCOSEL_RCH                       (0x3UL << RCC_CFG_MCOSEL_POS)                      /**< 0x03000000 */
#define RCC_CFG_MCOSEL_RCL                       (0x6UL << RCC_CFG_MCOSEL_POS)                      /**< 0x06000000 */
#define RCC_CFG_MCOSEL_LXTAL                     (0x7UL << RCC_CFG_MCOSEL_POS)                      /**< 0x07000000 */

#define RCC_CFG_MCOPRE_POS                       (28U)
#define RCC_CFG_MCOPRE_MASK                      (0x7UL << RCC_CFG_MCOPRE_POS)                      /**< 0x70000000 */
#define RCC_CFG_MCOPRE                           RCC_CFG_MCOPRE_MASK                                /**< MCO output clock division factor */
#define RCC_CFG_MCOPRE_DIV1                      (0x0UL << RCC_CFG_MCOPRE_POS)                      /**< 0x00000000 */
#define RCC_CFG_MCOPRE_DIV2                      (0x1UL << RCC_CFG_MCOPRE_POS)                      /**< 0x10000000 */
#define RCC_CFG_MCOPRE_DIV4                      (0x2UL << RCC_CFG_MCOPRE_POS)                      /**< 0x20000000 */
#define RCC_CFG_MCOPRE_DIV8                      (0x3UL << RCC_CFG_MCOPRE_POS)                      /**< 0x30000000 */
#define RCC_CFG_MCOPRE_DIV16                     (0x4UL << RCC_CFG_MCOPRE_POS)                      /**< 0x40000000 */
#define RCC_CFG_MCOPRE_DIV32                     (0x5UL << RCC_CFG_MCOPRE_POS)                      /**< 0x50000000 */
#define RCC_CFG_MCOPRE_DIV64                     (0x6UL << RCC_CFG_MCOPRE_POS)                      /**< 0x60000000 */
#define RCC_CFG_MCOPRE_DIV128                    (0x7UL << RCC_CFG_MCOPRE_POS)                      /**< 0x70000000 */

/* Bits for RCC_IER */
#define RCC_IER_LXTAL_CSSIE_POS                  (9U)
#define RCC_IER_LXTAL_CSSIE_MASK                 (0x1UL << RCC_IER_LXTAL_CSSIE_POS)                 /**< 0x00000200 */
#define RCC_IER_LXTAL_CSSIE                      RCC_IER_LXTAL_CSSIE_MASK                           /**< LXTAL CSS interrupt enable       */

/* Bits for RCC_ISR */
#define RCC_ISR_LXTAL_CSSF_POS                   (9U)
#define RCC_ISR_LXTAL_CSSF_MASK                  (0x1UL << RCC_ISR_LXTAL_CSSF_POS)                  /**< 0x00000200 */
#define RCC_ISR_LXTAL_CSSF                       RCC_ISR_LXTAL_CSSF_MASK                            /**< LXTAL CSS flag     */

/* Bits for RCC_ICR */
#define RCC_ICR_LXTAL_CSSC_POS                   (9U)
#define RCC_ICR_LXTAL_CSSC_MASK                  (0x1UL << RCC_ICR_LXTAL_CSSC_POS)                  /**< 0x00000200 */
#define RCC_ICR_LXTAL_CSSC                       RCC_ICR_LXTAL_CSSC_MASK                            /**< Clear LXTAL CSS flag             */

/* Bits for RCC_IOPRST */
#define RCC_IOPRST_GPIOA_RST_POS                 (0U)
#define RCC_IOPRST_GPIOA_RST_MASK                (0x1UL << RCC_IOPRST_GPIOA_RST_POS)                /**< 0x00000001 */
#define RCC_IOPRST_GPIOA_RST                     RCC_IOPRST_GPIOA_RST_MASK                          /**< GPIOA reset control */
#define RCC_IOPRST_GPIOB_RST_POS                 (1U)
#define RCC_IOPRST_GPIOB_RST_MASK                (0x1UL << RCC_IOPRST_GPIOB_RST_POS)                /**< 0x00000002 */
#define RCC_IOPRST_GPIOB_RST                     RCC_IOPRST_GPIOB_RST_MASK                          /**< GPIOB reset control */
#define RCC_IOPRST_GPIOF_RST_POS                 (5U)
#define RCC_IOPRST_GPIOF_RST_MASK                (0x1UL << RCC_IOPRST_GPIOF_RST_POS)                /**< 0x00000020 */
#define RCC_IOPRST_GPIOF_RST                     RCC_IOPRST_GPIOF_RST_MASK                          /**< GPIOF reset control */

/* Bits for RCC_AHBRST */
#define RCC_AHBRST_DMA_RST_POS                   (0U)
#define RCC_AHBRST_DMA_RST_MASK                  (0x1UL << RCC_AHBRST_DMA_RST_POS)                  /**< 0x00000001 */
#define RCC_AHBRST_DMA_RST                       RCC_AHBRST_DMA_RST_MASK                            /**< DMA reset control   */
#define RCC_AHBRST_CRC_RST_POS                   (12U)
#define RCC_AHBRST_CRC_RST_MASK                  (0x1UL << RCC_AHBRST_CRC_RST_POS)                  /**< 0x00001000 */
#define RCC_AHBRST_CRC_RST                       RCC_AHBRST_CRC_RST_MASK                            /**< CRC reset control   */

/* Bits for RCC_APBRST1 */
#define RCC_APBRST1_TIM3_RST_POS                 (1U)
#define RCC_APBRST1_TIM3_RST_MASK                (0x1UL << RCC_APBRST1_TIM3_RST_POS)                /**< 0x00000002 */
#define RCC_APBRST1_TIM3_RST                     RCC_APBRST1_TIM3_RST_MASK                          /**< TIM3 reset control    */
#define RCC_APBRST1_TIM8_RST_POS                 (6U)
#define RCC_APBRST1_TIM8_RST_MASK                (0x1UL << RCC_APBRST1_TIM8_RST_POS)                /**< 0x00000040 */
#define RCC_APBRST1_TIM8_RST                     RCC_APBRST1_TIM8_RST_MASK                          /**< TIM8 reset control    */
#define RCC_APBRST1_SPI2_RST_POS                 (14U)
#define RCC_APBRST1_SPI2_RST_MASK                (0x1UL << RCC_APBRST1_SPI2_RST_POS)                /**< 0x00004000 */
#define RCC_APBRST1_SPI2_RST                     RCC_APBRST1_SPI2_RST_MASK                          /**< SPI2 reset control    */
#define RCC_APBRST1_UART2_RST_POS                (17U)
#define RCC_APBRST1_UART2_RST_MASK               (0x1UL << RCC_APBRST1_UART2_RST_POS)               /**< 0x00020000 */
#define RCC_APBRST1_UART2_RST                    RCC_APBRST1_UART2_RST_MASK                         /**< UART2 reset control   */
#define RCC_APBRST1_LPUART1_RST_POS              (20U)
#define RCC_APBRST1_LPUART1_RST_MASK             (0x1UL << RCC_APBRST1_LPUART1_RST_POS)             /**< 0x00100000 */
#define RCC_APBRST1_LPUART1_RST                  RCC_APBRST1_LPUART1_RST_MASK                       /**< LPUART1 reset control */
#define RCC_APBRST1_I2C1_RST_POS                 (21U)
#define RCC_APBRST1_I2C1_RST_MASK                (0x1UL << RCC_APBRST1_I2C1_RST_POS)                /**< 0x00200000 */
#define RCC_APBRST1_I2C1_RST                     RCC_APBRST1_I2C1_RST_MASK                          /**< I2C1 reset control    */
#define RCC_APBRST1_LPTIM1_RST_POS               (31U)
#define RCC_APBRST1_LPTIM1_RST_MASK              (0x1UL << RCC_APBRST1_LPTIM1_RST_POS)              /**< 0x80000000 */
#define RCC_APBRST1_LPTIM1_RST                   RCC_APBRST1_LPTIM1_RST_MASK                        /**< LPTIM1 reset control  */

/* Bits for RCC_APBRST2 */
#define RCC_APBRST2_COMP_RST_POS                 (0U)
#define RCC_APBRST2_COMP_RST_MASK                (0x1UL << RCC_APBRST2_COMP_RST_POS)                /**< 0x00000001 */
#define RCC_APBRST2_COMP_RST                     RCC_APBRST2_COMP_RST_MASK                          /**< COMP reset control  */
#define RCC_APBRST2_TIM1_RST_POS                 (11U)
#define RCC_APBRST2_TIM1_RST_MASK                (0x1UL << RCC_APBRST2_TIM1_RST_POS)                /**< 0x00000800 */
#define RCC_APBRST2_TIM1_RST                     RCC_APBRST2_TIM1_RST_MASK                          /**< TIM1 reset control  */
#define RCC_APBRST2_SPI1_RST_POS                 (12U)
#define RCC_APBRST2_SPI1_RST_MASK                (0x1UL << RCC_APBRST2_SPI1_RST_POS)                /**< 0x00001000 */
#define RCC_APBRST2_SPI1_RST                     RCC_APBRST2_SPI1_RST_MASK                          /**< SPI1 reset control  */
#define RCC_APBRST2_UART1_RST_POS                (14U)
#define RCC_APBRST2_UART1_RST_MASK               (0x1UL << RCC_APBRST2_UART1_RST_POS)               /**< 0x00004000 */
#define RCC_APBRST2_UART1_RST                    RCC_APBRST2_UART1_RST_MASK                         /**< UART1 reset control */
#define RCC_APBRST2_ADC_RST_POS                  (20U)
#define RCC_APBRST2_ADC_RST_MASK                 (0x1UL << RCC_APBRST2_ADC_RST_POS)                 /**< 0x00100000 */
#define RCC_APBRST2_ADC_RST                      RCC_APBRST2_ADC_RST_MASK                           /**< ADC reset control   */
#define RCC_APBRST2_DBG_RST_POS                  (27U)
#define RCC_APBRST2_DBG_RST_MASK                 (0x1UL << RCC_APBRST2_DBG_RST_POS)                 /**< 0x08000000 */
#define RCC_APBRST2_DBG_RST                      RCC_APBRST2_DBG_RST_MASK                           /**< DBG reset control   */

/* Bits for RCC_IOPEN */
#define RCC_IOPEN_GPIOAEN_POS                    (0U)
#define RCC_IOPEN_GPIOAEN_MASK                   (0x1UL << RCC_IOPEN_GPIOAEN_POS)                   /**< 0x00000001 */
#define RCC_IOPEN_GPIOAEN                        RCC_IOPEN_GPIOAEN_MASK                             /**< GPIOA clock enable */
#define RCC_IOPEN_GPIOBEN_POS                    (1U)
#define RCC_IOPEN_GPIOBEN_MASK                   (0x1UL << RCC_IOPEN_GPIOBEN_POS)                   /**< 0x00000002 */
#define RCC_IOPEN_GPIOBEN                        RCC_IOPEN_GPIOBEN_MASK                             /**< GPIOB clock enable */
#define RCC_IOPEN_GPIOFEN_POS                    (5U)
#define RCC_IOPEN_GPIOFEN_MASK                   (0x1UL << RCC_IOPEN_GPIOFEN_POS)                   /**< 0x00000020 */
#define RCC_IOPEN_GPIOFEN                        RCC_IOPEN_GPIOFEN_MASK                             /**< GPIOF clock enable */

/* Bits for RCC_AHBEN */
#define RCC_AHBEN_DMAEN_POS                      (0U)
#define RCC_AHBEN_DMAEN_MASK                     (0x1UL << RCC_AHBEN_DMAEN_POS)                     /**< 0x00000001 */
#define RCC_AHBEN_DMAEN                          RCC_AHBEN_DMAEN_MASK                               /**< DMA clock enable   */
#define RCC_AHBEN_CRCEN_POS                      (12U)
#define RCC_AHBEN_CRCEN_MASK                     (0x1UL << RCC_AHBEN_CRCEN_POS)                     /**< 0x00001000 */
#define RCC_AHBEN_CRCEN                          RCC_AHBEN_CRCEN_MASK                               /**< CRC clock enable   */

/* Bits for RCC_APBEN1 */
#define RCC_APBEN1_TIM3EN_POS                    (1U)
#define RCC_APBEN1_TIM3EN_MASK                   (0x1UL << RCC_APBEN1_TIM3EN_POS)                   /**< 0x00000002 */
#define RCC_APBEN1_TIM3EN                        RCC_APBEN1_TIM3EN_MASK                             /**< TIM3 clock enable    */
#define RCC_APBEN1_TIM8EN_POS                    (6U)
#define RCC_APBEN1_TIM8EN_MASK                   (0x1UL << RCC_APBEN1_TIM8EN_POS)                   /**< 0x00000040 */
#define RCC_APBEN1_TIM8EN                        RCC_APBEN1_TIM8EN_MASK                             /**< TIM8 clock enable    */
#define RCC_APBEN1_RTCAPBEN_POS                  (10U)
#define RCC_APBEN1_RTCAPBEN_MASK                 (0x1UL << RCC_APBEN1_RTCAPBEN_POS)                 /**< 0x00000400 */
#define RCC_APBEN1_RTCAPBEN                      RCC_APBEN1_RTCAPBEN_MASK                           /**< RTCAPB clock enable  */
#define RCC_APBEN1_SPI2EN_POS                    (14U)
#define RCC_APBEN1_SPI2EN_MASK                   (0x1UL << RCC_APBEN1_SPI2EN_POS)                   /**< 0x00004000 */
#define RCC_APBEN1_SPI2EN                        RCC_APBEN1_SPI2EN_MASK                             /**< SPI2 clock enable    */
#define RCC_APBEN1_UART2EN_POS                   (17U)
#define RCC_APBEN1_UART2EN_MASK                  (0x1UL << RCC_APBEN1_UART2EN_POS)                  /**< 0x00020000 */
#define RCC_APBEN1_UART2EN                       RCC_APBEN1_UART2EN_MASK                            /**< UART2 clock enable   */
#define RCC_APBEN1_LPUART1EN_POS                 (20U)
#define RCC_APBEN1_LPUART1EN_MASK                (0x1UL << RCC_APBEN1_LPUART1EN_POS)                /**< 0x00100000 */
#define RCC_APBEN1_LPUART1EN                     RCC_APBEN1_LPUART1EN_MASK                          /**< LPUART1 clock enable */
#define RCC_APBEN1_I2C1EN_POS                    (21U)
#define RCC_APBEN1_I2C1EN_MASK                   (0x1UL << RCC_APBEN1_I2C1EN_POS)                   /**< 0x00200000 */
#define RCC_APBEN1_I2C1EN                        RCC_APBEN1_I2C1EN_MASK                             /**< I2C1 clock enable    */
#define RCC_APBEN1_PMUEN_POS                     (28U)
#define RCC_APBEN1_PMUEN_MASK                    (0x1UL << RCC_APBEN1_PMUEN_POS)                    /**< 0x10000000 */
#define RCC_APBEN1_PMUEN                         RCC_APBEN1_PMUEN_MASK                              /**< PMU clock enable     */
#define RCC_APBEN1_LPTIM1EN_POS                  (31U)
#define RCC_APBEN1_LPTIM1EN_MASK                 (0x1UL << RCC_APBEN1_LPTIM1EN_POS)                 /**< 0x80000000 */
#define RCC_APBEN1_LPTIM1EN                      RCC_APBEN1_LPTIM1EN_MASK                           /**< LPTIM1 clock enable  */

/* Bits for RCC_APBEN2 */
#define RCC_APBEN2_COMPEN_POS                    (0U)
#define RCC_APBEN2_COMPEN_MASK                   (0x1UL << RCC_APBEN2_COMPEN_POS)                   /**< 0x00000001 */
#define RCC_APBEN2_COMPEN                        RCC_APBEN2_COMPEN_MASK                             /**< COMP clock enable  */
#define RCC_APBEN2_TIM1EN_POS                    (11U)
#define RCC_APBEN2_TIM1EN_MASK                   (0x1UL << RCC_APBEN2_TIM1EN_POS)                   /**< 0x00000800 */
#define RCC_APBEN2_TIM1EN                        RCC_APBEN2_TIM1EN_MASK                             /**< TIM1 clock enable  */
#define RCC_APBEN2_SPI1EN_POS                    (12U)
#define RCC_APBEN2_SPI1EN_MASK                   (0x1UL << RCC_APBEN2_SPI1EN_POS)                   /**< 0x00001000 */
#define RCC_APBEN2_SPI1EN                        RCC_APBEN2_SPI1EN_MASK                             /**< SPI1 clock enable  */
#define RCC_APBEN2_UART1EN_POS                   (14U)
#define RCC_APBEN2_UART1EN_MASK                  (0x1UL << RCC_APBEN2_UART1EN_POS)                  /**< 0x00004000 */
#define RCC_APBEN2_UART1EN                       RCC_APBEN2_UART1EN_MASK                            /**< UART1 clock enable */
#define RCC_APBEN2_ADCEN_POS                     (20U)
#define RCC_APBEN2_ADCEN_MASK                    (0x1UL << RCC_APBEN2_ADCEN_POS)                    /**< 0x00100000 */
#define RCC_APBEN2_ADCEN                         RCC_APBEN2_ADCEN_MASK                              /**< ADC clock enable   */
#define RCC_APBEN2_DBGEN_POS                     (27U)
#define RCC_APBEN2_DBGEN_MASK                    (0x1UL << RCC_APBEN2_DBGEN_POS)                    /**< 0x08000000 */  
#define RCC_APBEN2_DBGEN                         RCC_APBEN2_DBGEN_MASK                              /**< DBG clock enable   */

/* Bits for RCC_CLKSEL */
#define RCC_CLKSEL_LPUART1_SEL_POS               (10U)
#define RCC_CLKSEL_LPUART1_SEL_MASK              (0x3UL << RCC_CLKSEL_LPUART1_SEL_POS)              /**< 0x00000C00 */
#define RCC_CLKSEL_LPUART1_SEL                   RCC_CLKSEL_LPUART1_SEL_MASK                        /**< LPUART1 KCLK selection  */
#define RCC_CLKSEL_LPUART1_SEL_PCLK              (0x0UL << RCC_CLKSEL_LPUART1_SEL_POS)              /**< 0x00000000 */
#define RCC_CLKSEL_LPUART1_SEL_SYSCLK            (0x1UL << RCC_CLKSEL_LPUART1_SEL_POS)              /**< 0x00000400 */
#define RCC_CLKSEL_LPUART1_SEL_RCH               (0x2UL << RCC_CLKSEL_LPUART1_SEL_POS)              /**< 0x00000800 */
#define RCC_CLKSEL_LPUART1_SEL_LXTAL             (0x3UL << RCC_CLKSEL_LPUART1_SEL_POS)              /**< 0x00000C00 */   

#define RCC_CLKSEL_LPTIM1_SEL_POS                (18U)
#define RCC_CLKSEL_LPTIM1_SEL_MASK               (0x3UL << RCC_CLKSEL_LPTIM1_SEL_POS)               /**< 0x000C0000 */
#define RCC_CLKSEL_LPTIM1_SEL                    RCC_CLKSEL_LPTIM1_SEL_MASK                         /**< LPTIM1 KCLK selection   */
#define RCC_CLKSEL_LPTIM1_SEL_PCLK               (0x0UL << RCC_CLKSEL_LPTIM1_SEL_POS)               /**< 0x00000000 */
#define RCC_CLKSEL_LPTIM1_SEL_RCL                (0x1UL << RCC_CLKSEL_LPTIM1_SEL_POS)               /**< 0x00040000 */
#define RCC_CLKSEL_LPTIM1_SEL_MCO                (0x2UL << RCC_CLKSEL_LPTIM1_SEL_POS)               /**< 0x00080000 */
#define RCC_CLKSEL_LPTIM1_SEL_LXTAL              (0x3UL << RCC_CLKSEL_LPTIM1_SEL_POS)               /**< 0x000C0000 */   

/* Bits for RCC_AWCR */
#define RCC_AWCR_LXTALON_POS                     (0U)
#define RCC_AWCR_LXTALON_MASK                    (0x1UL << RCC_AWCR_LXTALON_POS)                    /**< 0x00000001 */
#define RCC_AWCR_LXTALON                         RCC_AWCR_LXTALON_MASK                              /**< LXTAL enable                   */
#define RCC_AWCR_LXTAL_DRV_MODE_POS              (1U)
#define RCC_AWCR_LXTAL_DRV_MODE_MASK             (0x1UL << RCC_AWCR_LXTAL_DRV_MODE_POS)             /**< 0x00000002 */
#define RCC_AWCR_LXTAL_DRV_MODE                  RCC_AWCR_LXTAL_DRV_MODE_MASK                       /**< LXTAL drive mode               */
#define RCC_AWCR_LXTALRDY_POS                    (2U)
#define RCC_AWCR_LXTALRDY_MASK                   (0x1UL << RCC_AWCR_LXTALRDY_POS)                   /**< 0x00000004 */
#define RCC_AWCR_LXTALRDY                        RCC_AWCR_LXTALRDY_MASK                             /**< LXTAL ready flag               */
#define RCC_AWCR_LXTAL_DRV_POS                   (3U)
#define RCC_AWCR_LXTAL_DRV_MASK                  (0x3UL << RCC_AWCR_LXTAL_DRV_POS)                  /**< 0x00000018 */
#define RCC_AWCR_LXTAL_DRV                       RCC_AWCR_LXTAL_DRV_MASK                            /**< LXTAL drive capability control */
#define RCC_AWCR_LXTAL_DRV_0                     (0x0UL << RCC_AWCR_LXTAL_DRV_POS)                  /**< 0x00000000 */
#define RCC_AWCR_LXTAL_DRV_1                     (0x1UL << RCC_AWCR_LXTAL_DRV_POS)                  /**< 0x00000008 */
#define RCC_AWCR_LXTAL_DRV_2                     (0x2UL << RCC_AWCR_LXTAL_DRV_POS)                  /**< 0x00000010 */
#define RCC_AWCR_LXTAL_DRV_3                     (0x3UL << RCC_AWCR_LXTAL_DRV_POS)                  /**< 0x00000018 */

#define RCC_AWCR_LXTAL_CSSON_POS                 (5U)
#define RCC_AWCR_LXTAL_CSSON_MASK                (0x1UL << RCC_AWCR_LXTAL_CSSON_POS)                /**< 0x00000020 */
#define RCC_AWCR_LXTAL_CSSON                     RCC_AWCR_LXTAL_CSSON_MASK                          /**< LXTAL CSS enable               */
#define RCC_AWCR_LXTAL_CSSD_POS                  (6U)
#define RCC_AWCR_LXTAL_CSSD_MASK                 (0x1UL << RCC_AWCR_LXTAL_CSSD_POS)                 /**< 0x00000040 */
#define RCC_AWCR_LXTAL_CSSD                      RCC_AWCR_LXTAL_CSSD_MASK                           /**< LXTAL CSS error flag           */
#define RCC_AWCR_LXTALBYP_POS                    (7U)
#define RCC_AWCR_LXTALBYP_MASK                   (0x1UL << RCC_AWCR_LXTALBYP_POS)                   /**< 0x00000080 */
#define RCC_AWCR_LXTALBYP                        RCC_AWCR_LXTALBYP_MASK                             /**< LXTAL bypass                   */
#define RCC_AWCR_RTCSEL_POS                      (8U)
#define RCC_AWCR_RTCSEL_MASK                     (0x3UL << RCC_AWCR_RTCSEL_POS)                     /**< 0x00000300 */
#define RCC_AWCR_RTCSEL                          RCC_AWCR_RTCSEL_MASK                               /**< RTC KCLK selection             */
#define RCC_AWCR_RTCSEL_NONE                    (0x0UL << RCC_AWCR_RTCSEL_POS)                      /**< 0x00000000 */
#define RCC_AWCR_RTCSEL_LXTAL                   (0x1UL << RCC_AWCR_RTCSEL_POS)                      /**< 0x00000100 */
#define RCC_AWCR_RTCSEL_RCL                     (0x2UL << RCC_AWCR_RTCSEL_POS)                      /**< 0x00000200 */

#define RCC_AWCR_RTCEN_POS                       (15U)
#define RCC_AWCR_RTCEN_MASK                      (0x1UL << RCC_AWCR_RTCEN_POS)                      /**< 0x00008000 */
#define RCC_AWCR_RTCEN                           RCC_AWCR_RTCEN_MASK                                /**< RTC enable                     */
#define RCC_AWCR_AW_RST_POS                      (16U)
#define RCC_AWCR_AW_RST_MASK                     (0x1UL << RCC_AWCR_AW_RST_POS)                     /**< 0x00010000 */
#define RCC_AWCR_AW_RST                          RCC_AWCR_AW_RST_MASK                               /**< AON domain reset               */
#define RCC_AWCR_LXTAL_STAB_SEL_POS              (20U)
#define RCC_AWCR_LXTAL_STAB_SEL_MASK             (0x3UL << RCC_AWCR_LXTAL_STAB_SEL_POS)             /**< 0x00300000 */
#define RCC_AWCR_LXTAL_STAB_SEL                  RCC_AWCR_LXTAL_STAB_SEL_MASK                       /**< Number of LXTAL stable clock cycles */

/* Bits for RCC_CSR2 */
#define RCC_CSR2_RCLON_POS                       (0U)
#define RCC_CSR2_RCLON_MASK                      (0x1UL << RCC_CSR2_RCLON_POS)                      /**< 0x00000001 */
#define RCC_CSR2_RCLON                           RCC_CSR2_RCLON_MASK                                /**< RCL enable            */
#define RCC_CSR2_RCLRDY_POS                      (1U)
#define RCC_CSR2_RCLRDY_MASK                     (0x1UL << RCC_CSR2_RCLRDY_POS)                     /**< 0x00000002 */
#define RCC_CSR2_RCLRDY                          RCC_CSR2_RCLRDY_MASK                               /**< RCL ready flag        */
#define RCC_CSR2_LOCKUP_RSTEN_POS                (8U)
#define RCC_CSR2_LOCKUP_RSTEN_MASK               (0x1UL << RCC_CSR2_LOCKUP_RSTEN_POS)               /**< 0x00000100 */
#define RCC_CSR2_LOCKUP_RSTEN                    RCC_CSR2_LOCKUP_RSTEN_MASK                         /**< LOCKUP reset enable   */
#define RCC_CSR2_NRST_MODE_POS                   (12U)
#define RCC_CSR2_NRST_MODE_MASK                  (0x1UL << RCC_CSR2_NRST_MODE_POS)                  /**< 0x00001000 */
#define RCC_CSR2_NRST_MODE                       RCC_CSR2_NRST_MODE_MASK                            /**< NRST pin selection   */
#define RCC_CSR2_RMVF_POS                        (16U)
#define RCC_CSR2_RMVF_MASK                       (0x1UL << RCC_CSR2_RMVF_POS)                       /**< 0x00010000 */
#define RCC_CSR2_RMVF                            RCC_CSR2_RMVF_MASK                                 /**< Clear reset flag      */
#define RCC_CSR2_PVD_RSTF_POS                    (23U)
#define RCC_CSR2_PVD_RSTF_MASK                   (0x1UL << RCC_CSR2_PVD_RSTF_POS)                   /**< 0x00800000 */
#define RCC_CSR2_PVD_RSTF                        RCC_CSR2_PVD_RSTF_MASK                             /**< PVD reset flag        */
#define RCC_CSR2_LOCKUP_RSTF_POS                 (24U)
#define RCC_CSR2_LOCKUP_RSTF_MASK                (0x1UL << RCC_CSR2_LOCKUP_RSTF_POS)                /**< 0x01000000 */
#define RCC_CSR2_LOCKUP_RSTF                     RCC_CSR2_LOCKUP_RSTF_MASK                          /**< LOCKUP reset flag     */
#define RCC_CSR2_NRST_RSTF_POS                   (26U)
#define RCC_CSR2_NRST_RSTF_MASK                  (0x1UL << RCC_CSR2_NRST_RSTF_POS)                  /**< 0x04000000 */
#define RCC_CSR2_NRST_RSTF                       RCC_CSR2_NRST_RSTF_MASK                            /**< NRST pin reset flag   */
#define RCC_CSR2_POR_RSTF_POS                    (27U)
#define RCC_CSR2_POR_RSTF_MASK                   (0x1UL << RCC_CSR2_POR_RSTF_POS)                   /**< 0x08000000 */
#define RCC_CSR2_POR_RSTF                        RCC_CSR2_POR_RSTF_MASK                             /**< POR or BOR reset flag */
#define RCC_CSR2_SW_RSTF_POS                     (28U)
#define RCC_CSR2_SW_RSTF_MASK                    (0x1UL << RCC_CSR2_SW_RSTF_POS)                    /**< 0x10000000 */
#define RCC_CSR2_SW_RSTF                         RCC_CSR2_SW_RSTF_MASK                              /**< Software reset flag   */
#define RCC_CSR2_IWDG_RSTF_POS                   (29U)
#define RCC_CSR2_IWDG_RSTF_MASK                  (0x1UL << RCC_CSR2_IWDG_RSTF_POS)                  /**< 0x20000000 */
#define RCC_CSR2_IWDG_RSTF                       RCC_CSR2_IWDG_RSTF_MASK                            /**< IWDG  reset flag      */

/* Bits for RCC_RCLCAL */
#define RCC_RCLCAL_RCL_CAL_POS                   (0U)
#define RCC_RCLCAL_RCL_CAL_MASK                  (0x1FUL << RCC_RCLCAL_RCL_CAL_POS)                 /**< 0x0000001F */
#define RCC_RCLCAL_RCL_CAL                       RCC_RCLCAL_RCL_CAL_MASK                            /**< RCL calibration value */

/* Bits for RCC_RCHCAL */
#define RCC_RCHCAL_RCH_CAL_FINE_POS              (0U)
#define RCC_RCHCAL_RCH_CAL_FINE_MASK             (0x3FUL << RCC_RCHCAL_RCH_CAL_FINE_POS)            /**< 0x0000003F */
#define RCC_RCHCAL_RCH_CAL_FINE                  RCC_RCHCAL_RCH_CAL_FINE_MASK                       /**< RCH fine calibration value   */
#define RCC_RCHCAL_RCH_CAL_COARSE_POS            (8U)
#define RCC_RCHCAL_RCH_CAL_COARSE_MASK           (0x3UL << RCC_RCHCAL_RCH_CAL_COARSE_POS)           /**< 0x00000300 */
#define RCC_RCHCAL_RCH_CAL_COARSE                RCC_RCHCAL_RCH_CAL_COARSE_MASK                     /**< RCL coarse calibration value */

/*-----------------------------------------------------------------------------------------------
                                       RTC  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for RTC_TR */
#define RTC_TR_SU_POS                            (0U)
#define RTC_TR_SU_MASK                           (0xFUL << RTC_TR_SU_POS)                           /**< 0x0000000F */
#define RTC_TR_SU                                RTC_TR_SU_MASK                                     /**< Second units in BCD format */
#define RTC_TR_ST_POS                            (4U)
#define RTC_TR_ST_MASK                           (0x7UL << RTC_TR_ST_POS)                           /**< 0x00000070 */
#define RTC_TR_ST                                RTC_TR_ST_MASK                                     /**< Second tens in BCD format  */
#define RTC_TR_MNU_POS                           (8U)
#define RTC_TR_MNU_MASK                          (0xFUL << RTC_TR_MNU_POS)                          /**< 0x00000F00 */
#define RTC_TR_MNU                               RTC_TR_MNU_MASK                                    /**< Minute units in BCD format */
#define RTC_TR_MNT_POS                           (12U)
#define RTC_TR_MNT_MASK                          (0x7UL << RTC_TR_MNT_POS)                          /**< 0x00007000 */
#define RTC_TR_MNT                               RTC_TR_MNT_MASK                                    /**< Minute tens in BCD format  */
#define RTC_TR_HU_POS                            (16U)
#define RTC_TR_HU_MASK                           (0xFUL << RTC_TR_HU_POS)                           /**< 0x000F0000 */
#define RTC_TR_HU                                RTC_TR_HU_MASK                                     /**< Hour units in BCD format   */
#define RTC_TR_HT_POS                            (20U)
#define RTC_TR_HT_MASK                           (0x3UL << RTC_TR_HT_POS)                           /**< 0x00300000 */
#define RTC_TR_HT                                RTC_TR_HT_MASK                                     /**< Hour tens in BCD format    */

/* Bits for RTC_DR */
#define RTC_DR_DU_POS                            (0U)
#define RTC_DR_DU_MASK                           (0xFUL << RTC_DR_DU_POS)                           /**< 0x0000000F */
#define RTC_DR_DU                                RTC_DR_DU_MASK                                     /**< Date units in BCD format  */
#define RTC_DR_DT_POS                            (4U)
#define RTC_DR_DT_MASK                           (0x3UL << RTC_DR_DT_POS)                           /**< 0x00000030 */
#define RTC_DR_DT                                RTC_DR_DT_MASK                                     /**< Date tens in BCD format   */
#define RTC_DR_MU_POS                            (8U)
#define RTC_DR_MU_MASK                           (0xFUL << RTC_DR_MU_POS)                           /**< 0x00000F00 */
#define RTC_DR_MU                                RTC_DR_MU_MASK                                     /**< Month units in BCD format */
#define RTC_DR_MT_POS                            (12U)
#define RTC_DR_MT_MASK                           (0x1UL << RTC_DR_MT_POS)                           /**< 0x00001000 */
#define RTC_DR_MT                                RTC_DR_MT_MASK                                     /**< Month tens in BCD format  */
#define RTC_DR_WDU_POS                           (13U)
#define RTC_DR_WDU_MASK                          (0x7UL << RTC_DR_WDU_POS)                          /**< 0x0000E000 */
#define RTC_DR_WDU                               RTC_DR_WDU_MASK                                    /**< Week day units            */
#define RTC_DR_YU_POS                            (16U)
#define RTC_DR_YU_MASK                           (0xFUL << RTC_DR_YU_POS)                           /**< 0x000F0000 */
#define RTC_DR_YU                                RTC_DR_YU_MASK                                     /**< Year units in BCD format  */
#define RTC_DR_YT_POS                            (20U)
#define RTC_DR_YT_MASK                           (0xFUL << RTC_DR_YT_POS)                           /**< 0x00F00000 */
#define RTC_DR_YT                                RTC_DR_YT_MASK                                     /**< Year tens in BCD format   */

/* Bits for RTC_SSR */
#define RTC_SSR_SS_POS                           (0U)
#define RTC_SSR_SS_MASK                          (0xFFUL << RTC_SSR_SS_POS)                         /**< 0x000000FF */
#define RTC_SSR_SS                               RTC_SSR_SS_MASK                                    /**< Sub second value          */

/* Bits for RTC_CSR */
#define RTC_CSR_MODSTA_POS                       (6U)
#define RTC_CSR_MODSTA_MASK                      (0x1UL << RTC_CSR_MODSTA_POS)                      /**< 0x00000040 */
#define RTC_CSR_MODSTA                           RTC_CSR_MODSTA_MASK                                /**< RTC mode status           */
#define RTC_CSR_MODSEL_POS                       (7U)
#define RTC_CSR_MODSEL_MASK                      (0x1UL << RTC_CSR_MODSEL_POS)                      /**< 0x00000080 */
#define RTC_CSR_MODSEL                           RTC_CSR_MODSEL_MASK                                /**< RTC mode selection        */
#define RTC_CSR_CALSTA_POS                       (16U)
#define RTC_CSR_CALSTA_MASK                      (0x1UL << RTC_CSR_CALSTA_POS)                      /**< 0x00010000 */
#define RTC_CSR_CALSTA                           RTC_CSR_CALSTA_MASK                                /**< RTC smooth digital calibration status */

/* Bits for RTC_CR */
#define RTC_CR_ALARME_POS                        (8U)
#define RTC_CR_ALARME_MASK                       (0x1UL << RTC_CR_ALARME_POS)                       /**< 0x00000100 */
#define RTC_CR_ALARME                            RTC_CR_ALARME_MASK                                 /**< Alarm enable                   */
#define RTC_CR_WUTIM1E_POS                       (9U)
#define RTC_CR_WUTIM1E_MASK                      (0x1UL << RTC_CR_WUTIM1E_POS)                      /**< 0x00000200 */
#define RTC_CR_WUTIM1E                           RTC_CR_WUTIM1E_MASK                                /**< Wakeup timer1 enable           */
#define RTC_CR_WUTIM2E_POS                       (10U)
#define RTC_CR_WUTIM2E_MASK                      (0x1UL << RTC_CR_WUTIM2E_POS)                      /**< 0x00000400 */
#define RTC_CR_WUTIM2E                           RTC_CR_WUTIM2E_MASK                                /**< Wakeup timer2 enable           */
#define RTC_CR_ALARMIE_POS                       (12U)
#define RTC_CR_ALARMIE_MASK                      (0x1UL << RTC_CR_ALARMIE_POS)                      /**< 0x00001000 */
#define RTC_CR_ALARMIE                           RTC_CR_ALARMIE_MASK                                /**< Alarm interrupt enable         */
#define RTC_CR_CALIE_POS                         (13U)
#define RTC_CR_CALIE_MASK                        (0x1UL << RTC_CR_CALIE_POS)                        /**< 0x00002000 */
#define RTC_CR_CALIE                             RTC_CR_CALIE_MASK                                  /**< Calibration enable             */
#define RTC_CR_OUTEN_POS                         (19U)
#define RTC_CR_OUTEN_MASK                        (0x1UL << RTC_CR_OUTEN_POS)                        /**< 0x00080000 */
#define RTC_CR_OUTEN                             RTC_CR_OUTEN_MASK                                  /**< RTC_OUT output enable          */
#define RTC_CR_POL_POS                           (20U)
#define RTC_CR_POL_MASK                          (0x1UL << RTC_CR_POL_POS)                          /**< 0x00100000 */
#define RTC_CR_POL                               RTC_CR_POL_MASK                                    /**< Output polarity                */
#define RTC_CR_OUT_SEL_POS                       (21U)
#define RTC_CR_OUT_SEL_MASK                      (0x7UL << RTC_CR_OUT_SEL_POS)                      /**< 0x00E00000 */
#define RTC_CR_OUT_SEL                           RTC_CR_OUT_SEL_MASK                                /**< Output selection               */
#define RTC_CR_OUT_SEL_APRE                      (0x0UL << RTC_CR_OUT_SEL_POS)                      /**< 0x00000000 */
#define RTC_CR_OUT_SEL_SPRE                      (0x1UL << RTC_CR_OUT_SEL_POS)                      /**< 0x00200000 */
#define RTC_CR_OUT_SEL_ALARMF                    (0x2UL << RTC_CR_OUT_SEL_POS)                      /**< 0x00400000 */
#define RTC_CR_OUT_SEL_MIN                       (0x4UL << RTC_CR_OUT_SEL_POS)                      /**< 0x00800000 */
#define RTC_CR_OUT_SEL_HOUR                      (0x5UL << RTC_CR_OUT_SEL_POS)                      /**< 0x00A00000 */
#define RTC_CR_OUT_SEL_DAY                       (0x6UL << RTC_CR_OUT_SEL_POS)                      /**< 0x00C00000 */
#define RTC_CR_OUT_SEL_CAL                       (0x7UL << RTC_CR_OUT_SEL_POS)                      /**< 0x00E00000 */

#define RTC_CR_WUTIM1IE_POS                      (27U)
#define RTC_CR_WUTIM1IE_MASK                     (0x1UL << RTC_CR_WUTIM1IE_POS)                     /**< 0x08000000 */
#define RTC_CR_WUTIM1IE                          RTC_CR_WUTIM1IE_MASK                               /**< Wakeup timer1 interrupt enable */
#define RTC_CR_WUTIM2IE_POS                      (28U)
#define RTC_CR_WUTIM2IE_MASK                     (0x1UL << RTC_CR_WUTIM2IE_POS)                     /**< 0x10000000 */
#define RTC_CR_WUTIM2IE                          RTC_CR_WUTIM2IE_MASK                               /**< Wakeup timer2 interrupt enable */

/* Bits for RTC_WUTIM1 */
#define RTC_WUTIM1_PERIOD_POS                    (0U)
#define RTC_WUTIM1_PERIOD_MASK                   (0xFUL << RTC_WUTIM1_PERIOD_POS)                   /**< 0x0000000F */
#define RTC_WUTIM1_PERIOD                        RTC_WUTIM1_PERIOD_MASK                             /**< Wakeup auto-reload 1 value bits */

/* Bits for RTC_WUTIM2 */
#define RTC_WUTIM2_PERIOD_POS                    (0U)
#define RTC_WUTIM2_PERIOD_MASK                   (0xFUL << RTC_WUTIM2_PERIOD_POS)                   /**< 0x0000000F */
#define RTC_WUTIM2_PERIOD                        RTC_WUTIM2_PERIOD_MASK                             /**< Wakeup auto-reload 2 value bits */

/* Bits for RTC_WPR */
#define RTC_WPR_KEY_POS                          (0U)
#define RTC_WPR_KEY_MASK                         (0xFFUL << RTC_WPR_KEY_POS)                        /**< 0x000000FF */
#define RTC_WPR_KEY                              RTC_WPR_KEY_MASK                                   /**< Write protection key            */

/* Bits for RTC_CALR */
#define RTC_CALR_CALM_POS                        (0U)
#define RTC_CALR_CALM_MASK                       (0x1FFUL << RTC_CALR_CALM_POS)                     /**< 0x000001FF */
#define RTC_CALR_CALM                            RTC_CALR_CALM_MASK                                 /**< Calibration minus                     */
#define RTC_CALR_CALP_POS                        (15U)
#define RTC_CALR_CALP_MASK                       (0x1UL << RTC_CALR_CALP_POS)                       /**< 0x00008000 */
#define RTC_CALR_CALP                            RTC_CALR_CALP_MASK                                 /**< Increase frequency of RTC by 488.5ppm */

/* Bits for RTC_ALARMR */
#define RTC_ALARMR_SU_POS                        (0U)
#define RTC_ALARMR_SU_MASK                       (0xFUL << RTC_ALARMR_SU_POS)                       /**< 0x0000000F */
#define RTC_ALARMR_SU                            RTC_ALARMR_SU_MASK                                 /**< Second units in BCD format */
#define RTC_ALARMR_ST_POS                        (4U)
#define RTC_ALARMR_ST_MASK                       (0x7UL << RTC_ALARMR_ST_POS)                       /**< 0x00000070 */
#define RTC_ALARMR_ST                            RTC_ALARMR_ST_MASK                                 /**< Second tens in BCD format  */
#define RTC_ALARMR_MSK1_POS                      (7U)
#define RTC_ALARMR_MSK1_MASK                     (0x1UL << RTC_ALARMR_MSK1_POS)                     /**< 0x00000080 */
#define RTC_ALARMR_MSK1                          RTC_ALARMR_MSK1_MASK                               /**< Alarm seconds mask         */
#define RTC_ALARMR_MNU_POS                       (8U)
#define RTC_ALARMR_MNU_MASK                      (0xFUL << RTC_ALARMR_MNU_POS)                      /**< 0x00000F00 */
#define RTC_ALARMR_MNU                           RTC_ALARMR_MNU_MASK                                /**< Minute units in BCD format */
#define RTC_ALARMR_MNT_POS                       (12U)
#define RTC_ALARMR_MNT_MASK                      (0x7UL << RTC_ALARMR_MNT_POS)                      /**< 0x00007000 */
#define RTC_ALARMR_MNT                           RTC_ALARMR_MNT_MASK                                /**< Minute tens in BCD format  */
#define RTC_ALARMR_MSK2_POS                      (15U)
#define RTC_ALARMR_MSK2_MASK                     (0x1UL << RTC_ALARMR_MSK2_POS)                     /**< 0x00008000 */
#define RTC_ALARMR_MSK2                          RTC_ALARMR_MSK2_MASK                               /**< Alarm minutes mask         */
#define RTC_ALARMR_HU_POS                        (16U)
#define RTC_ALARMR_HU_MASK                       (0xFUL << RTC_ALARMR_HU_POS)                       /**< 0x000F0000 */
#define RTC_ALARMR_HU                            RTC_ALARMR_HU_MASK                                 /**< Hour units in BCD format   */
#define RTC_ALARMR_HT_POS                        (20U)
#define RTC_ALARMR_HT_MASK                       (0x3UL << RTC_ALARMR_HT_POS)                       /**< 0x00300000 */
#define RTC_ALARMR_HT                            RTC_ALARMR_HT_MASK                                 /**< Hour tens in BCD format    */
#define RTC_ALARMR_MSK3_POS                      (23U)
#define RTC_ALARMR_MSK3_MASK                     (0x1UL << RTC_ALARMR_MSK3_POS)                     /**< 0x00800000 */
#define RTC_ALARMR_MSK3                          RTC_ALARMR_MSK3_MASK                               /**< Alarm hours mask           */
#define RTC_ALARMR_MSKALL                        (RTC_ALARMR_MSK1  | RTC_ALARMR_MSK2 \
                                                                   | RTC_ALARMR_MSK3)               /**< 0x00808080 */

/* Bits for RTC_SR */
#define RTC_SR_ALARMF_POS                        (0U)
#define RTC_SR_ALARMF_MASK                       (0x1UL << RTC_SR_ALARMF_POS)                       /**< 0x00000001 */
#define RTC_SR_ALARMF                            RTC_SR_ALARMF_MASK                                 /**< Alarm flag         */
#define RTC_SR_CALF_POS                          (1U)
#define RTC_SR_CALF_MASK                         (0x1UL << RTC_SR_CALF_POS)                         /**< 0x00000002 */
#define RTC_SR_CALF                              RTC_SR_CALF_MASK                                   /**< Calibration flag   */
#define RTC_SR_WUTIM1F_POS                       (6U)
#define RTC_SR_WUTIM1F_MASK                      (0x1UL << RTC_SR_WUTIM1F_POS)                      /**< 0x00000040 */
#define RTC_SR_WUTIM1F                           RTC_SR_WUTIM1F_MASK                                /**< Wakeup timer1 flag */
#define RTC_SR_WUTIM2F_POS                       (7U)
#define RTC_SR_WUTIM2F_MASK                      (0x1UL << RTC_SR_WUTIM2F_POS)                      /**< 0x00000080 */
#define RTC_SR_WUTIM2F                           RTC_SR_WUTIM2F_MASK                                /**< Wakeup timer2 flag */

/* Bits for RTC_ISR */
#define RTC_ISR_ALARMIF_POS                      (0U)
#define RTC_ISR_ALARMIF_MASK                     (0x1UL << RTC_ISR_ALARMIF_POS)                     /**< 0x00000001 */
#define RTC_ISR_ALARMIF                          RTC_ISR_ALARMIF_MASK                               /**< Alarm interrupt flag         */
#define RTC_ISR_CALIF_POS                        (1U)
#define RTC_ISR_CALIF_MASK                       (0x1UL << RTC_ISR_CALIF_POS)                       /**< 0x00000002 */
#define RTC_ISR_CALIF                            RTC_ISR_CALIF_MASK                                 /**< Calibration interrupt flag   */
#define RTC_ISR_WUTIM1IF_POS                     (6U)
#define RTC_ISR_WUTIM1IF_MASK                    (0x1UL << RTC_ISR_WUTIM1IF_POS)                    /**< 0x00000040 */
#define RTC_ISR_WUTIM1IF                         RTC_ISR_WUTIM1IF_MASK                              /**< Wakeup timer1 interrupt flag */
#define RTC_ISR_WUTIM2IF_POS                     (7U)
#define RTC_ISR_WUTIM2IF_MASK                    (0x1UL << RTC_ISR_WUTIM2IF_POS)                    /**< 0x00000080 */
#define RTC_ISR_WUTIM2IF                         RTC_ISR_WUTIM2IF_MASK                              /**< Wakeup timer2 interrupt flag */

/* Bits for RTC_CLR */
#define RTC_CLR_CALARMF_POS                      (0U)
#define RTC_CLR_CALARMF_MASK                     (0x1UL << RTC_CLR_CALARMF_POS)                     /**< 0x00000001 */
#define RTC_CLR_CALARMF                          RTC_CLR_CALARMF_MASK                               /**< Clear alarm flag         */
#define RTC_CLR_CCALF_POS                        (1U)
#define RTC_CLR_CCALF_MASK                       (0x1UL << RTC_CLR_CCALF_POS)                       /**< 0x00000002 */
#define RTC_CLR_CCALF                            RTC_CLR_CCALF_MASK                                 /**< Clear calibration flag   */
#define RTC_CLR_CWUTIM1F_POS                     (6U)
#define RTC_CLR_CWUTIM1F_MASK                    (0x1UL << RTC_CLR_CWUTIM1F_POS)                    /**< 0x00000040 */
#define RTC_CLR_CWUTIM1F                         RTC_CLR_CWUTIM1F_MASK                              /**< Clear wakeup timer1 flag */
#define RTC_CLR_CWUTIM2F_POS                     (7U)
#define RTC_CLR_CWUTIM2F_MASK                    (0x1UL << RTC_CLR_CWUTIM2F_POS)                    /**< 0x00000080 */
#define RTC_CLR_CWUTIM2F                         RTC_CLR_CWUTIM2F_MASK                              /**< Clear wakeup timer2 flag */


/*-----------------------------------------------------------------------------------------------
                                       SPI  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for SPI_CR1 */
#define SPI_CR1_SPE_POS                          (0U)
#define SPI_CR1_SPE_MASK                         (0x1UL << SPI_CR1_SPE_POS)                         /**< 0x00000001 */
#define SPI_CR1_SPE                              SPI_CR1_SPE_MASK                                   /**< Peripheral enable              */
#define SPI_CR1_BR_POS                           (1U)
#define SPI_CR1_BR_MASK                          (0x7UL << SPI_CR1_BR_POS)                          /**< 0x0000000E */
#define SPI_CR1_BR                               SPI_CR1_BR_MASK                                    /**< Bit baud rate control          */
#define SPI_CR1_BR_PCLK_DIV_2                    (0x0UL << SPI_CR1_BR_POS)                          /**< 0x00000000 */
#define SPI_CR1_BR_PCLK_DIV_4                    (0x1UL << SPI_CR1_BR_POS)                          /**< 0x00000002 */
#define SPI_CR1_BR_PCLK_DIV_8                    (0x2UL << SPI_CR1_BR_POS)                          /**< 0x00000004 */
#define SPI_CR1_BR_PCLK_DIV_16                   (0x3UL << SPI_CR1_BR_POS)                          /**< 0x00000006 */
#define SPI_CR1_BR_PCLK_DIV_32                   (0x4UL << SPI_CR1_BR_POS)                          /**< 0x00000008 */
#define SPI_CR1_BR_PCLK_DIV_64                   (0x5UL << SPI_CR1_BR_POS)                          /**< 0x0000000A */
#define SPI_CR1_BR_PCLK_DIV_128                  (0x6UL << SPI_CR1_BR_POS)                          /**< 0x0000000C */
#define SPI_CR1_CPHA_POS                         (4U)
#define SPI_CR1_CPHA_MASK                        (0x1UL << SPI_CR1_CPHA_POS)                        /**< 0x00000010 */
#define SPI_CR1_CPHA                             SPI_CR1_CPHA_MASK                                  /**< Clock phase                    */
#define SPI_CR1_CPOL_POS                         (5U)
#define SPI_CR1_CPOL_MASK                        (0x1UL << SPI_CR1_CPOL_POS)                        /**< 0x00000020 */
#define SPI_CR1_CPOL                             SPI_CR1_CPOL_MASK                                  /**< Clock polarity                 */
#define SPI_CR1_MSTR_POS                         (6U)
#define SPI_CR1_MSTR_MASK                        (0x1UL << SPI_CR1_MSTR_POS)                        /**< 0x00000040 */
#define SPI_CR1_MSTR                             SPI_CR1_MSTR_MASK                                  /**< Master mode selection          */
#define SPI_CR1_LSBFIRST_POS                     (8U)
#define SPI_CR1_LSBFIRST_MASK                    (0x1UL << SPI_CR1_LSBFIRST_POS)                    /**< 0x00000100 */
#define SPI_CR1_LSBFIRST                         SPI_CR1_LSBFIRST_MASK                              /**< Frame format                   */
#define SPI_CR1_NSSOE_POS                        (10U)
#define SPI_CR1_NSSOE_MASK                       (0x1UL << SPI_CR1_NSSOE_POS)                       /**< 0x00000400 */
#define SPI_CR1_NSSOE                            SPI_CR1_NSSOE_MASK                                 /**< NSS out enable                 */
#define SPI_CR1_SSM_POS                          (11U)
#define SPI_CR1_SSM_MASK                         (0x1UL << SPI_CR1_SSM_POS)                         /**< 0x00000800 */
#define SPI_CR1_SSM                              SPI_CR1_SSM_MASK                                   /**< Slave mode Software NSS enable */
#define SPI_CR1_DMAR_POS                         (16U)
#define SPI_CR1_DMAR_MASK                        (0x1UL << SPI_CR1_DMAR_POS)                        /**< 0x00010000 */
#define SPI_CR1_DMAR                             SPI_CR1_DMAR_MASK                                  /**< RX DMA request enable          */
#define SPI_CR1_DMAT_POS                         (17U)
#define SPI_CR1_DMAT_MASK                        (0x1UL << SPI_CR1_DMAT_POS)                        /**< 0x00020000 */
#define SPI_CR1_DMAT                             SPI_CR1_DMAT_MASK                                  /**< TX DMA request enable          */
#define SPI_CR1_ERRIE_POS                        (18U)
#define SPI_CR1_ERRIE_MASK                       (0x1UL << SPI_CR1_ERRIE_POS)                       /**< 0x00040000 */
#define SPI_CR1_ERRIE                            SPI_CR1_ERRIE_MASK                                 /**< Error interrupt enable         */
#define SPI_CR1_RXFNEIE_POS                      (20U)
#define SPI_CR1_RXFNEIE_MASK                     (0x1UL << SPI_CR1_RXFNEIE_POS)                     /**< 0x00100000 */
#define SPI_CR1_RXFNEIE                          SPI_CR1_RXFNEIE_MASK                               /**< RX data register not empty interrupt enable */
#define SPI_CR1_TXFEIE_POS                       (25U)
#define SPI_CR1_TXFEIE_MASK                      (0x1UL << SPI_CR1_TXFEIE_POS)                      /**< 0x02000000 */
#define SPI_CR1_TXFEIE                           SPI_CR1_TXFEIE_MASK                                /**< TX data register empty interrupt enable */

/* Bits for SPI_CR2 */
#define SPI_CR2_NSSO_POS                         (0U)
#define SPI_CR2_NSSO_MASK                        (0x1UL << SPI_CR2_NSSO_POS)                        /**< 0x00000001 */
#define SPI_CR2_NSSO                             SPI_CR2_NSSO_MASK                                  /**< NSS out level */

/* Bits for SPI_ISR */
#define SPI_ISR_MMF_POS                          (0U)
#define SPI_ISR_MMF_MASK                         (0x1UL << SPI_ISR_MMF_POS)                         /**< 0x00000001 */
#define SPI_ISR_MMF                              SPI_ISR_MMF_MASK                                   /**< Master mode confilct flag          */
#define SPI_ISR_OVR_POS                          (2U)
#define SPI_ISR_OVR_MASK                         (0x1UL << SPI_ISR_OVR_POS)                         /**< 0x00000004 */
#define SPI_ISR_OVR                              SPI_ISR_OVR_MASK                                   /**< RX FIFO overrun flag               */
#define SPI_ISR_BUSY_POS                         (4U)
#define SPI_ISR_BUSY_MASK                        (0x1UL << SPI_ISR_BUSY_POS)                        /**< 0x00000010 */
#define SPI_ISR_BUSY                             SPI_ISR_BUSY_MASK                                  /**< Busy flag                          */
#define SPI_ISR_RXFNE_POS                        (6U)
#define SPI_ISR_RXFNE_MASK                       (0x1UL << SPI_ISR_RXFNE_POS)                       /**< 0x00000040 */
#define SPI_ISR_RXFNE                            SPI_ISR_RXFNE_MASK                                 /**< RX data register not empty flag    */
#define SPI_ISR_TXFE_POS                         (8U)
#define SPI_ISR_TXFE_MASK                        (0x1UL << SPI_ISR_TXFE_POS)                        /**< 0x00000100 */
#define SPI_ISR_TXFE                             SPI_ISR_TXFE_MASK                                  /**< TX data register empty flag        */

/* Bits for SPI_ICR */
#define SPI_ICR_MMFCF_POS                        (0U)
#define SPI_ICR_MMFCF_MASK                       (0x1UL << SPI_ICR_MMFCF_POS)                       /**< 0x00000001 */
#define SPI_ICR_MMFCF                            SPI_ICR_MMFCF_MASK                                 /**< MMF flag clear */
#define SPI_ICR_OVRCF_POS                        (2U)
#define SPI_ICR_OVRCF_MASK                       (0x1UL << SPI_ICR_OVRCF_POS)                       /**< 0x00000004 */
#define SPI_ICR_OVRCF                            SPI_ICR_OVRCF_MASK                                 /**< OVR flag clear */

/* Bits for SPI_DR */
#define SPI_DR_DR_POS                            (0U)
#define SPI_DR_DR_MASK                           (0xFFUL << SPI_DR_DR_POS)                          /**< 0x000000FF */
#define SPI_DR_DR                                SPI_DR_DR_MASK                                     /**< 8 bits Tx or Rx data */


/*-----------------------------------------------------------------------------------------------
                                       TIM  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for TIM_CR1 */
#define TIM_CR1_CEN_POS                          (0U)
#define TIM_CR1_CEN_MASK                         (0x1UL << TIM_CR1_CEN_POS)                         /**< 0x00000001 */
#define TIM_CR1_CEN                              TIM_CR1_CEN_MASK                                   /**< Counter enable                  */

#define TIM_CR1_UDIS_POS                         (1U)
#define TIM_CR1_UDIS_MASK                        (0x1UL << TIM_CR1_UDIS_POS)                        /**< 0x00000002 */
#define TIM_CR1_UDIS                             TIM_CR1_UDIS_MASK                                  /**< Update disable                  */

#define TIM_CR1_URS_POS                          (2U)
#define TIM_CR1_URS_MASK                         (0x1UL << TIM_CR1_URS_POS)                         /**< 0x00000004 */
#define TIM_CR1_URS                              TIM_CR1_URS_MASK                                   /**< Update request source           */

#define TIM_CR1_OPM_POS                          (3U)
#define TIM_CR1_OPM_MASK                         (0x1UL << TIM_CR1_OPM_POS)                         /**< 0x00000008 */
#define TIM_CR1_OPM                              TIM_CR1_OPM_MASK                                   /**< One pulse mode                  */

#define TIM_CR1_DIR_POS                          (4U)
#define TIM_CR1_DIR_MASK                         (0x1UL << TIM_CR1_DIR_POS)                         /**< 0x00000010 */
#define TIM_CR1_DIR                              TIM_CR1_DIR_MASK                                   /**< Direction                       */

#define TIM_CR1_CMS_POS                          (5U)
#define TIM_CR1_CMS_MASK                         (0x3UL << TIM_CR1_CMS_POS)                         /**< 0x00000060 */
#define TIM_CR1_CMS                              TIM_CR1_CMS_MASK                                   /**< Center-aligned mode selection   */
#define TIM_CR1_CMS_CENTER_DOWN                  (0x1UL << TIM_CR1_CMS_POS)                         /**< 0x00000020 */
#define TIM_CR1_CMS_CENTER_UP                    (0x2UL << TIM_CR1_CMS_POS)                         /**< 0x00000040 */
#define TIM_CR1_CMS_CENTER_UP_DOWN               (0x3UL << TIM_CR1_CMS_POS)                         /**< 0x00000060 */

#define TIM_CR1_ARPE_POS                         (7U)
#define TIM_CR1_ARPE_MASK                        (0x1UL << TIM_CR1_ARPE_POS)                        /**< 0x00000080 */
#define TIM_CR1_ARPE                             TIM_CR1_ARPE_MASK                                  /**< Auto-reload preload enable      */

#define TIM_CR1_CLK_DIV_POS                      (8U)
#define TIM_CR1_CLK_DIV_MASK                     (0x3UL << TIM_CR1_CLK_DIV_POS)                     /**< 0x00000300 */
#define TIM_CR1_CLK_DIV                          TIM_CR1_CLK_DIV_MASK                               /**< Clock division                  */
#define TIM_CR1_CLK_DIV1                         (0x0UL << TIM_CR1_CLK_DIV_POS)                     /**< 0x00000000 */
#define TIM_CR1_CLK_DIV2                         (0x1UL << TIM_CR1_CLK_DIV_POS)                     /**< 0x00000100 */
#define TIM_CR1_CLK_DIV4                         (0x2UL << TIM_CR1_CLK_DIV_POS)                     /**< 0x00000200 */

/* Bits for TIM_CR2 */
#define TIM_CR2_CC_PRECR_POS                     (0U)
#define TIM_CR2_CC_PRECR_MASK                    (0x1UL << TIM_CR2_CC_PRECR_POS)                    /**< 0x00000001 */
#define TIM_CR2_CC_PRECR                         TIM_CR2_CC_PRECR_MASK                              /**< Capture/compare preloaded control        */
#define TIM_CR2_CCU_SEL_POS                      (2U)
#define TIM_CR2_CCU_SEL_MASK                     (0x1UL << TIM_CR2_CCU_SEL_POS)                     /**< 0x00000004 */
#define TIM_CR2_CCU_SEL                          TIM_CR2_CCU_SEL_MASK                               /**< Capture/compare control update selection */
#define TIM_CR2_CC_DMASEL_POS                    (3U)
#define TIM_CR2_CC_DMASEL_MASK                   (0x1UL << TIM_CR2_CC_DMASEL_POS)                   /**< 0x00000008 */
#define TIM_CR2_CC_DMASEL                        TIM_CR2_CC_DMASEL_MASK                             /**< Capture/compare DMA selection            */

#define TIM_CR2_MM_SEL_POS                       (4U)
#define TIM_CR2_MM_SEL_MASK                      (0x07UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000070 */
#define TIM_CR2_MM_SEL                           TIM_CR2_MM_SEL_MASK                                /**< Master mode selection                    */
#define TIM_CR2_MM_SEL_RESET                     (0x00UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000000 */
#define TIM_CR2_MM_SEL_ENABLE                    (0x01UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000010 */  
#define TIM_CR2_MM_SEL_UPDATE                    (0x02UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000020 */  
#define TIM_CR2_MM_SEL_CC1IF                     (0x03UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000030 */  
#define TIM_CR2_MM_SEL_OC1REF                    (0x04UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000040 */  
#define TIM_CR2_MM_SEL_OC2REF                    (0x05UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000050 */  
#define TIM_CR2_MM_SEL_OC3REF                    (0x06UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000060 */  
#define TIM_CR2_MM_SEL_OC4REF                    (0x07UL << TIM_CR2_MM_SEL_POS)                     /**< 0x00000070 */

#define TIM_CR2_TI1_XOR_SEL_POS                  (7U)
#define TIM_CR2_TI1_XOR_SEL_MASK                 (0x1UL << TIM_CR2_TI1_XOR_SEL_POS)                 /**< 0x00000080 */
#define TIM_CR2_TI1_XOR_SEL                      TIM_CR2_TI1_XOR_SEL_MASK                           /**< TI1 selection                            */

#define TIM_CR2_OIS1_POS                         (8U)
#define TIM_CR2_OIS1_MASK                        (0x1UL << TIM_CR2_OIS1_POS)                        /**< 0x00000100 */
#define TIM_CR2_OIS1                             TIM_CR2_OIS1_MASK                                  /**< Output idle state 1 (OC1 output)         */
#define TIM_CR2_OIS1N_POS                        (9U)
#define TIM_CR2_OIS1N_MASK                       (0x1UL << TIM_CR2_OIS1N_POS)                       /**< 0x00000200 */
#define TIM_CR2_OIS1N                            TIM_CR2_OIS1N_MASK                                 /**< Output idle state 1 (OC1N output)        */
#define TIM_CR2_OIS2_POS                         (10U)
#define TIM_CR2_OIS2_MASK                        (0x1UL << TIM_CR2_OIS2_POS)                        /**< 0x00000400 */
#define TIM_CR2_OIS2                             TIM_CR2_OIS2_MASK                                  /**< Output idle state 2 (OC2 output)         */
#define TIM_CR2_OIS2N_POS                        (11U)
#define TIM_CR2_OIS2N_MASK                       (0x1UL << TIM_CR2_OIS2N_POS)                       /**< 0x00000800 */
#define TIM_CR2_OIS2N                            TIM_CR2_OIS2N_MASK                                 /**< Output idle state 2 (OC2N output)        */
#define TIM_CR2_OIS3_POS                         (12U)
#define TIM_CR2_OIS3_MASK                        (0x1UL << TIM_CR2_OIS3_POS)                        /**< 0x00001000 */
#define TIM_CR2_OIS3                             TIM_CR2_OIS3_MASK                                  /**< Output idle state 3 (OC3 output)         */
#define TIM_CR2_OIS3N_POS                        (13U)
#define TIM_CR2_OIS3N_MASK                       (0x1UL << TIM_CR2_OIS3N_POS)                       /**< 0x00002000 */
#define TIM_CR2_OIS3N                            TIM_CR2_OIS3N_MASK                                 /**< Output idle state 3 (OC3N output)        */
#define TIM_CR2_OIS4_POS                         (14U)
#define TIM_CR2_OIS4_MASK                        (0x1UL << TIM_CR2_OIS4_POS)                        /**< 0x00004000 */
#define TIM_CR2_OIS4                             TIM_CR2_OIS4_MASK                                  /**< Output idle state 4 (OC4 output)         */

/* Bits for TIM_SMC */
#define TIM_SMC_SM_SEL_POS                       (0U)
#define TIM_SMC_SM_SEL_MASK                      (0x7UL << TIM_SMC_SM_SEL_POS)                      /**< 0x00000007 */
#define TIM_SMC_SM_SEL                           TIM_SMC_SM_SEL_MASK                                /**< Slave mode selection         */
#define TIM_SMC_SM_SEL_NONE                      (0x00UL << TIM_SMC_SM_SEL_POS)                     /**< 0x00000000 */  
#define TIM_SMC_SM_SEL_RESET                     (0x04UL << TIM_SMC_SM_SEL_POS)                     /**< 0x00000004 */  
#define TIM_SMC_SM_SEL_GATED                     (0x05UL << TIM_SMC_SM_SEL_POS)                     /**< 0x00000005 */ 
#define TIM_SMC_SM_SEL_TRIG                      (0x06UL << TIM_SMC_SM_SEL_POS)                     /**< 0x00000006 */ 
#define TIM_SMC_SM_SEL_EXT_MODE1                 (0x07UL << TIM_SMC_SM_SEL_POS)                     /**< 0x00000007 */

#define TIM_SMC_OCCS_POS                         (3U)
#define TIM_SMC_OCCS_MASK                        (0x1UL << TIM_SMC_OCCS_POS)                        /**< 0x00000008 */
#define TIM_SMC_OCCS                             TIM_SMC_OCCS_MASK                                  /**< OCREF clear selection        */

#define TIM_SMC_TS_POS                           (4U)
#define TIM_SMC_TS_MASK                          (0x7UL << TIM_SMC_TS_POS)                          /**< 0x00000070 */
#define TIM_SMC_TS                               TIM_SMC_TS_MASK                                    /**< Trigger selection            */
#define TIM_SMC_TS_ITR0                          (0x00UL << TIM_SMC_TS_POS)                         /**< 0x00000000 */
#define TIM_SMC_TS_TI1F_ED                       (0x04UL << TIM_SMC_TS_POS)                         /**< 0x00000040 */
#define TIM_SMC_TS_TI1FP1                        (0x05UL << TIM_SMC_TS_POS)                         /**< 0x00000050 */
#define TIM_SMC_TS_TI2FP2                        (0x06UL << TIM_SMC_TS_POS)                         /**< 0x00000060 */
#define TIM_SMC_TS_ETRF                          (0x07UL << TIM_SMC_TS_POS)                         /**< 0x00000070 */

#define TIM_SMC_MS_MOD_POS                       (7U)
#define TIM_SMC_MS_MOD_MASK                      (0x1UL << TIM_SMC_MS_MOD_POS)                      /**< 0x00000080 */
#define TIM_SMC_MS_MOD                           TIM_SMC_MS_MOD_MASK                                /**< Master/slave mode            */

#define TIM_SMC_ETF_POS                          (8U)
#define TIM_SMC_ETF_MASK                         (0x7UL << TIM_SMC_ETF_POS)                         /**< 0x00000700 */
#define TIM_SMC_ETF                              TIM_SMC_ETF_MASK                                   /**< External trigger filter      */
#define TIM_SMC_ETF_FILT_DIV1                    (0x01UL << TIM_SMC_ETF_POS)                        /**< 0x00000100 */  
#define TIM_SMC_ETF_FILT_DIV2                    (0x02UL << TIM_SMC_ETF_POS)                        /**< 0x00000200 */  
#define TIM_SMC_ETF_FILT_DIV4                    (0x03UL << TIM_SMC_ETF_POS)                        /**< 0x00000300 */  
#define TIM_SMC_ETF_FILT_DIV8                    (0x04UL << TIM_SMC_ETF_POS)                        /**< 0x00000400 */  
#define TIM_SMC_ETF_FILT_DIV16                   (0x05UL << TIM_SMC_ETF_POS)                        /**< 0x00000500 */  
#define TIM_SMC_ETF_FILT_DIV32                   (0x06UL << TIM_SMC_ETF_POS)                        /**< 0x00000600 */

#define TIM_SMC_ET_PRE_POS                       (12U)
#define TIM_SMC_ET_PRE_MASK                      (0x3UL << TIM_SMC_ET_PRE_POS)                      /**< 0x00003000 */
#define TIM_SMC_ET_PRE                           TIM_SMC_ET_PRE_MASK                                /**< External trigger prescaler   */
#define TIM_SMC_ET_PRE_DIV1                      (0x0UL << TIM_SMC_ET_PRE_POS)                      /**< 0x00000000 */
#define TIM_SMC_ET_PRE_DIV2                      (0x1UL << TIM_SMC_ET_PRE_POS)                      /**< 0x00001000 */
#define TIM_SMC_ET_PRE_DIV4                      (0x2UL << TIM_SMC_ET_PRE_POS)                      /**< 0x00002000 */
#define TIM_SMC_ET_PRE_DIV8                      (0x3UL << TIM_SMC_ET_PRE_POS)                      /**< 0x00003000 */

#define TIM_SMC_ECEN_POS                         (14U)
#define TIM_SMC_ECEN_MASK                        (0x1UL << TIM_SMC_ECEN_POS)                        /**< 0x00004000 */
#define TIM_SMC_ECEN                             TIM_SMC_ECEN_MASK                                  /**< External clock enable        */

#define TIM_SMC_ETP_POS                          (15U)
#define TIM_SMC_ETP_MASK                         (0x1UL << TIM_SMC_ETP_POS)                         /**< 0x00008000 */
#define TIM_SMC_ETP                              TIM_SMC_ETP_MASK                                   /**< External trigger polarity    */

/* Bits for TIM_DIER */
#define TIM_DIER_UIE_POS                         (0U)
#define TIM_DIER_UIE_MASK                        (0x1UL << TIM_DIER_UIE_POS)                        /**< 0x00000001 */
#define TIM_DIER_UIE                             TIM_DIER_UIE_MASK                                  /**< Update interrupt enable              */

#define TIM_DIER_CC1IE_POS                       (1U)
#define TIM_DIER_CC1IE_MASK                      (0x1UL << TIM_DIER_CC1IE_POS)                      /**< 0x00000002 */
#define TIM_DIER_CC1IE                           TIM_DIER_CC1IE_MASK                                /**< Capture/Compare 1 interrupt enable   */
#define TIM_DIER_CC2IE_POS                       (2U)
#define TIM_DIER_CC2IE_MASK                      (0x1UL << TIM_DIER_CC2IE_POS)                      /**< 0x00000004 */
#define TIM_DIER_CC2IE                           TIM_DIER_CC2IE_MASK                                /**< Capture/Compare 2 interrupt enable   */
#define TIM_DIER_CC3IE_POS                       (3U)
#define TIM_DIER_CC3IE_MASK                      (0x1UL << TIM_DIER_CC3IE_POS)                      /**< 0x00000008 */
#define TIM_DIER_CC3IE                           TIM_DIER_CC3IE_MASK                                /**< Capture/Compare 3 interrupt enable   */
#define TIM_DIER_CC4IE_POS                       (4U)
#define TIM_DIER_CC4IE_MASK                      (0x1UL << TIM_DIER_CC4IE_POS)                      /**< 0x00000010 */
#define TIM_DIER_CC4IE                           TIM_DIER_CC4IE_MASK                                /**< Capture/Compare 4 interrupt enable   */

#define TIM_DIER_COMIE_POS                       (5U)
#define TIM_DIER_COMIE_MASK                      (0x1UL << TIM_DIER_COMIE_POS)                      /**< 0x00000020 */
#define TIM_DIER_COMIE                           TIM_DIER_COMIE_MASK                                /**< COM interrupt enable                 */
#define TIM_DIER_TIE_POS                         (6U)
#define TIM_DIER_TIE_MASK                        (0x1UL << TIM_DIER_TIE_POS)                        /**< 0x00000040 */
#define TIM_DIER_TIE                             TIM_DIER_TIE_MASK                                  /**< Trigger interrupt enable             */
#define TIM_DIER_BIE_POS                         (7U)
#define TIM_DIER_BIE_MASK                        (0x1UL << TIM_DIER_BIE_POS)                        /**< 0x00000080 */
#define TIM_DIER_BIE                             TIM_DIER_BIE_MASK                                  /**< Break interrupt enable               */

#define TIM_DIER_UDMAEN_POS                      (8U)
#define TIM_DIER_UDMAEN_MASK                     (0x1UL << TIM_DIER_UDMAEN_POS)                     /**< 0x00000100 */
#define TIM_DIER_UDMAEN                          TIM_DIER_UDMAEN_MASK                               /**< Update DMA request enable            */
#define TIM_DIER_CC1_DMAEN_POS                   (9U)
#define TIM_DIER_CC1_DMAEN_MASK                  (0x1UL << TIM_DIER_CC1_DMAEN_POS)                  /**< 0x00000200 */
#define TIM_DIER_CC1_DMAEN                       TIM_DIER_CC1_DMAEN_MASK                            /**< Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2_DMAEN_POS                   (10U)
#define TIM_DIER_CC2_DMAEN_MASK                  (0x1UL << TIM_DIER_CC2_DMAEN_POS)                  /**< 0x00000400 */
#define TIM_DIER_CC2_DMAEN                       TIM_DIER_CC2_DMAEN_MASK                            /**< Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3_DMAEN_POS                   (11U)
#define TIM_DIER_CC3_DMAEN_MASK                  (0x1UL << TIM_DIER_CC3_DMAEN_POS)                  /**< 0x00000800 */
#define TIM_DIER_CC3_DMAEN                       TIM_DIER_CC3_DMAEN_MASK                            /**< Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4_DMAEN_POS                   (12U)
#define TIM_DIER_CC4_DMAEN_MASK                  (0x1UL << TIM_DIER_CC4_DMAEN_POS)                  /**< 0x00001000 */
#define TIM_DIER_CC4_DMAEN                       TIM_DIER_CC4_DMAEN_MASK                            /**< Capture/Compare 4 DMA request enable */
#define TIM_DIER_COM_DMAEN_POS                   (13U)
#define TIM_DIER_COM_DMAEN_MASK                  (0x1UL << TIM_DIER_COM_DMAEN_POS)                  /**< 0x00002000 */
#define TIM_DIER_COM_DMAEN                       TIM_DIER_COM_DMAEN_MASK                            /**< COM DMA request enable               */
#define TIM_DIER_TDMAEN_POS                      (14U)
#define TIM_DIER_TDMAEN_MASK                     (0x1UL << TIM_DIER_TDMAEN_POS)                     /**< 0x00004000 */
#define TIM_DIER_TDMAEN                          TIM_DIER_TDMAEN_MASK                               /**< Trigger DMA request enable           */

/* Bits for TIM_SR */
#define TIM_SR_UIF_POS                           (0U)
#define TIM_SR_UIF_MASK                          (0x1UL << TIM_SR_UIF_POS)                          /**< 0x00000001 */
#define TIM_SR_UIF                               TIM_SR_UIF_MASK                                    /**< Update interrupt flag                */
#define TIM_SR_CC1IF_POS                         (1U)
#define TIM_SR_CC1IF_MASK                        (0x1UL << TIM_SR_CC1IF_POS)                        /**< 0x00000002 */
#define TIM_SR_CC1IF                             TIM_SR_CC1IF_MASK                                  /**< Capture/Compare 1 interrupt flag     */
#define TIM_SR_CC2IF_POS                         (2U)
#define TIM_SR_CC2IF_MASK                        (0x1UL << TIM_SR_CC2IF_POS)                        /**< 0x00000004 */
#define TIM_SR_CC2IF                             TIM_SR_CC2IF_MASK                                  /**< Capture/Compare 2 interrupt flag     */
#define TIM_SR_CC3IF_POS                         (3U)
#define TIM_SR_CC3IF_MASK                        (0x1UL << TIM_SR_CC3IF_POS)                        /**< 0x00000008 */
#define TIM_SR_CC3IF                             TIM_SR_CC3IF_MASK                                  /**< Capture/Compare 3 interrupt flag     */
#define TIM_SR_CC4IF_POS                         (4U)
#define TIM_SR_CC4IF_MASK                        (0x1UL << TIM_SR_CC4IF_POS)                        /**< 0x00000010 */
#define TIM_SR_CC4IF                             TIM_SR_CC4IF_MASK                                  /**< Capture/Compare 4 interrupt flag     */

#define TIM_SR_COMIF_POS                         (5U)
#define TIM_SR_COMIF_MASK                        (0x1UL << TIM_SR_COMIF_POS)                        /**< 0x00000020 */
#define TIM_SR_COMIF                             TIM_SR_COMIF_MASK                                  /**< COM interrupt flag                   */
#define TIM_SR_TIF_POS                           (6U)
#define TIM_SR_TIF_MASK                          (0x1UL << TIM_SR_TIF_POS)                          /**< 0x00000040 */
#define TIM_SR_TIF                               TIM_SR_TIF_MASK                                    /**< Trigger interrupt flag               */
#define TIM_SR_BIF_POS                           (7U)
#define TIM_SR_BIF_MASK                          (0x1UL << TIM_SR_BIF_POS)                          /**< 0x00000080 */
#define TIM_SR_BIF                               TIM_SR_BIF_MASK                                    /**< Break interrupt flag                 */

#define TIM_SR_CC1OF_POS                         (9U)
#define TIM_SR_CC1OF_MASK                        (0x1UL << TIM_SR_CC1OF_POS)                        /**< 0x00000200 */
#define TIM_SR_CC1OF                             TIM_SR_CC1OF_MASK                                  /**< Capture 1 overcapture flag           */
#define TIM_SR_CC2OF_POS                         (10U)
#define TIM_SR_CC2OF_MASK                        (0x1UL << TIM_SR_CC2OF_POS)                        /**< 0x00000400 */
#define TIM_SR_CC2OF                             TIM_SR_CC2OF_MASK                                  /**< Capture 2 overcapture flag           */
#define TIM_SR_CC3OF_POS                         (11U)
#define TIM_SR_CC3OF_MASK                        (0x1UL << TIM_SR_CC3OF_POS)                        /**< 0x00000800 */
#define TIM_SR_CC3OF                             TIM_SR_CC3OF_MASK                                  /**< Capture 3 overcapture flag           */
#define TIM_SR_CC4OF_POS                         (12U)
#define TIM_SR_CC4OF_MASK                        (0x1UL << TIM_SR_CC4OF_POS)                        /**< 0x00001000 */
#define TIM_SR_CC4OF                             TIM_SR_CC4OF_MASK                                  /**< Capture 4 overcapture flag           */

/* Bits for TIM_EVTG */
#define TIM_EVTG_UG_POS                          (0U)
#define TIM_EVTG_UG_MASK                         (0x1UL << TIM_EVTG_UG_POS)                         /**< 0x00000001 */
#define TIM_EVTG_UG                              TIM_EVTG_UG_MASK                                   /**< Update generation                         */
#define TIM_EVTG_CC1G_POS                        (1U)
#define TIM_EVTG_CC1G_MASK                       (0x1UL << TIM_EVTG_CC1G_POS)                       /**< 0x00000002 */
#define TIM_EVTG_CC1G                            TIM_EVTG_CC1G_MASK                                 /**< Capture/compare 1 generation              */
#define TIM_EVTG_CC2G_POS                        (2U)
#define TIM_EVTG_CC2G_MASK                       (0x1UL << TIM_EVTG_CC2G_POS)                       /**< 0x00000004 */
#define TIM_EVTG_CC2G                            TIM_EVTG_CC2G_MASK                                 /**< Capture/compare 2 generation              */
#define TIM_EVTG_CC3G_POS                        (3U)
#define TIM_EVTG_CC3G_MASK                       (0x1UL << TIM_EVTG_CC3G_POS)                       /**< 0x00000008 */
#define TIM_EVTG_CC3G                            TIM_EVTG_CC3G_MASK                                 /**< Capture/Compare 3 generation              */
#define TIM_EVTG_CC4G_POS                        (4U)
#define TIM_EVTG_CC4G_MASK                       (0x1UL << TIM_EVTG_CC4G_POS)                       /**< 0x00000010 */
#define TIM_EVTG_CC4G                            TIM_EVTG_CC4G_MASK                                 /**< Capture/Compare 4 generation              */
#define TIM_EVTG_COMG_POS                        (5U)
#define TIM_EVTG_COMG_MASK                       (0x1UL << TIM_EVTG_COMG_POS)                       /**< 0x00000020 */
#define TIM_EVTG_COMG                            TIM_EVTG_COMG_MASK                                 /**< Capture/compare control update generation */
#define TIM_EVTG_TG_POS                          (6U)
#define TIM_EVTG_TG_MASK                         (0x1UL << TIM_EVTG_TG_POS)                         /**< 0x00000040 */
#define TIM_EVTG_TG                              TIM_EVTG_TG_MASK                                   /**< Trigger generation                        */
#define TIM_EVTG_BG_POS                          (7U)
#define TIM_EVTG_BG_MASK                         (0x1UL << TIM_EVTG_BG_POS)                         /**< 0x00000080 */
#define TIM_EVTG_BG                              TIM_EVTG_BG_MASK                                   /**< Break generation                          */

/* Bits for TIM_CCM1 (output) */
#define TIM_CCM1_CC1S_POS                        (0U)
#define TIM_CCM1_CC1S_MASK                       (0x3UL << TIM_CCM1_CC1S_POS)                       /**< 0x00000003 */
#define TIM_CCM1_CC1S                            TIM_CCM1_CC1S_MASK                                 /**< Capture/compare 1 selection     */
#define TIM_CCM1_CC1S_DIRECTTI                   (0x1UL << TIM_CCM1_CC1S_POS)                       /**< 0x00000001 */
#define TIM_CCM1_CC1S_INDIRECTTI                 (0x2UL << TIM_CCM1_CC1S_POS)                       /**< 0x00000002 */
#define TIM_CCM1_CC1S_TRC                        (0x3UL << TIM_CCM1_CC1S_POS)                       /**< 0x00000003 */

#define TIM_CCM1_OC1FE_POS                       (2U)
#define TIM_CCM1_OC1FE_MASK                      (0x1UL << TIM_CCM1_OC1FE_POS)                      /**< 0x00000004 */
#define TIM_CCM1_OC1FE                           TIM_CCM1_OC1FE_MASK                                /**< Output compare 1 fast enable    */
#define TIM_CCM1_OC1PE_POS                       (3U)
#define TIM_CCM1_OC1PE_MASK                      (0x1UL << TIM_CCM1_OC1PE_POS)                      /**< 0x00000008 */
#define TIM_CCM1_OC1PE                           TIM_CCM1_OC1PE_MASK                                /**< Output compare 1 preload enable */

#define TIM_CCM1_OC1M_POS                        (4U)
#define TIM_CCM1_OC1M_MASK                       (0x7UL << TIM_CCM1_OC1M_POS)                       /**< 0x00000070 */
#define TIM_CCM1_OC1M                            TIM_CCM1_OC1M_MASK                                 /**< Output compare 1 mode           */
#define TIM_CCM1_OC1M_FROZEN                     (0x00UL << TIM_CCM1_OC1M_POS)                      /**< 0x00000000 */ 
#define TIM_CCM1_OC1M_ACTIVE                     (0x01UL << TIM_CCM1_OC1M_POS)                      /**< 0x00000010 */ 
#define TIM_CCM1_OC1M_INACTIVE                   (0x02UL << TIM_CCM1_OC1M_POS)                      /**< 0x00000020 */ 
#define TIM_CCM1_OC1M_TOGGLE                     (0x03UL << TIM_CCM1_OC1M_POS)                      /**< 0x00000030 */ 
#define TIM_CCM1_OC1M_FORCED_INACTIVE            (0x04UL << TIM_CCM1_OC1M_POS)                      /**< 0x00000040 */ 
#define TIM_CCM1_OC1M_FORCED_ACTIVE              (0x05UL << TIM_CCM1_OC1M_POS)                      /**< 0x00000050 */ 
#define TIM_CCM1_OC1M_PWM1                       (0x06UL << TIM_CCM1_OC1M_POS)                      /**< 0x00000060 */ 
#define TIM_CCM1_OC1M_PWM2                       (0x07UL << TIM_CCM1_OC1M_POS)                      /**< 0x00000070 */ 

#define TIM_CCM1_OC1CE_POS                       (7U)
#define TIM_CCM1_OC1CE_MASK                      (0x1UL << TIM_CCM1_OC1CE_POS)                      /**< 0x00000080 */
#define TIM_CCM1_OC1CE                           TIM_CCM1_OC1CE_MASK                                /**< Output compare 1 clear enable   */

#define TIM_CCM1_CC2S_POS                        (8U)
#define TIM_CCM1_CC2S_MASK                       (0x3UL << TIM_CCM1_CC2S_POS)                       /**< 0x00000300 */
#define TIM_CCM1_CC2S                            TIM_CCM1_CC2S_MASK                                 /**< Capture/compare 2 selection     */
#define TIM_CCM1_CC2S_DIRECTTI                   (0x1UL << TIM_CCM1_CC2S_POS)                       /**< 0x00000100 */
#define TIM_CCM1_CC2S_INDIRECTTI                 (0x2UL << TIM_CCM1_CC2S_POS)                       /**< 0x00000200 */
#define TIM_CCM1_CC2S_TRC                        (0x3UL << TIM_CCM1_CC2S_POS)                       /**< 0x00000300 */

#define TIM_CCM1_OC2FE_POS                       (10U)
#define TIM_CCM1_OC2FE_MASK                      (0x1UL << TIM_CCM1_OC2FE_POS)                      /**< 0x00000400 */
#define TIM_CCM1_OC2FE                           TIM_CCM1_OC2FE_MASK                                /**< Output compare 2 fast enable    */
#define TIM_CCM1_OC2PE_POS                       (11U)
#define TIM_CCM1_OC2PE_MASK                      (0x1UL << TIM_CCM1_OC2PE_POS)                      /**< 0x00000800 */
#define TIM_CCM1_OC2PE                           TIM_CCM1_OC2PE_MASK                                /**< Output compare 2 preload enable */

#define TIM_CCM1_OC2M_POS                        (12U)
#define TIM_CCM1_OC2M_MASK                       (0x7UL << TIM_CCM1_OC2M_POS)                       /**< 0x00007000 */
#define TIM_CCM1_OC2M                            TIM_CCM1_OC2M_MASK                                 /**< Output compare 2 mode           */
#define TIM_CCM1_OC2M_FROZEN                     (0x00UL << TIM_CCM1_OC2M_POS)                      /**< 0x00000000 */ 
#define TIM_CCM1_OC2M_ACTIVE                     (0x01UL << TIM_CCM1_OC2M_POS)                      /**< 0x00001000 */ 
#define TIM_CCM1_OC2M_INACTIVE                   (0x02UL << TIM_CCM1_OC2M_POS)                      /**< 0x00002000 */ 
#define TIM_CCM1_OC2M_TOGGLE                     (0x03UL << TIM_CCM1_OC2M_POS)                      /**< 0x00003000 */ 
#define TIM_CCM1_OC2M_FORCED_INACTIVE            (0x04UL << TIM_CCM1_OC2M_POS)                      /**< 0x00004000 */ 
#define TIM_CCM1_OC2M_FORCED_ACTIVE              (0x05UL << TIM_CCM1_OC2M_POS)                      /**< 0x00005000 */ 
#define TIM_CCM1_OC2M_PWM1                       (0x06UL << TIM_CCM1_OC2M_POS)                      /**< 0x00006000 */ 
#define TIM_CCM1_OC2M_PWM2                       (0x07UL << TIM_CCM1_OC2M_POS)                      /**< 0x00007000 */ 
                                     
#define TIM_CCM1_OC2CE_POS                       (15U)
#define TIM_CCM1_OC2CE_MASK                      (0x1UL << TIM_CCM1_OC2CE_POS)                      /**< 0x00008000 */
#define TIM_CCM1_OC2CE                           TIM_CCM1_OC2CE_MASK                                /**<  Output compare 2 clear enable  */

/* Bits for TIM_CCM1 (input) */
#define TIM_CCM1_IC1PSC_POS                      (2U)
#define TIM_CCM1_IC1PSC_MASK                     (0x3UL << TIM_CCM1_IC1PSC_POS)                     /**< 0x0000000C */
#define TIM_CCM1_IC1PSC                          TIM_CCM1_IC1PSC_MASK                               /**< Input capture 1 prescaler       */
#define TIM_CCM1_IC1PSC_DIV1                     (0x0UL << TIM_CCM1_IC1PSC_POS)                     /**< 0x00000000 */
#define TIM_CCM1_IC1PSC_DIV2                     (0x1UL << TIM_CCM1_IC1PSC_POS)                     /**< 0x00000004 */
#define TIM_CCM1_IC1PSC_DIV4                     (0x2UL << TIM_CCM1_IC1PSC_POS)                     /**< 0x00000008 */
#define TIM_CCM1_IC1PSC_DIV8                     (0x3UL << TIM_CCM1_IC1PSC_POS)                     /**< 0x0000000C */

#define TIM_CCM1_IC1F_POS                        (4U)
#define TIM_CCM1_IC1F_MASK                       (0x7UL << TIM_CCM1_IC1F_POS)                       /**< 0x00000070 */
#define TIM_CCM1_IC1F                            TIM_CCM1_IC1F_MASK                                 /**< Input capture 1 filter          */
#define TIM_CCM1_IC1F_FILT_DIV1                  (0x01UL << TIM_CCM1_IC1F_POS)                      /**< 0x00000010 */
#define TIM_CCM1_IC1F_FILT_DIV2                  (0x02UL << TIM_CCM1_IC1F_POS)                      /**< 0x00000020 */
#define TIM_CCM1_IC1F_FILT_DIV4                  (0x03UL << TIM_CCM1_IC1F_POS)                      /**< 0x00000030 */
#define TIM_CCM1_IC1F_FILT_DIV8                  (0x04UL << TIM_CCM1_IC1F_POS)                      /**< 0x00000040 */
#define TIM_CCM1_IC1F_FILT_DIV16                 (0x05UL << TIM_CCM1_IC1F_POS)                      /**< 0x00000050 */
#define TIM_CCM1_IC1F_FILT_DIV32                 (0x06UL << TIM_CCM1_IC1F_POS)                      /**< 0x00000060 */

#define TIM_CCM1_IC2PSC_POS                      (10U)
#define TIM_CCM1_IC2PSC_MASK                     (0x3UL << TIM_CCM1_IC2PSC_POS)                     /**< 0x00000C00 */
#define TIM_CCM1_IC2PSC                          TIM_CCM1_IC2PSC_MASK                               /**< Input capture 2 prescaler       */
#define TIM_CCM1_IC2PSC_DIV1                     (0x0UL << TIM_CCM1_IC2PSC_POS)                     /**< 0x00000000 */
#define TIM_CCM1_IC2PSC_DIV2                     (0x1UL << TIM_CCM1_IC2PSC_POS)                     /**< 0x00000400 */
#define TIM_CCM1_IC2PSC_DIV4                     (0x2UL << TIM_CCM1_IC2PSC_POS)                     /**< 0x00000800 */
#define TIM_CCM1_IC2PSC_DIV8                     (0x3UL << TIM_CCM1_IC2PSC_POS)                     /**< 0x00000C00 */

#define TIM_CCM1_IC2F_POS                        (12U)
#define TIM_CCM1_IC2F_MASK                       (0x7UL << TIM_CCM1_IC2F_POS)                       /**< 0x00007000 */
#define TIM_CCM1_IC2F                            TIM_CCM1_IC2F_MASK                                 /**< Input capture 2 filter          */
#define TIM_CCM1_IC2F_FILT_DIV1                  (0x01UL << TIM_CCM1_IC2F_POS)                      /**< 0x00001000 */
#define TIM_CCM1_IC2F_FILT_DIV2                  (0x02UL << TIM_CCM1_IC2F_POS)                      /**< 0x00002000 */
#define TIM_CCM1_IC2F_FILT_DIV4                  (0x03UL << TIM_CCM1_IC2F_POS)                      /**< 0x00003000 */
#define TIM_CCM1_IC2F_FILT_DIV8                  (0x04UL << TIM_CCM1_IC2F_POS)                      /**< 0x00004000 */
#define TIM_CCM1_IC2F_FILT_DIV16                 (0x05UL << TIM_CCM1_IC2F_POS)                      /**< 0x00005000 */
#define TIM_CCM1_IC2F_FILT_DIV32                 (0x06UL << TIM_CCM1_IC2F_POS)                      /**< 0x00006000 */

/* Bits for TIM_CCM2 (output) */
#define TIM_CCM2_CC3S_POS                        (0U)
#define TIM_CCM2_CC3S_MASK                       (0x3UL << TIM_CCM2_CC3S_POS)                       /**< 0x00000003 */
#define TIM_CCM2_CC3S                            TIM_CCM2_CC3S_MASK                                 /**< Capture/compare 3 selection     */
#define TIM_CCM2_CC3S_DIRECTTI                   (0x1UL << TIM_CCM2_CC3S_POS)                       /**< 0x00000001 */
#define TIM_CCM2_CC3S_INDIRECTTI                 (0x2UL << TIM_CCM2_CC3S_POS)                       /**< 0x00000002 */
#define TIM_CCM2_CC3S_TRC                        (0x3UL << TIM_CCM2_CC3S_POS)                       /**< 0x00000003 */

#define TIM_CCM2_OC3FE_POS                       (2U)
#define TIM_CCM2_OC3FE_MASK                      (0x1UL << TIM_CCM2_OC3FE_POS)                      /**< 0x00000004 */
#define TIM_CCM2_OC3FE                           TIM_CCM2_OC3FE_MASK                                /**< Output compare 3 fast enable    */
#define TIM_CCM2_OC3PE_POS                       (3U)
#define TIM_CCM2_OC3PE_MASK                      (0x1UL << TIM_CCM2_OC3PE_POS)                      /**< 0x00000008 */
#define TIM_CCM2_OC3PE                           TIM_CCM2_OC3PE_MASK                                /**< Output compare 3 preload enable */

#define TIM_CCM2_OC3M_POS                        (4U)
#define TIM_CCM2_OC3M_MASK                       (0x7UL << TIM_CCM2_OC3M_POS)                       /**< 0x00000070 */
#define TIM_CCM2_OC3M                            TIM_CCM2_OC3M_MASK                                 /**< Output compare 3 mode           */
#define TIM_CCM2_OC3M_FROZEN                     (0x00UL << TIM_CCM2_OC3M_POS)                      /**< 0x00000000 */ 
#define TIM_CCM2_OC3M_ACTIVE                     (0x01UL << TIM_CCM2_OC3M_POS)                      /**< 0x00000010 */ 
#define TIM_CCM2_OC3M_INACTIVE                   (0x02UL << TIM_CCM2_OC3M_POS)                      /**< 0x00000020 */ 
#define TIM_CCM2_OC3M_TOGGLE                     (0x03UL << TIM_CCM2_OC3M_POS)                      /**< 0x00000030 */ 
#define TIM_CCM2_OC3M_FORCED_INACTIVE            (0x04UL << TIM_CCM2_OC3M_POS)                      /**< 0x00000040 */ 
#define TIM_CCM2_OC3M_FORCED_ACTIVE              (0x05UL << TIM_CCM2_OC3M_POS)                      /**< 0x00000050 */ 
#define TIM_CCM2_OC3M_PWM1                       (0x06UL << TIM_CCM2_OC3M_POS)                      /**< 0x00000060 */ 
#define TIM_CCM2_OC3M_PWM2                       (0x07UL << TIM_CCM2_OC3M_POS)                      /**< 0x00000070 */ 

#define TIM_CCM2_OC3CE_POS                       (7U)
#define TIM_CCM2_OC3CE_MASK                      (0x1UL << TIM_CCM2_OC3CE_POS)                      /**< 0x00000080 */
#define TIM_CCM2_OC3CE                           TIM_CCM2_OC3CE_MASK                                /**< Output compare 3 clear enable   */

#define TIM_CCM2_CC4S_POS                        (8U)
#define TIM_CCM2_CC4S_MASK                       (0x3UL << TIM_CCM2_CC4S_POS)                       /**< 0x00000300 */
#define TIM_CCM2_CC4S                            TIM_CCM2_CC4S_MASK                                 /**< Capture/Compare 4 selection     */
#define TIM_CCM2_CC4S_DIRECTTI                   (0x1UL << TIM_CCM2_CC4S_POS)                       /**< 0x00000100 */
#define TIM_CCM2_CC4S_INDIRECTTI                 (0x2UL << TIM_CCM2_CC4S_POS)                       /**< 0x00000200 */
#define TIM_CCM2_CC4S_TRC                        (0x3UL << TIM_CCM2_CC4S_POS)                       /**< 0x00000300 */

#define TIM_CCM2_OC4FE_POS                       (10U)
#define TIM_CCM2_OC4FE_MASK                      (0x1UL << TIM_CCM2_OC4FE_POS)                      /**< 0x00000400 */
#define TIM_CCM2_OC4FE                           TIM_CCM2_OC4FE_MASK                                /**< Output compare 4 fast enable    */
#define TIM_CCM2_OC4PE_POS                       (11U)
#define TIM_CCM2_OC4PE_MASK                      (0x1UL << TIM_CCM2_OC4PE_POS)                      /**< 0x00000800 */
#define TIM_CCM2_OC4PE                           TIM_CCM2_OC4PE_MASK                                /**< Output compare 4 preload enable */

#define TIM_CCM2_OC4M_POS                        (12U)
#define TIM_CCM2_OC4M_MASK                       (0x7UL << TIM_CCM2_OC4M_POS)                       /**< 0x00007000 */
#define TIM_CCM2_OC4M                            TIM_CCM2_OC4M_MASK                                 /**< Output compare 4 mode           */
#define TIM_CCM2_OC4M_FROZEN                     (0x00UL << TIM_CCM2_OC4M_POS)                      /**< 0x00000000 */ 
#define TIM_CCM2_OC4M_ACTIVE                     (0x01UL << TIM_CCM2_OC4M_POS)                      /**< 0x00001000 */ 
#define TIM_CCM2_OC4M_INACTIVE                   (0x02UL << TIM_CCM2_OC4M_POS)                      /**< 0x00002000 */ 
#define TIM_CCM2_OC4M_TOGGLE                     (0x03UL << TIM_CCM2_OC4M_POS)                      /**< 0x00003000 */ 
#define TIM_CCM2_OC4M_FORCED_INACTIVE            (0x04UL << TIM_CCM2_OC4M_POS)                      /**< 0x00004000 */ 
#define TIM_CCM2_OC4M_FORCED_ACTIVE              (0x05UL << TIM_CCM2_OC4M_POS)                      /**< 0x00005000 */ 
#define TIM_CCM2_OC4M_PWM1                       (0x06UL << TIM_CCM2_OC4M_POS)                      /**< 0x00006000 */ 
#define TIM_CCM2_OC4M_PWM2                       (0x07UL << TIM_CCM2_OC4M_POS)                      /**< 0x00007000 */ 

#define TIM_CCM2_OC4CE_POS                       (15U)
#define TIM_CCM2_OC4CE_MASK                      (0x1UL << TIM_CCM2_OC4CE_POS)                      /**< 0x00008000 */
#define TIM_CCM2_OC4CE                           TIM_CCM2_OC4CE_MASK                                /**< Output compare 4 clear enable   */

/* Bits for TIM_CCM2 (input) */
#define TIM_CCM2_IC3PSC_POS                      (2U)
#define TIM_CCM2_IC3PSC_MASK                     (0x3UL << TIM_CCM2_IC3PSC_POS)                     /**< 0x0000000C */
#define TIM_CCM2_IC3PSC                          TIM_CCM2_IC3PSC_MASK                               /**< Input capture 3 prescaler       */
#define TIM_CCM2_IC3PSC_DIV1                     (0x0UL << TIM_CCM2_IC3PSC_POS)                     /**< 0x00000000 */   
#define TIM_CCM2_IC3PSC_DIV2                     (0x1UL << TIM_CCM2_IC3PSC_POS)                     /**< 0x00000004 */   
#define TIM_CCM2_IC3PSC_DIV4                     (0x2UL << TIM_CCM2_IC3PSC_POS)                     /**< 0x00000008 */   
#define TIM_CCM2_IC3PSC_DIV8                     (0x3UL << TIM_CCM2_IC3PSC_POS)                     /**< 0x0000000C */   

#define TIM_CCM2_IC3F_POS                        (4U)
#define TIM_CCM2_IC3F_MASK                       (0x7UL << TIM_CCM2_IC3F_POS)                       /**< 0x00000070 */
#define TIM_CCM2_IC3F                            TIM_CCM2_IC3F_MASK                                 /**< Input capture 3 filter          */
#define TIM_CCM2_IC3F_FILT_DIV1                  (0x01UL << TIM_CCM2_IC3F_POS)                      /**< 0x00000010 */
#define TIM_CCM2_IC3F_FILT_DIV2                  (0x02UL << TIM_CCM2_IC3F_POS)                      /**< 0x00000020 */
#define TIM_CCM2_IC3F_FILT_DIV4                  (0x03UL << TIM_CCM2_IC3F_POS)                      /**< 0x00000030 */
#define TIM_CCM2_IC3F_FILT_DIV8                  (0x04UL << TIM_CCM2_IC3F_POS)                      /**< 0x00000040 */
#define TIM_CCM2_IC3F_FILT_DIV16                 (0x05UL << TIM_CCM2_IC3F_POS)                      /**< 0x00000050 */
#define TIM_CCM2_IC3F_FILT_DIV32                 (0x06UL << TIM_CCM2_IC3F_POS)                      /**< 0x00000060 */

#define TIM_CCM2_IC4PSC_POS                      (10U)
#define TIM_CCM2_IC4PSC_MASK                     (0x3UL << TIM_CCM2_IC4PSC_POS)                     /**< 0x00000C00 */
#define TIM_CCM2_IC4PSC                          TIM_CCM2_IC4PSC_MASK                               /**< Input capture 4 prescaler       */
#define TIM_CCM2_IC4PSC_DIV1                     (0x0UL << TIM_CCM2_IC4PSC_POS)                     /**< 0x00000000 */   
#define TIM_CCM2_IC4PSC_DIV2                     (0x1UL << TIM_CCM2_IC4PSC_POS)                     /**< 0x00000400 */   
#define TIM_CCM2_IC4PSC_DIV4                     (0x2UL << TIM_CCM2_IC4PSC_POS)                     /**< 0x00000800 */   
#define TIM_CCM2_IC4PSC_DIV8                     (0x3UL << TIM_CCM2_IC4PSC_POS)                     /**< 0x00000C00 */  

#define TIM_CCM2_IC4F_POS                        (12U)
#define TIM_CCM2_IC4F_MASK                       (0x7UL << TIM_CCM2_IC4F_POS)                       /**< 0x00007000 */
#define TIM_CCM2_IC4F                            TIM_CCM2_IC4F_MASK                                 /**< Input capture 4 filter          */
#define TIM_CCM2_IC4F_FILT_DIV1                  (0x01UL << TIM_CCM2_IC4F_POS)                      /**< 0x00001000 */
#define TIM_CCM2_IC4F_FILT_DIV2                  (0x02UL << TIM_CCM2_IC4F_POS)                      /**< 0x00002000 */
#define TIM_CCM2_IC4F_FILT_DIV4                  (0x03UL << TIM_CCM2_IC4F_POS)                      /**< 0x00003000 */
#define TIM_CCM2_IC4F_FILT_DIV8                  (0x04UL << TIM_CCM2_IC4F_POS)                      /**< 0x00004000 */
#define TIM_CCM2_IC4F_FILT_DIV16                 (0x05UL << TIM_CCM2_IC4F_POS)                      /**< 0x00005000 */
#define TIM_CCM2_IC4F_FILT_DIV32                 (0x06UL << TIM_CCM2_IC4F_POS)                      /**< 0x00006000 */

/* Bits for TIM_CCEN */
#define TIM_CCEN_CC1E_POS                        (0U)
#define TIM_CCEN_CC1E_MASK                       (0x1UL << TIM_CCEN_CC1E_POS)                       /**< 0x00000001 */
#define TIM_CCEN_CC1E                            TIM_CCEN_CC1E_MASK                                 /**< Capture/Compare 1 output enable                 */
#define TIM_CCEN_CC1P_POS                        (1U)
#define TIM_CCEN_CC1P_MASK                       (0x1UL << TIM_CCEN_CC1P_POS)                       /**< 0x00000002 */
#define TIM_CCEN_CC1P                            TIM_CCEN_CC1P_MASK                                 /**< Capture/Compare 1 output polarity               */
#define TIM_CCEN_CC1NE_POS                       (2U)
#define TIM_CCEN_CC1NE_MASK                      (0x1UL << TIM_CCEN_CC1NE_POS)                      /**< 0x00000004 */
#define TIM_CCEN_CC1NE                           TIM_CCEN_CC1NE_MASK                                /**< Capture/Compare 1 complementary output enable   */
#define TIM_CCEN_CC1NP_POS                       (3U)
#define TIM_CCEN_CC1NP_MASK                      (0x1UL << TIM_CCEN_CC1NP_POS)                      /**< 0x00000008 */
#define TIM_CCEN_CC1NP                           TIM_CCEN_CC1NP_MASK                                /**< Capture/Compare 1 complementary output polarity */

#define TIM_CCEN_CC2E_POS                        (4U)
#define TIM_CCEN_CC2E_MASK                       (0x1UL << TIM_CCEN_CC2E_POS)                       /**< 0x00000010 */
#define TIM_CCEN_CC2E                            TIM_CCEN_CC2E_MASK                                 /**< Capture/Compare 2 output enable                 */
#define TIM_CCEN_CC2P_POS                        (5U)
#define TIM_CCEN_CC2P_MASK                       (0x1UL << TIM_CCEN_CC2P_POS)                       /**< 0x00000020 */
#define TIM_CCEN_CC2P                            TIM_CCEN_CC2P_MASK                                 /**< Capture/Compare 2 output Polarity               */
#define TIM_CCEN_CC2NE_POS                       (6U)
#define TIM_CCEN_CC2NE_MASK                      (0x1UL << TIM_CCEN_CC2NE_POS)                      /**< 0x00000040 */
#define TIM_CCEN_CC2NE                           TIM_CCEN_CC2NE_MASK                                /**< Capture/Compare 2 complementary output enable   */
#define TIM_CCEN_CC2NP_POS                       (7U)
#define TIM_CCEN_CC2NP_MASK                      (0x1UL << TIM_CCEN_CC2NP_POS)                      /**< 0x00000080 */
#define TIM_CCEN_CC2NP                           TIM_CCEN_CC2NP_MASK                                /**< Capture/Compare 2 complementary output polarity */

#define TIM_CCEN_CC3E_POS                        (8U)
#define TIM_CCEN_CC3E_MASK                       (0x1UL << TIM_CCEN_CC3E_POS)                       /**< 0x00000100 */
#define TIM_CCEN_CC3E                            TIM_CCEN_CC3E_MASK                                 /**< Capture/Compare 3 output enable                 */
#define TIM_CCEN_CC3P_POS                        (9U)
#define TIM_CCEN_CC3P_MASK                       (0x1UL << TIM_CCEN_CC3P_POS)                       /**< 0x00000200 */
#define TIM_CCEN_CC3P                            TIM_CCEN_CC3P_MASK                                 /**< Capture/Compare 3 output Polarity               */
#define TIM_CCEN_CC3NE_POS                       (10U)
#define TIM_CCEN_CC3NE_MASK                      (0x1UL << TIM_CCEN_CC3NE_POS)                      /**< 0x00000400 */
#define TIM_CCEN_CC3NE                           TIM_CCEN_CC3NE_MASK                                /**< Capture/Compare 3 complementary output enable   */
#define TIM_CCEN_CC3NP_POS                       (11U)
#define TIM_CCEN_CC3NP_MASK                      (0x1UL << TIM_CCEN_CC3NP_POS)                      /**< 0x00000800 */
#define TIM_CCEN_CC3NP                           TIM_CCEN_CC3NP_MASK                                /**< Capture/Compare 3 complementary output polarity */

#define TIM_CCEN_CC4E_POS                        (12U)
#define TIM_CCEN_CC4E_MASK                       (0x1UL << TIM_CCEN_CC4E_POS)                       /**< 0x00001000 */
#define TIM_CCEN_CC4E                            TIM_CCEN_CC4E_MASK                                 /**< Capture/Compare 4 output enable                 */
#define TIM_CCEN_CC4P_POS                        (13U)
#define TIM_CCEN_CC4P_MASK                       (0x1UL << TIM_CCEN_CC4P_POS)                       /**< 0x00002000 */
#define TIM_CCEN_CC4P                            TIM_CCEN_CC4P_MASK                                 /**< Capture/Compare 4 output Polarity               */
#define TIM_CCEN_CC4NP_POS                       (15U)
#define TIM_CCEN_CC4NP_MASK                      (0x1UL << TIM_CCEN_CC4NP_POS)                      /**< 0x00008000 */
#define TIM_CCEN_CC4NP                           TIM_CCEN_CC4NP_MASK                                /**< Capture/Compare 4 complementary output polarity */

/* Bits for TIM_CNT */
#define TIM_CNT_CNT_POS                          (0U)
#define TIM_CNT_CNT_MASK                         (0xFFFFUL << TIM_CNT_CNT_POS)                      /**< 0x0000FFFF */
#define TIM_CNT_CNT                              TIM_CNT_CNT_MASK                                   /**< Counter value               */

/* Bits for TIM_PSC */
#define TIM_PSC_PSC_POS                          (0U)
#define TIM_PSC_PSC_MASK                         (0xFUL << TIM_PSC_PSC_POS)                         /**< 0x0000000F */
#define TIM_PSC_PSC                              TIM_PSC_PSC_MASK                                   /**< Prescaler value             */

/* Bits for TIM_ARR */
#define TIM_ARR_ARR_POS                          (0U)
#define TIM_ARR_ARR_MASK                         (0xFFFFUL << TIM_ARR_ARR_POS)                      /**< 0x0000FFFF */
#define TIM_ARR_ARR                              TIM_ARR_ARR_MASK                                   /**< Auto-reload value           */

/* Bits for TIM_RCR */
#define TIM_RCR_REP_POS                          (0U)
#define TIM_RCR_REP_MASK                         (0xFFUL << TIM_RCR_REP_POS)                        /**< 0x000000FF */
#define TIM_RCR_REP                              TIM_RCR_REP_MASK                                   /**< Repetition counter value    */

/* Bits for TIM_CC1 */
#define TIM_CC1_CC1_POS                          (0U)
#define TIM_CC1_CC1_MASK                         (0xFFFFUL << TIM_CC1_CC1_POS)                      /**< 0x0000FFFF */
#define TIM_CC1_CC1                              TIM_CC1_CC1_MASK                                   /**< Capture/Compare 1 value     */

/* Bits for TIM_CC2 */
#define TIM_CC2_CC2_POS                          (0U)
#define TIM_CC2_CC2_MASK                         (0xFFFFUL << TIM_CC2_CC2_POS)                      /**< 0x0000FFFF */
#define TIM_CC2_CC2                              TIM_CC2_CC2_MASK                                   /**< Capture/Compare 2 value     */

/* Bits for TIM_CC3 */
#define TIM_CC3_CC3_POS                          (0U)
#define TIM_CC3_CC3_MASK                         (0xFFFFUL << TIM_CC3_CC3_POS)                      /**< 0x0000FFFF */
#define TIM_CC3_CC3                              TIM_CC3_CC3_MASK                                   /**< Capture/Compare 3 value     */

/* Bits for TIM_CC4 */
#define TIM_CC4_CC4_POS                          (0U)
#define TIM_CC4_CC4_MASK                         (0xFFFFUL << TIM_CC4_CC4_POS)                      /**< 0x0000FFFF */
#define TIM_CC4_CC4                              TIM_CC4_CC4_MASK                                   /**< Capture/Compare 4 value     */

   
/* Bits for TIM_BDT */
#define TIM_BDT_DTG_POS                          (0U)
#define TIM_BDT_DTG_MASK                         (0xFFUL << TIM_BDT_DTG_POS)                        /**< 0x000000FF */
#define TIM_BDT_DTG                              TIM_BDT_DTG_MASK                                   /**< Dead-Time generator setup   */

#define TIM_BDT_LOCK_POS                         (8U)
#define TIM_BDT_LOCK_MASK                        (0x3UL << TIM_BDT_LOCK_POS)                        /**< 0x00000300 */
#define TIM_BDT_LOCK                             TIM_BDT_LOCK_MASK                                  /**< Lock configuration          */
#define TIM_BDT_LOCK_LEVEL1                      (0x1UL << TIM_BDT_LOCK_POS)                        /**< 0x00000100 */
#define TIM_BDT_LOCK_LEVEL2                      (0x2UL << TIM_BDT_LOCK_POS)                        /**< 0x00000200 */
#define TIM_BDT_LOCK_LEVEL3                      (0x3UL << TIM_BDT_LOCK_POS)                        /**< 0x00000300 */

#define TIM_BDT_OSSI_POS                         (10U)
#define TIM_BDT_OSSI_MASK                        (0x1UL << TIM_BDT_OSSI_POS)                        /**< 0x00000400 */
#define TIM_BDT_OSSI                             TIM_BDT_OSSI_MASK                                  /**< Off-State selection for Idle mode */
#define TIM_BDT_OSSR_POS                         (11U)
#define TIM_BDT_OSSR_MASK                        (0x1UL << TIM_BDT_OSSR_POS)                        /**< 0x00000800 */
#define TIM_BDT_OSSR                             TIM_BDT_OSSR_MASK                                  /**< Off-State selection for Run mode  */
#define TIM_BDT_BKEN_POS                         (12U)
#define TIM_BDT_BKEN_MASK                        (0x1UL << TIM_BDT_BKEN_POS)                        /**< 0x00001000 */
#define TIM_BDT_BKEN                             TIM_BDT_BKEN_MASK                                  /**< Break enable for break 1          */
#define TIM_BDT_AOEN_POS                         (14U)
#define TIM_BDT_AOEN_MASK                        (0x1UL << TIM_BDT_AOEN_POS)                        /**< 0x00004000 */
#define TIM_BDT_AOEN                             TIM_BDT_AOEN_MASK                                  /**< Automatic output enable           */
#define TIM_BDT_MOEN_POS                         (15U)
#define TIM_BDT_MOEN_MASK                        (0x1UL << TIM_BDT_MOEN_POS)                        /**< 0x00008000 */
#define TIM_BDT_MOEN                             TIM_BDT_MOEN_MASK                                  /**< Main output enable                */

/* Bits for TIM_CFG */
#define TIM_CFG_OCREF_CLR_POS                    (0U)
#define TIM_CFG_OCREF_CLR_MASK                   (0x1UL << TIM_CFG_OCREF_CLR_POS)                   /**< 0x00000001 */
#define TIM_CFG_OCREF_CLR                        TIM_CFG_OCREF_CLR_MASK                             /**< OCREF clear input selection       */

/* Bits for TIM1_AF1 */
#define TIM1_AF1_BKINE_POS                       (0U)
#define TIM1_AF1_BKINE_MASK                      (0x1UL << TIM1_AF1_BKINE_POS)                      /**< 0x00000001 */
#define TIM1_AF1_BKINE                           TIM1_AF1_BKINE_MASK                                /**< BRK BKIN input enable             */
#define TIM1_AF1_BKCMP1E_POS                     (1U)
#define TIM1_AF1_BKCMP1E_MASK                    (0x1UL << TIM1_AF1_BKCMP1E_POS)                    /**< 0x00000002 */
#define TIM1_AF1_BKCMP1E                         TIM1_AF1_BKCMP1E_MASK                              /**< BRK COMP1 enable                  */
#define TIM1_AF1_BKCMP2E_POS                     (2U)
#define TIM1_AF1_BKCMP2E_MASK                    (0x1UL << TIM1_AF1_BKCMP2E_POS)                    /**< 0x00000004 */
#define TIM1_AF1_BKCMP2E                         TIM1_AF1_BKCMP2E_MASK                              /**< BRK COMP2 enable                  */
#define TIM1_AF1_LOCKUP_LOCK_POS                 (7U)
#define TIM1_AF1_LOCKUP_LOCK_MASK                (0x1UL << TIM1_AF1_LOCKUP_LOCK_POS)                /**< 0x00000080 */
#define TIM1_AF1_LOCKUP_LOCK                     TIM1_AF1_LOCKUP_LOCK_MASK                          /**< LOCKUP LOCK enable                */
#define TIM1_AF1_PVD_LOCK_POS                    (8U)
#define TIM1_AF1_PVD_LOCK_MASK                   (0x1UL << TIM1_AF1_PVD_LOCK_POS)                   /**< 0x00000100 */
#define TIM1_AF1_PVD_LOCK                        TIM1_AF1_PVD_LOCK_MASK                             /**< PVD LOCK enable                   */
#define TIM1_AF1_BKINP_POS                       (9U)
#define TIM1_AF1_BKINP_MASK                      (0x1UL << TIM1_AF1_BKINP_POS)                      /**< 0x00000200 */
#define TIM1_AF1_BKINP                           TIM1_AF1_BKINP_MASK                                /**< BRK BKIN input polarity           */
#define TIM1_AF1_BKCMP1P_POS                     (10U)
#define TIM1_AF1_BKCMP1P_MASK                    (0x1UL << TIM1_AF1_BKCMP1P_POS)                    /**< 0x00000400 */
#define TIM1_AF1_BKCMP1P                         TIM1_AF1_BKCMP1P_MASK                              /**< BRK COMP1 input polarity          */
#define TIM1_AF1_BKCMP2P_POS                     (11U)
#define TIM1_AF1_BKCMP2P_MASK                    (0x1UL << TIM1_AF1_BKCMP2P_POS)                    /**< 0x00000800 */
#define TIM1_AF1_BKCMP2P                         TIM1_AF1_BKCMP2P_MASK                              /**< BRK COMP2 input polarity          */

/* Bits for TIM_AF1_ETR_SEL */
#define TIM_AF1_ETR_SEL_POS                      (14U)
#define TIM_AF1_ETR_SEL_MASK                     (0x7UL << TIM_AF1_ETR_SEL_POS)                     /**< 0x0001C000 */
#define TIM_AF1_ETR_SEL                          TIM_AF1_ETR_SEL_MASK                               /**< TIM ETR source selection          */

/* Bits for TIM3_ETR_SEL */ 
#define TIM3_AF1_ETR_SEL_GPIO                    (0x0UL << TIM_AF1_ETR_SEL_POS)                     /**< 0x00000000 */
#define TIM3_AF1_ETR_SEL_COMP1                   (0x1UL << TIM_AF1_ETR_SEL_POS)                     /**< 0x00004000 */
#define TIM3_AF1_ETR_SEL_COMP2                   (0x2UL << TIM_AF1_ETR_SEL_POS)                     /**< 0x00008000 */
#define TIM3_AF1_ETR_SEL_LXTAL                   (0x3UL << TIM_AF1_ETR_SEL_POS)                     /**< 0x0000C000 */
#define TIM3_AF1_ETR_SEL_MCO                     (0x5UL << TIM_AF1_ETR_SEL_POS)                     /**< 0x00014000 */
#define TIM3_AF1_ETR_SEL_RCL                     (0x6UL << TIM_AF1_ETR_SEL_POS)                     /**< 0x00018000 */

/* Bits for TIM_TISEL */
#define TIM_TISEL_TI1_SEL_POS                    (0U)
#define TIM_TISEL_TI1_SEL_MASK                   (0x1UL << TIM_TISEL_TI1_SEL_POS)                   /**< 0x00000001  */
#define TIM_TISEL_TI1_SEL                        TIM_TISEL_TI1_SEL_MASK                             /**< TIM TI1 SEL */

#define TIM_TISEL_TI2_SEL_POS                    (8U)
#define TIM_TISEL_TI2_SEL_MASK                   (0x1UL << TIM_TISEL_TI2_SEL_POS)                   /**< 0x00000100  */
#define TIM_TISEL_TI2_SEL                        TIM_TISEL_TI2_SEL_MASK                             /**< TIM TI2 SEL */

#define TIM_TISEL_TI4_SEL_POS                    (24U)
#define TIM_TISEL_TI4_SEL_MASK                   (0x3UL << TIM_TISEL_TI4_SEL_POS)                   /**< 0x03000000  */
#define TIM_TISEL_TI4_SEL                        TIM_TISEL_TI4_SEL_MASK                             /**< TIM TI4 SEL */

/* Bits for TIM3_TISEL */
#define TIM3_TISEL_TI1_SEL_CH1                   (0x0UL << TIM_TISEL_TI1_SEL_POS)                   /**< 0x00000000  */
#define TIM3_TISEL_TI1_SEL_COMP1                 (0x1UL << TIM_TISEL_TI1_SEL_POS)                   /**< 0x00000001  */ 

#define TIM3_TISEL_TI2_SEL_CH2                   (0x0UL << TIM_TISEL_TI2_SEL_POS)                   /**< 0x00000000  */
#define TIM3_TISEL_TI2_SEL_COMP2                 (0x1UL << TIM_TISEL_TI2_SEL_POS)                   /**< 0x00000100  */    

#define TIM3_TISEL_TI4_SEL_CH4                   (0x0UL << TIM_TISEL_TI4_SEL_POS)                   /**< 0x00000000  */
#define TIM3_TISEL_TI4_SEL_LXTAL                 (0x1UL << TIM_TISEL_TI4_SEL_POS)                   /**< 0x01000000  */
#define TIM3_TISEL_TI4_SEL_MCO                   (0x2UL << TIM_TISEL_TI4_SEL_POS)                   /**< 0x02000000  */
#define TIM3_TISEL_TI4_SEL_RCL                   (0x3UL << TIM_TISEL_TI4_SEL_POS)                   /**< 0x03000000  */

/*-----------------------------------------------------------------------------------------------
                                       UART  Registers Bits
------------------------------------------------------------------------------------------------*/
/* Bits for UART_CR1 */
#define UART_CR1_UE_POS                          (0U)
#define UART_CR1_UE_MASK                         (0x1UL << UART_CR1_UE_POS)                         /**< 0x00000001 */
#define UART_CR1_UE                              UART_CR1_UE_MASK                                   /**< UART enable                                */
#define UART_CR1_UEWK_POS                        (1U)
#define UART_CR1_UEWK_MASK                       (0x1UL << UART_CR1_UEWK_POS)                       /**< 0x00000002 */
#define UART_CR1_UEWK                            UART_CR1_UEWK_MASK                                 /**< LPUART enable in STOP mode                 */
#define UART_CR1_RE_POS                          (2U)
#define UART_CR1_RE_MASK                         (0x1UL << UART_CR1_RE_POS)                         /**< 0x00000004 */
#define UART_CR1_RE                              UART_CR1_RE_MASK                                   /**< Receiver enable                            */
#define UART_CR1_TE_POS                          (3U)
#define UART_CR1_TE_MASK                         (0x1UL << UART_CR1_TE_POS)                         /**< 0x00000008 */
#define UART_CR1_TE                              UART_CR1_TE_MASK                                   /**< Transmitter enable                         */
#define UART_CR1_RXNEIE_POS                      (5U)
#define UART_CR1_RXNEIE_MASK                     (0x1UL << UART_CR1_RXNEIE_POS)                     /**< 0x00000020 */
#define UART_CR1_RXNEIE                          UART_CR1_RXNEIE_MASK                               /**< RXNE not empty interrupt enable            */
#define UART_CR1_TCIE_POS                        (6U)
#define UART_CR1_TCIE_MASK                       (0x1UL << UART_CR1_TCIE_POS)                       /**< 0x00000040 */
#define UART_CR1_TCIE                            UART_CR1_TCIE_MASK                                 /**< Transmission Complete interrupt enable     */
#define UART_CR1_TXEIE_POS                       (7U)
#define UART_CR1_TXEIE_MASK                      (0x1UL << UART_CR1_TXEIE_POS)                      /**< 0x00000080 */
#define UART_CR1_TXEIE                           UART_CR1_TXEIE_MASK                                /**< TXE not full interrupt enable              */
#define UART_CR1_PEIE_POS                        (8U)
#define UART_CR1_PEIE_MASK                       (0x1UL << UART_CR1_PEIE_POS)                       /**< 0x00000100 */
#define UART_CR1_PEIE                            UART_CR1_PEIE_MASK                                 /**< PE interrupt enable                        */
#define UART_CR1_PTS_POS                         (9U)
#define UART_CR1_PTS_MASK                        (0x1UL << UART_CR1_PTS_POS)                        /**< 0x00000200 */
#define UART_CR1_PTS                             UART_CR1_PTS_MASK                                  /**< Parity selection                           */
#define UART_CR1_PEN_POS                         (10U)
#define UART_CR1_PEN_MASK                        (0x1UL << UART_CR1_PEN_POS)                        /**< 0x00000400 */
#define UART_CR1_PEN                             UART_CR1_PEN_MASK                                  /**< Parity control enable                      */
#define UART_CR1_WL_POS                          (12U)
#define UART_CR1_WL_MASK                         (0x1UL << UART_CR1_WL_POS)                         /**< 0x00001000 */
#define UART_CR1_WL                              UART_CR1_WL_MASK                                   /**< Word length                                */
#define UART_CR1_WL8BITS                         (0x0UL << UART_CR1_WL_POS)                         /**< 0x00000000 */
#define UART_CR1_WL9BITS                         UART_CR1_WL_MASK                                   /**< 0x00001000 */
#define UART_CR1_CMIE_POS                        (14U)
#define UART_CR1_CMIE_MASK                       (0x1UL << UART_CR1_CMIE_POS)                       /**< 0x00004000 */
#define UART_CR1_CMIE                            UART_CR1_CMIE_MASK                                 /**< Character match interrupt enable */

/* Bits for UART_CR2 */
#define UART_CR2_STOPBIT_POS                     (13U)
#define UART_CR2_STOPBIT_MASK                    (0x1UL << UART_CR2_STOPBIT_POS)                    /**< 0x00002000 */
#define UART_CR2_STOPBIT                         UART_CR2_STOPBIT_MASK                              /**< STOP bits */
#define UART_CR2_STOPBIT_1                       (0x0UL << UART_CR2_STOPBIT_POS)                    /**< 0x00000000 */
#define UART_CR2_STOPBIT_2                       (0x1UL << UART_CR2_STOPBIT_POS)                    /**< 0x00002000 */
#define UART_CR2_SWAP_POS                        (15U)
#define UART_CR2_SWAP_MASK                       (0x1UL << UART_CR2_SWAP_POS)                       /**< 0x00008000 */
#define UART_CR2_SWAP                            UART_CR2_SWAP_MASK                                 /**< SWAP TX/RX pins                            */
#define UART_CR2_RXIVC_POS                       (16U)
#define UART_CR2_RXIVC_MASK                      (0x1UL << UART_CR2_RXIVC_POS)                      /**< 0x00010000 */
#define UART_CR2_RXIVC                           UART_CR2_RXIVC_MASK                                /**< RX pin active level inversion              */
#define UART_CR2_TXIVC_POS                       (17U)
#define UART_CR2_TXIVC_MASK                      (0x1UL << UART_CR2_TXIVC_POS)                      /**< 0x00020000 */
#define UART_CR2_TXIVC                           UART_CR2_TXIVC_MASK                                /**< TX pin active level inversion              */
#define UART_CR2_DATAIVC_POS                     (18U)
#define UART_CR2_DATAIVC_MASK                    (0x1UL << UART_CR2_DATAIVC_POS)                    /**< 0x00040000 */
#define UART_CR2_DATAIVC                         UART_CR2_DATAIVC_MASK                              /**< Binary data inversion                      */
#define UART_CR2_MSBFIRST_POS                    (19U)
#define UART_CR2_MSBFIRST_MASK                   (0x1UL << UART_CR2_MSBFIRST_POS)                   /**< 0x00080000 */
#define UART_CR2_MSBFIRST                        UART_CR2_MSBFIRST_MASK                             /**< Most significant bit first                 */
#define UART_CR2_CMFD_POS                        (24U)
#define UART_CR2_CMFD_MASK                       (0xFFUL << UART_CR2_CMFD_POS)                      /**< 0xFF000000 */
#define UART_CR2_CMFD                            UART_CR2_CMFD_MASK                                 /**< Match Character of LPUART                  */

/* Bits for UART_CR3 */
#define UART_CR3_EIE_POS                         (0U)
#define UART_CR3_EIE_MASK                        (0x1UL << UART_CR3_EIE_POS)                        /**< 0x00000001 */
#define UART_CR3_EIE                             UART_CR3_EIE_MASK                                  /**< Error interrupt enable                     */
#define UART_CR3_HDEN_POS                        (3U)
#define UART_CR3_HDEN_MASK                       (0x1UL << UART_CR3_HDEN_POS)                       /**< 0x00000008 */
#define UART_CR3_HDEN                            UART_CR3_HDEN_MASK                                 /**< Half-Duplex selection                      */
#define UART_CR3_DMAR_POS                        (6U)
#define UART_CR3_DMAR_MASK                       (0x1UL << UART_CR3_DMAR_POS)                       /**< 0x00000040 */
#define UART_CR3_DMAR                            UART_CR3_DMAR_MASK                                 /**< DMA enable receiver                        */
#define UART_CR3_DMAT_POS                        (7U)
#define UART_CR3_DMAT_MASK                       (0x1UL << UART_CR3_DMAT_POS)                       /**< 0x00000080 */
#define UART_CR3_DMAT                            UART_CR3_DMAT_MASK                                 /**< DMA enable transmitter                     */
#define UART_CR3_RTSE_POS                        (8U)
#define UART_CR3_RTSE_MASK                       (0x1UL << UART_CR3_RTSE_POS)                       /**< 0x00000100 */
#define UART_CR3_RTSE                            UART_CR3_RTSE_MASK                                 /**< RTS enable */
#define UART_CR3_CTSE_POS                        (9U)
#define UART_CR3_CTSE_MASK                       (0x1UL << UART_CR3_CTSE_POS)                       /**< 0x00000200 */
#define UART_CR3_CTSE                            UART_CR3_CTSE_MASK                                 /**< CTS enable                                 */
#define UART_CR3_CTSIE_POS                       (10U)
#define UART_CR3_CTSIE_MASK                      (0x1UL << UART_CR3_CTSIE_POS)                      /**< 0x00000400 */
#define UART_CR3_CTSIE                           UART_CR3_CTSIE_MASK                                /**< CTS interrupt enable                       */
#define UART_CR3_OBS_POS                         (11U)
#define UART_CR3_OBS_MASK                        (0x1UL << UART_CR3_OBS_POS)                        /**< 0x00000800 */
#define UART_CR3_OBS                             UART_CR3_OBS_MASK                                  /**< One sample bit method enable               */
#define UART_CR3_ORED_POS                        (12U)
#define UART_CR3_ORED_MASK                       (0x1UL << UART_CR3_ORED_POS)                       /**< 0x00001000 */
#define UART_CR3_ORED                            UART_CR3_ORED_MASK                                 /**< Overrun disable                            */
#define UART_CR3_DDRE_POS                        (13U)
#define UART_CR3_DDRE_MASK                       (0x1UL << UART_CR3_DDRE_POS)                       /**< 0x00002000 */
#define UART_CR3_DDRE                            UART_CR3_DDRE_MASK                                 /**< DMA disable on reception error             */
#define UART_CR3_LPWKIE_POS                      (22U)
#define UART_CR3_LPWKIE_MASK                     (0x1UL << UART_CR3_LPWKIE_POS)                     /**< 0x00400000 */
#define UART_CR3_LPWKIE                          UART_CR3_LPWKIE_MASK                               /**< Wake up interrupt enable                   */

/* Bits for UART_BRR */
#define UART_BRR_LPUART_POS                      (0U)
#define UART_BRR_LPUART_MASK                     (0xFFFFFUL << UART_BRR_LPUART_POS)                 /**< 0x000FFFFF */
#define UART_BRR_LPUART                          UART_BRR_LPUART_MASK                               /**< LPUART baud rate register [19:0]           */
#define UART_BRR_BRR_POS                         (0U)
#define UART_BRR_BRR_MASK                        (0xFFFFUL << UART_BRR_BRR_POS)                     /**< 0x0000FFFF */
#define UART_BRR_BRR                             UART_BRR_BRR_MASK                                  /**< UART  baud rate register [15:0]            */

/* Bits for UART_ISR */
#define UART_ISR_PE_POS                          (0U)
#define UART_ISR_PE_MASK                         (0x1UL << UART_ISR_PE_POS)                         /**< 0x00000001 */
#define UART_ISR_PE                              UART_ISR_PE_MASK                                   /**< Parity rrror                               */
#define UART_ISR_FE_POS                          (1U)
#define UART_ISR_FE_MASK                         (0x1UL << UART_ISR_FE_POS)                         /**< 0x00000002 */
#define UART_ISR_FE                              UART_ISR_FE_MASK                                   /**< Framing rrror                              */
#define UART_ISR_NOISE_POS                       (2U)
#define UART_ISR_NOISE_MASK                      (0x1UL << UART_ISR_NOISE_POS)                      /**< 0x00000004 */
#define UART_ISR_NOISE                           UART_ISR_NOISE_MASK                                /**< Noise detected flag                        */
#define UART_ISR_ORE_POS                         (3U)
#define UART_ISR_ORE_MASK                        (0x1UL << UART_ISR_ORE_POS)                        /**< 0x00000008 */
#define UART_ISR_ORE                             UART_ISR_ORE_MASK                                  /**< OverRun rrror                              */
#define UART_ISR_RXNE_POS                        (5U)
#define UART_ISR_RXNE_MASK                       (0x1UL << UART_ISR_RXNE_POS)                       /**< 0x00000020 */
#define UART_ISR_RXNE                            UART_ISR_RXNE_MASK                                 /**< Read data register not empty               */
#define UART_ISR_TC_POS                          (6U)
#define UART_ISR_TC_MASK                         (0x1UL << UART_ISR_TC_POS)                         /**< 0x00000040 */
#define UART_ISR_TC                              UART_ISR_TC_MASK                                   /**< Transmission complete                      */
#define UART_ISR_TXE_POS                         (7U)
#define UART_ISR_TXE_MASK                        (0x1UL << UART_ISR_TXE_POS)                        /**< 0x00000080 */
#define UART_ISR_TXE                             UART_ISR_TXE_MASK                                  /**< Transmit data register empty               */
#define UART_ISR_CTSIF_POS                       (9U)
#define UART_ISR_CTSIF_MASK                      (0x1UL << UART_ISR_CTSIF_POS)                      /**< 0x00000200 */
#define UART_ISR_CTSIF                           UART_ISR_CTSIF_MASK                                /**< CTS interrupt flag                         */
#define UART_ISR_CTS_POS                         (10U)
#define UART_ISR_CTS_MASK                        (0x1UL << UART_ISR_CTS_POS)                        /**< 0x00000400 */
#define UART_ISR_CTS                             UART_ISR_CTS_MASK                                  /**< CTS flag                                   */
#define UART_ISR_BUSY_POS                        (16U)
#define UART_ISR_BUSY_MASK                       (0x1UL << UART_ISR_BUSY_POS)                       /**< 0x00010000 */
#define UART_ISR_BUSY                            UART_ISR_BUSY_MASK                                 /**< Busy flag                                  */
#define UART_ISR_CMF_POS                         (17U)
#define UART_ISR_CMF_MASK                        (0x1UL << UART_ISR_CMF_POS)                        /**< 0x00020000 */
#define UART_ISR_CMF                             UART_ISR_CMF_MASK                                  /**< Character match flag                       */
#define UART_ISR_LPWK_POS                        (20U)
#define UART_ISR_LPWK_MASK                       (0x1UL << UART_ISR_LPWK_POS)                       /**< 0x00100000 */
#define UART_ISR_LPWK                            UART_ISR_LPWK_MASK                                 /**< Wake up from stop mode flag                */
#define UART_ISR_TEACK_POS                       (21U)
#define UART_ISR_TEACK_MASK                      (0x1UL << UART_ISR_TEACK_POS)                      /**< 0x00200000 */
#define UART_ISR_TEACK                           UART_ISR_TEACK_MASK                                /**< Transmit enable acknowledge flag           */
#define UART_ISR_REACK_POS                       (22U)
#define UART_ISR_REACK_MASK                      (0x1UL << UART_ISR_REACK_POS)                      /**< 0x00400000 */
#define UART_ISR_REACK                           UART_ISR_REACK_MASK                                /**< Receive enable acknowledge flag            */

/* Bits for UART_ICR */
#define UART_ICR_PECF_POS                        (0U)
#define UART_ICR_PECF_MASK                       (0x1UL << UART_ICR_PECF_POS)                       /**< 0x00000001 */
#define UART_ICR_PECF                            UART_ICR_PECF_MASK                                 /**< Parity error clear flag                    */
#define UART_ICR_FECF_POS                        (1U)
#define UART_ICR_FECF_MASK                       (0x1UL << UART_ICR_FECF_POS)                       /**< 0x00000002 */
#define UART_ICR_FECF                            UART_ICR_FECF_MASK                                 /**< Framing error clear flag                   */
#define UART_ICR_NOISECF_POS                     (2U)
#define UART_ICR_NOISECF_MASK                    (0x1UL << UART_ICR_NOISECF_POS)                    /**< 0x00000004 */
#define UART_ICR_NOISECF                         UART_ICR_NOISECF_MASK                              /**< Noise error detected clear flag            */
#define UART_ICR_ORECF_POS                       (3U)
#define UART_ICR_ORECF_MASK                      (0x1UL << UART_ICR_ORECF_POS)                      /**< 0x00000008 */
#define UART_ICR_ORECF                           UART_ICR_ORECF_MASK                                /**< OverRun error clear flag                   */
#define UART_ICR_TCCF_POS                        (6U)
#define UART_ICR_TCCF_MASK                       (0x1UL << UART_ICR_TCCF_POS)                       /**< 0x00000040 */
#define UART_ICR_TCCF                            UART_ICR_TCCF_MASK                                 /**< Transmission complete clear flag           */
#define UART_ICR_CTSCF_POS                       (9U)
#define UART_ICR_CTSCF_MASK                      (0x1UL << UART_ICR_CTSCF_POS)                      /**< 0x00000200 */
#define UART_ICR_CTSCF                           UART_ICR_CTSCF_MASK                                /**< CTS interrupt clear flag                   */
#define UART_ICR_CMCF_POS                        (17U)
#define UART_ICR_CMCF_MASK                       (0x1UL << UART_ICR_CMCF_POS)                       /**< 0x00020000 */
#define UART_ICR_CMCF                            UART_ICR_CMCF_MASK                                 /**< Character match clear flag                 */
#define UART_ICR_LPWKCF_POS                      (20U)
#define UART_ICR_LPWKCF_MASK                     (0x1UL << UART_ICR_LPWKCF_POS)                     /**< 0x00100000 */
#define UART_ICR_LPWKCF                          UART_ICR_LPWKCF_MASK                               /**< Wake up from stop mode clear flag          */

/* Bits for UART_RDR */
#define UART_RDR_RDR_POS                         (0U)
#define UART_RDR_RDR_MASK                        (0x1FFUL << UART_RDR_RDR_POS)                      /**< 0x000001FF */
#define UART_RDR_RDR                             UART_RDR_RDR_MASK                                  /**< RDR[8:0] bits (Receive data value)         */

/* Bits for UART_TDR */
#define UART_TDR_TDR_POS                         (0U)
#define UART_TDR_TDR_MASK                        (0x1FFUL << UART_TDR_TDR_POS)                      /**< 0x000001FF */
#define UART_TDR_TDR                             UART_TDR_TDR_MASK                                  /**< TDR[8:0] bits (Transmit data value)        */

/* Bits for UART_PRESC */
#define UART_PRESC_PRESCALER_POS                 (0U)
#define UART_PRESC_PRESCALER_MASK                (0xFUL << UART_PRESC_PRESCALER_POS)                /**< 0x0000000F */
#define UART_PRESC_PRESCALER                     UART_PRESC_PRESCALER_MASK                          /**< PRESCALER[3:0] bits (Clock prescaler)      */
#define UART_PRESC_PRESCALER_DIV1                (0x0UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000000 Input clock devided by 1        */
#define UART_PRESC_PRESCALER_DIV2                (0x1UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000001 Input clock devided by 2        */
#define UART_PRESC_PRESCALER_DIV4                (0x2UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000002 Input clock devided by 4        */
#define UART_PRESC_PRESCALER_DIV6                (0x3UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000003 Input clock devided by 6        */
#define UART_PRESC_PRESCALER_DIV8                (0x4UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000004 Input clock devided by 8        */
#define UART_PRESC_PRESCALER_DIV10               (0x5UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000005 Input clock devided by 10       */
#define UART_PRESC_PRESCALER_DIV12               (0x6UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000006 Input clock devided by 12       */
#define UART_PRESC_PRESCALER_DIV16               (0x7UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000007 Input clock devided by 16       */
#define UART_PRESC_PRESCALER_DIV32               (0x8UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000008 Input clock devided by 32       */
#define UART_PRESC_PRESCALER_DIV64               (0x9UL << UART_PRESC_PRESCALER_POS)                /**< 0x00000009 Input clock devided by 64       */
#define UART_PRESC_PRESCALER_DIV128              (0xAUL << UART_PRESC_PRESCALER_POS)                /**< 0x0000000A Input clock devided by 128      */
#define UART_PRESC_PRESCALER_DIV256              (0xBUL << UART_PRESC_PRESCALER_POS)                /**< 0x0000000B Input clock devided by 256      */
/**
* @}
*/

#ifdef __cplusplus
}
#endif /* __cplusplus */

/**
* @}
*/

/**
* @}
*/

#endif /* CIU32F032_H */
